JPH0523254U - Memory circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if an error occurs in the data storage memory of the computer, only the corresponding address is switched to the data storage memory of another system, and a storage circuit that can continue the processing of the computer is obtained. [Arrangement] A main system and a sub system data storage memories 3a and 3b for storing data information and a parity storage memory 6 are arranged. A parity checker 12 for arranging the correctness of information based on the information in the main system data storage memory 3a and the parity storage memory 6 when a read request is issued is arranged. A selector 14 is arranged to transfer main system information when the identification result is normal and subordinate information to the CPU 1 when the identification result is abnormal. [Effect] Even if an abnormality occurs in the main system data storage memory 3a, the processing of the CPU 1 can be continued.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory circuit that strongly requires the reliability of stored data and that requires continuity of processing even when a temporary error or a permanent failure occurs during memory storage.

[0002]

[Prior Art]

 FIG. 3 is a diagram showing a method of detecting a logic inversion error in a memory circuit according to a conventional parity check method. In the figure, 1 is a CPU for executing an operation, 2 is an information output bus for outputting data information such as an operation result, 3a is a data storage memory for storing the data information of the information output bus 2, and 4 is an information output bus 2. A parity generator 5 for generating parity data based on the data information is parity information output from the parity generator 4. Whether the parity generator 4 is odd or even parity is set in advance by the system. Reference numeral 6 is a parity storage memory for storing the parity information 5, 7 is an address bus for determining at which address of the data storage memory 3a and the parity storage memory 6 the information is stored, 8 is a write signal from the CPU 1, and 9 is a write signal. Is a read signal from the CPU 1, 10a is an information input bus for inputting data information from the data storage memory 3a to the CPU 1 when the read signal 9 is generated, and 11 is output from the parity storage memory 6 when the read signal 9 is generated. Parity information, 12 is a parity checker for identifying whether the data information is normal or abnormal based on the information input bus 10a and the parity information 11, and 13 is an error signal for notifying the CPU 1 of the abnormality according to the result of the parity checker 12.

Next, the operation will be described. FIG. 4 shows the timing of writing data information from the CPU 1 to the data storage memory 3a. FIG. 5 shows the timing of reading information from the data storage memory 3a.

First, a data information writing method will be described with reference to FIG. When the CPU 1 executes the calculation, the CPU 1 outputs the corresponding address information to the address bus 7 at the timing of t1 in order to store the calculation result in the data storage memory 3a. One write cycle is from t1 to t4. At t2, the write signal 8 is output, and at the same time, the data information is output to the information output bus 2. This information is also input to the parity generator 4 to generate the parity information 5. The data information of the information output bus 2 and the parity information 5 are stored in the data storage memory 3a and the parity storage memory 6 at the trailing end t3 of the write signal 8, respectively.

Next, a data information reading method will be described with reference to FIG. The CPU 1 reads data information from the data storage memory 3a prior to executing the operation. At t5, the corresponding address of the data storage memory 3a is output to the address bus 7. One read cycle is from t5 to t8. When the read signal 9 is output at t6, the data storage memory 3a and the parity storage memory 6 designated by the address bus 7 output the corresponding data information as the information input bus 10a and the parity information 11. These two pieces of information are input to the parity checker 12 to discriminate between normal and abnormal. This identification is performed at t7. When the error signal 13 is at H level, that is, normal, the processing of the CPU 1 is continued. If the error signal 13 is L level, that is, if there is an abnormality, the abnormality information is transferred to the CPU 1 and the processing of the CPU 1 is stopped.

[0006]

[Problems to be solved by the device]

 The error detection method using the parity check method as described above has a problem in that when an error occurs during reading of data information, the processing of the CPU 1 cannot be continued and must be stopped.

The present invention has been made to solve such a problem, and an object thereof is to be able to continue processing even when an error occurs in the data storage memory 3a and a parity abnormality is identified at the time of data reading. There is.

[0008]

[Means for Solving the Problems]

 In the storage circuit according to the present invention, two data storage memories for storing data information from the CPU 1 are arranged as a master system and a slave system, and when the write request by the write signal 8 from the CPU 1 requests the same data information at the same time. And a slave data storage memory, and at the same time, this data information is input to the parity generator 4 to generate the parity information 5, which is then written to the parity storage memory 6, and the read request by the read signal 9 from the CPU 1 At times, the data information and parity information 11 at the corresponding address are simultaneously read from the master and slave data storage memories and the parity storage memory 6, and the master data information and parity information 11 are input to the parity checker 12. Identifies normal or abnormal, and if normal, data information of main system Remains transferred to CPU1, when abnormalities Ru der those to be forwarded to CPU1 is switched by the selector data only information in the data read cycle.

[0009]

[Action]

 As described above, two data storage memories for storing data information are configured as a master system and a slave system, and when the data information is read from the CPU 1, an abnormal state of the master system is identified by the parity checker 12, and an abnormality has occurred. In this case, by switching to the data information output from the slave data storage memory during the read cycle, the operation can be continued without interruption.

[0010]

【Example】

 Example 1. FIG. 1 shows an embodiment of the present invention, and 1 to 13 are exactly the same as the above-mentioned conventional circuit. The data storage memory 3a functions as a main system. 3b is a subordinate data storage memory, 10b is an information input bus for inputting data information from the data storage memory 3b to the CPU 1, 14 is a selector for selecting the information input bus 10a or 10b, and 10c is selected by the selector 14. It is an information input bus for transferring the information input bus 10a or 10b to the CPU 1.

Next, the operation will be described. The timing of writing the data information from the CPU 1 to the data storage memories 3a and 3b is basically the same as in FIG. 4 of the conventional example. The difference is that the information output bus 2 is connected to the data storage memories 3a and 3b, and the same data information can be written simultaneously by the write signal 8. FIG. 2 shows the timing of reading data information from the data storage memories 3a and 3b according to this idea.

A data information reading method will be described with reference to FIGS. 1 and 2. In the figure, the selector 14 normally selects the information input bus 10a.

The CPU 1 reads data information from the data storage memories 3a and 3b prior to execution of calculation. At t5, the corresponding addresses of the data storage memories 3a and 3b are output to the address bus 7. One read cycle is from t5 to t8. When the read signal 9 is output at t6, the corresponding data information is output to the information input buses 10a and 10b and the parity information 11 by the data storage memories 3a and 3b designated by the address bus 7 and the parity storage memory 6. The information input bus 10a and the parity information 11 are input to the parity checker 12 to discriminate normality or abnormality. This identification is performed immediately after t6 and until t7. When the error signal 13 shown in FIG. 2A is H level, that is, when the data is normal, the data information of the information input bus 10a is output to the information input bus 10c via the selector 14 and input to the CPU 1 for processing. Will continue. If the error signal 13 shown in FIG. 2B is at L level, that is, if the data information of the information input bus 10a is abnormal, the selector 14 is switched by the error signal 13 and the information input bus 10b becomes the information input bus 10c. It will be input to the CPU 1. In the next cycle of the read signal 9, the same processing as described above is repeated, and when there is no abnormality in the information output bus 10a, the data information is transferred to the CPU 1 as the information input bus 10c.

By configuring the data storage memories 3a and 3b as described above, even if an abnormality occurs in the data storage memory 3a of the master system, the data storage memory 3b of the slave system can be used as a backup to continue the processing. it can.

In the above description, a method of using the present invention in a memory circuit that requires high reliability has been described. However, it is applied to a data register of an input / output circuit that requires similar reliability. Good.

[0016]

[Effect of the device]

 Since the present invention is configured as described above, there is an effect that the processing of the CPU 1 can be continued without interruption unless an abnormality occurs at the same address of the data storage memories 3a and 3b at the same time.

[Brief description of drawings]

FIG. 1 is a memory circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of a memory circuit showing an embodiment of the present invention.

FIG. 3 is a diagram showing a conventional memory circuit.

FIG. 4 is a diagram showing an operation timing when writing data in a conventional memory circuit.

FIG. 5 is a diagram showing an operation timing when reading data from a conventional memory circuit.

[Explanation of symbols]

 1 CPU 3a Data storage memory 3b Data storage memory 4 Parity generator 6 Parity storage memory 7 Address bus 8 Write signal 9 Read signal 12 Parity checker 14 Selector

Claims (1)

[Scope of utility model registration request] 1. A CPU for executing an operation, two data storage memories for a main system and a sub system for simultaneously recording data information output from the CPU according to a write signal from the CPU, C
A parity generator that generates parity information based on data information from the PU, a parity storage memory that stores parity information output from the parity generator,
A parity checker that checks the correctness of the data information from the data information output from the main system data storage memory and the parity information output from the parity storage memory according to the read signal from the CPU. It is composed of a selector that transfers the data information of the system to the CPU, and transfers the data information that is output from the slave system at the same time to the CPU when the result of the parity check is abnormal. When the data information stored in the primary and secondary data storage memories and the parity information stored in the parity storage memory are read at the same time, and the main system data information and parity information are checked by the parity checker, it is normal. Outputs the main system information to the CPU as it is by the selector,
A storage circuit characterized in that when it is abnormal, the selector is switched from the master system to the slave system by an error signal output from the parity checker, and the slave system data information is transferred to the CPU only when the error signal is generated.