JP3214551B2 - Conflict detection failure diagnosis method, conflict detection failure diagnosis method, bus converter, and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a high-order CPU (ce
The present invention relates to a method and a method for diagnosing a failure in contention detection inside a bus converter in a multiprocessor system in which a bus converter having a mechanism for storing a state of a cache of a central processing unit (CPU) connects a CPU and a shared bus.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a multiprocessor system in which a shared bus and a CPU are connected by a bus converter.

In FIG. 3, CPUs 201 and 205 have caches 202 and 206, respectively. These CPUs 201 and 205 are connected to local buses 210 and 21.
1 are connected to the bus converters 203 and 207, respectively, and are connected to the shared bus 212 via these bus converters. A memory 209 as a main storage device is connected to the shared bus 212, and each CPU 2
01 and 205 can access the memory 209 via the shared bus 212.

The bus converters 203 and 207 have tag memories 204 and 208, respectively. These tag memories 204 and 208 store the upper CPU 20 respectively.
The statuses of the caches 202 and 206 of the first and second 205 are recorded. These bus converters 203 and 207 register the corresponding memory addresses in the tag memory at the timing when the higher-level CPU issues a “memory READ instruction” issued to the local bus to the shared bus.
The memory address of the data existing in the cache can be determined.

Next, the operation of the multiprocessor system will be described. Here, a case will be described where the CPU 201 issues a memory READ instruction to acquire data from the memory 209, and processes the content of the acquired data in the own cache 202.

When the contents of the data obtained by the CPU 201 are processed in the own cache 202, the contents of the data (data corresponding to the processed data) stored in the memory 209 become old, and the other CPU 205 When the CPU 201 issues a “memory READ instruction” to an address corresponding to, the CPU 201 must return data (processed data) existing in the cache 202 of the CPU 201 to the memory 209. Therefore, the bus converter 203 on the shared bus 212
5 issued on the shared bus 212
The index in the own tag memory 204 is read by the “command”, and the memory address registered in the own tag memory 204 and the shared bus 212 are read.
When the address of the “memory READ instruction” issued above matches, the cache 2
02, it is determined that the data of the corresponding memory address exists, and this memory READ instruction is issued on the local bus 210. At this time, the bus converter 203 deletes the registration of the corresponding memory address from its own tag memory 204.

The bus converter 203 is connected to the local bus 20
CPU that has received the memory READ instruction issued on 3.
201 checks whether the corresponding data exists in its own cache 202.

If the corresponding data does not exist, or if the corresponding data exists but the data is unprocessed data, the corresponding data is deleted from the cache 202 and Notify the bus converter 203 that there is no data to be performed. Bus converter 2 receiving notification from host CPU 201 that there is no corresponding data in cache 202
03 notifies this to the bus converter 207 of the READ request source. After receiving this notification, the bus converter 207 that has issued the READ request
The data read from the memory 209 is returned to the CPU 205 by the memory READ instruction issued by the 205.

On the other hand, if the own cache 202 has processed data of the corresponding memory address, the CPU 201 issues a “cache to cache WRITE instruction” on the local bus 210. "Cache to cache WRIT" on local bus 210
The bus converter 203 that has received the “E instruction” places “cache to cache WR” on the shared bus 212 as it is.
ITE instruction ". When a “cache to cache WRITE instruction” is issued on the shared bus 212,
At the same time as the content of the memory 209 is updated by the instruction, the instruction is transmitted to the bus converter 207 of the request source.
And the upper C
The updated data is returned to the PU 205.

With the above operation, the latest information is always stored in the memory 209, and each CPU can acquire the latest information.

In the case of this multiprocessor system, for example, the CPU 201 may independently write back the processed data in its own cache 202 to the memory 209 by a “memory WRITE instruction” (in this case,
As in the case of the “cache to cache WRITE instruction”, the transfer of the update data to another CPU is not performed. ). In this case, the CPU 201 executes the “WRITE instruction”
Is issued, and the bus converter 203
When another CPU 205 issues a “memory READ instruction” of the same memory address on the shared bus 212 while issuing the “RITE instruction” on the shared bus 212,
A conflict between the “memory WRITE instruction” and the “memory READ instruction” occurs, and the “memory W
It is necessary to change the "RITE instruction" to the "cache to cache WRITE instruction" as described above.

The contention check as described above is performed by the contention detection circuit provided inside the bus converter.
This is performed by comparing the addresses of the “ITE instruction” and “memory READ instruction”. If the contention detection circuit fails, normal data is not returned to the source of the memory READ instruction, causing data corruption and a failure to recognize the failure. The circuit is duplicated, and if the comparison results do not match, a method of determining a failure is used. FIG.
The specific configuration is shown in FIG.

In FIG. 4, the CPU 301 and the shared bus 3
11 is connected to the upper CPU
It has a tag memory 310 in which the state of the cache 302 of 301 is recorded. The bus converter 303 internally stores the “memory WR” issued from the host CPU 301.
ITE instruction "and" memory RE issued from another CPU "
A duplicate conflict detection circuit 305, 307 for comparing the address with the "AD instruction", and a failure detection circuit 3 which receives the address comparison results of these detection circuits as inputs, and determines a failure when the comparison results do not match as a failure.
06, a buffer 304 for storing an instruction received from the CPU 301, a buffer 308 for storing an instruction issued from another CPU on the shared bus 311, and a tag memory for controlling registration / deletion of an address in the tag memory 310. And a control circuit 309.

In the bus converter 303, the CPU 3
01 is stored in the buffer 304 until it is issued to the shared bus 311. Buffer 30
4 issues a “memory READ instruction” to the shared bus 311, the corresponding memory address is registered in the tag memory 310 by the tag memory control circuit 309, and the data of the corresponding memory address is stored in the cache of the upper CPU. Record the presence of

When a "memory READ instruction" is issued from the other CPU on the shared bus 311, the tag memory 310 is indexed by the tag memory control circuit 309, and the address of the "memory READ instruction" is registered. Check if there is. When the address of the “memory READ instruction” is registered in the tag memory 310, the “memory READ instruction” is stored in the buffer 308.
At this time, the tag memory control circuit 309 deletes the registration information of the corresponding memory address from the tag memory 310.

The “memory RE” stored in the buffer 308
When the "AD command" is issued on the local bus 312, the CPU 301 receiving the "AD command" issues a "cache to cache WRITE command" and transfers the corresponding data (processed data) from the cache 302.

If the CPU 301 issues a "memory WRITE instruction" at an address corresponding to the memory address before issuing the "memory READ instruction" stored in the buffer 308 to the local bus 312,
The following conflict check is performed. First, the CPU 30
1 issues a “memory WRITE instruction” in the buffer 30
4 is stored. Then, the conflict detection circuit 305 compares the address of the “memory WRITE instruction” stored in the buffer 304 with the address of the “memory READ instruction” stored in the buffer 308, and only when the addresses match, the “memory WRITE instruction”. Is "cache to
Cache WRITE instruction ".

In the bus converter 303, the conflict detection circuit B307 performs the same address comparison as that of the conflict detection circuit 305, and the result of the comparison is the failure detection circuit 3.
Checked by 06. The failure detection circuit 306
If the comparison results do not match, it is determined that the conflict detection circuit has failed.

[0019]

However, in the above-mentioned prior art, since a circuit failure is detected by duplicating the conflict detection circuit inside the bus converter, the circuit scale inside the bus converter is large. There was a problem that it would be.

An object of the present invention is to provide a failure diagnosis method, a failure diagnosis method, and a bus converter which can easily diagnose a failure of a conflict detection circuit inside the bus converter and can reduce the circuit scale of the bus converter. Is to do. Another object of the present invention is to provide a recording medium for executing such a failure diagnosis process.

[0021]

In order to achieve the above object, according to the conflict detection / diagnosis method of the present invention, a plurality of central processing units are connected to a main storage unit via a shared bus, and the plurality of central processing units are connected to a main storage unit. And a shared bus, a bus converter having a tag memory for storing the state of a cache of a higher-level central processing unit is provided. Each of the converters performs a write instruction issued from a higher-level central processing unit to update data in the main storage device and a read instruction issued from another central processing unit to read data from the main storage device. Contention detection means for issuing a predetermined instruction on the shared bus in place of the write instruction when detecting a contention with the read instruction,
When receiving a read command from the upper central processing unit to read data from the main storage device, the memory address of the data read by the read instruction is registered in its own tag memory, and the other central processing unit When a read command to read data from the main storage device is issued on the shared bus, it is checked whether the memory address of data read by the read command is registered in its own tag memory, If registered, the read instruction is notified to the upper central processing unit to transfer the corresponding data to the main storage device, and delete the memory address of the data from the own tag memory. Tag memory control means, the tag memory control means, from another central processing unit on the shared bus, When a write instruction to update data stored in the main storage device is issued, it is checked whether the same memory address as the memory address of the data updated by the write instruction is registered in its own tag memory. And if it is registered, it is diagnosed that the conflict detection function of the bus converter issuing the write instruction is out of order.

In the conflict detection failure diagnosis method according to the present invention, a plurality of central processing units are connected to a main storage device via a shared bus, and a higher order central processing unit is connected between the plurality of central processing units and the shared bus. Write instructions for updating the data of the main storage device issued by a higher-level central processing unit, each of the bus converters being connected by a bus converter having a tag memory for storing the state of the cache Detecting a conflict with a read instruction issued from another central processing unit for reading data from the main storage device, and issuing a predetermined instruction on the shared bus instead of the write instruction. A method for diagnosing conflict detection failures performed in a multiprocessor system comprising: When a read command to read data from the main storage device is received from the device, the memory address of the data read by the read command is registered in its own tag memory, and the data is read from the other central processing unit onto the shared bus. When a read command for reading data from the main storage device is issued, it is checked whether or not the memory address of the data read by the read command is registered in its own tag memory. In such a case, the upper central processing unit is notified of the read instruction and the corresponding data is transferred to the main storage device, and the memory address of the data is deleted from the own tag memory, The memory address of the write instruction issued on the shared bus is a bus converter other than the source of the write instruction. If you registered in any of the tag memory, and wherein the diagnosing and conflict detection functions of the write command issuing bus converter has failed.

The bus converter according to the present invention is an upper central processing unit provided between a central processing unit of a multiprocessor system in which a plurality of central processing units are connected to a main storage device via a shared bus and the shared bus. A bus converter having a tag memory for storing the state of the cache of the main storage device, and a write instruction issued from a higher-level central processing unit for updating data in the main storage device and issued from another central processing device. Detecting a conflict with a read instruction for reading data from the main storage device, the conflict detecting means for issuing a predetermined instruction on the shared bus in place of the write instruction; When a read command for reading data from the main storage device is received from the device, a memory address of data read by the read command is received. Registered in its own tag memory, when a read instruction to read data from the main storage device is issued from the other central processing unit onto the shared bus, the memory address of the data read by the read instruction is changed. It checks whether or not it is registered in its own tag memory, and if it is registered, notifies the upper central processing unit of the read instruction and transfers the corresponding data to the main storage device. Tag memory control means for deleting the memory address of the data from its own tag memory, and the tag memory control means is stored in the main storage device on the shared bus from another central processing unit. When a write instruction is issued to update the stored data, the same memory address as the memory address of the data updated by the write instruction is issued. Les performs a check is registered in the own tag memory, when it is registered, characterized in that the diagnosis with the write instruction issuer conflict detection functions of the bus converters is faulty.

In the recording medium of the present invention, a plurality of central processing units are connected to a main storage device via a shared bus, and a cache of a higher-level central processing unit is provided between the plurality of central processing units and the shared bus. A storage medium used in a multiprocessor system provided with a bus converter having a tag memory for storing a state, wherein a read command for reading data from the main storage device from an upper central processing unit is provided. Receiving the instruction, the first processing for registering the memory address of the data read by the read instruction in its own tag memory, and the reading of data from the main storage device onto the shared bus from another central processing unit. Is issued, the memory address of the data read by the read instruction is registered in the tag memory. Check if it is registered, and if it is registered, notify the upper central processing unit of the read instruction to transfer the corresponding data to the main storage device, and from the own tag memory. A second process for deleting a memory address of the data, a write command issued from a higher-level central processing unit for updating data in the main storage device, and a main instruction issued from another central processing device. When detecting a conflict with a read instruction for reading data from the device, the write instruction
A third process of updating the data in the main storage device in place of the above and issuing a predetermined command to return the updated data to the central processing unit that is the source of the read command to the shared bus ;
When a write instruction for updating data stored in the main storage device is issued on the shared bus from another central processing unit, the same memory as the memory address of the data updated by the write instruction is issued. Checking whether the address is registered in its own tag memory, and if it is registered, diagnosing that the contention detection function of the bus converter issuing the write instruction is out of order;
Is recorded on each of the bus converters.

(Operation) In the present invention as described above, when a read command is issued from a higher-level central processing unit, each bus converter registers its memory address in its own tag memory, and the other central processing units. When a read instruction is issued from the device, it is checked whether the memory address is registered in its own tag memory. If the memory address is registered, the read instruction is notified to the upper central processing unit. The corresponding data is transferred to the main storage device, and the memory address of the data is deleted from the own tag memory. As a result, the latest state of the cache of the upper central processing unit is always stored in the tag memory of each bus converter. In this configuration, when a conflict occurs between the write instruction from the host central processing unit and the read instruction from another central processing unit and the conflict detection unit has failed, the write instruction is issued directly on the shared bus. In this case, however, the same memory address as the memory address of the erroneously issued write instruction is always registered in the tag memory of the bus converter that issued the read instruction. Therefore, by checking whether the memory address of the write instruction issued on the shared bus is registered in the tag memory of the bus converter other than the issuer, the failure of the conflict detection function of the write instruction issuer's bus converter is checked. Can be diagnosed.

Further, in the present invention, only one contention detection circuit is required, and there is no need to duplicate the contention detection circuit as in the prior art, so that the circuit scale does not increase.

[0027]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a multiprocessor system to which the conflict detection failure diagnosis method of the present invention is applied. In FIG. 1, a bus converter 103 that connects a CPU 101 and a shared bus 109 has a tag memory 108 in which the state of the cache 102 of the host CPU 101 is recorded.

The bus converter 103 internally includes a “memory WRITE instruction” issued by the host CPU 101.
And a conflict detection circuit 105 for comparing the address of a "memory READ instruction" issued from another CPU to the shared bus 109; a buffer 104 for storing the instruction received from the CPU 101; And a tag memory control circuit 107 for controlling registration / deletion of an address in the tag memory 108.

The conflict detection circuit 105 is connected to the host CPU 10
"Memory WRITE instruction" issued from other CPs and other CPs
When a conflict with the “memory READ instruction” issued from U is detected, the “cache to cache WRITE instruction” is replaced by the “cache to cache WRITE instruction” instead of the “memory WRITE instruction”.
09 is issued.

The tag memory control circuit 107 controls the upper CP
The memory address of the “memory WRITE instruction” issued from U101 is registered in the tag memory 108, and another C
When the PU issues a “memory READ instruction” on the shared bus 109, it checks whether the memory address of the data read by the instruction is registered in its own tag memory. The upper CPU is notified of the read command to transfer the corresponding data, and deletes the memory address of the data from the own tag memory 108. In addition, the tag memory control circuit 107 transmits a shared bus 109 from another CPU.
For the “memory WRITE instruction” issued above, it is checked whether or not the corresponding memory address is registered in the tag memory 108. If the memory address is registered, the contention of the write instruction issuing source bus converter occurs. Diagnose that the detection function has failed.

In the bus converter 103 described above, the CP
The instruction received from U101 is stored in the buffer 104 until it is issued to the shared bus 109. Then, a “memory READ instruction” is sent from the buffer 104 to the shared bus 109.
Is issued, the corresponding memory address is registered in the tag memory 108 by the tag memory control circuit 107, thereby recording that the data of the corresponding memory address exists in the cache of the upper CPU.

When a "memory READ instruction" is issued from another CPU to the shared bus 109, the tag memory 108 is indexed by the tag memory control circuit 107, and the address of the issued "memory READ instruction" is assigned to the tag. It is checked whether it is registered in the memory 108. If the address of the issued “memory READ instruction” is registered, the “memory READ instruction” is stored in the buffer 106.
And deletes the registered information of the corresponding memory address from the tag memory 108. The "memory READ instruction" stored in the buffer 106 is issued to the local bus 110, and the CPU 101 receiving the "memory read instruction"
The cache WRITE instruction causes the cache 10
2 to transfer the corresponding data.

Before issuing the “memory READ instruction” stored in the buffer 106 to the local bus 110,
The CPU 101 stores the data at the corresponding address in “memory W
When issued by the "WRITE instruction", the issued "memory WRITE instruction" is stored in the buffer 104, and the "memory WRITE instruction" stored in the buffer 104 by the conflict detection circuit 105 and the buffer 106. The address is compared with the "memory READ instruction". Only when the comparison result of the addresses in the conflict detection circuit 105 matches, the “memory WR
"ITE instruction" is "cache to cache WRITE"
Instruction ", and the" cache to cache WR "
The data transfer by the "ITE instruction" is performed.

When the conflict detection circuit 105 fails,
The “memory WRITE instruction”, which is to be converted to the “cache to cache WRITE instruction”, is issued on the shared bus 109 as it is. However, in this case, since the corresponding address is always registered in the tag memory of the CPU that issued the “memory READ instruction”,
The bus converter on the CPU side that issued the shared bus 109
The failure of the conflict detection circuit 105 can be detected by indexing the own tag memory with the “memory WRITE instruction” issued above and checking whether the corresponding address is registered. As described above, in the present conflict detection failure diagnosis method, the bus converter connected to each CPU uses the “memory WRITE” issued on the shared bus 109.
Instruction ”, the index of the own tag memory is read, and the“ memory WRIT ”
By checking whether the address corresponding to the "E instruction" is registered, it is possible to diagnose the failure of the conflict detection circuit. (Other Embodiments) In the case of the multiprocessor system as shown in FIG. 1, the recording medium 1 such as a semiconductor memory or a CD-ROM as shown in FIG.
It is also possible to adopt a configuration in which the CPU 20 is connected to the shared bus 109 and the bus converter of each CPU performs data processing according to the program recorded in the recording medium 120. In this case, the recording medium 120 includes the higher-order CP.
When a "memory READ instruction" is received from U, a first process of registering a memory address of data read by the instruction in its own tag memory, and a "memory READ instruction" is issued on the shared bus 109 from another CPU. Then, it is checked whether or not the memory address of the data read by the instruction is registered in its own tag memory. If the memory address is registered, the upper CPU is notified of the “memory READ instruction”. A second process of causing the corresponding data to be transferred and deleting the memory address of the data from the own tag memory;
"Memory WRITE instruction" issued from U and other CP
Upon detecting a conflict with a “memory READ instruction” issued from U, a third process of updating data in the memory (main storage device) and returning the updated data to the CPU that has issued the read instruction, When a "memory WRITE instruction" is issued from the CPU to the shared bus 109, it is checked whether the same memory address as the memory address of the data updated by the instruction is registered in the own tag memory, and the registered memory address is registered. In that case, the "memory WRI
A program for executing the fourth processing for diagnosing that the conflict detection function of the bus converter of the issuer of the “TE instruction” has failed and for each of the bus converters is recorded.

[0036]

According to the present invention configured as described above, the memory address of the "memory WRITE instruction" issued on the shared bus is changed to the address of the bus converter other than the source of the "memory WRITE instruction". It is possible to diagnose whether or not the contention detection function of the bus converter that issued the write instruction has failed by a simple process such as checking whether the content is registered in any of the tag memories.

In addition, according to the present invention, since only one contention detection circuit is provided inside the bus converter, the circuit scale of the bus converter can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a multiprocessor system to which a conflict detection failure diagnosis method of the present invention is applied.

FIG. 2 is a block diagram illustrating an embodiment including a recording medium.

FIG. 3 is a block diagram illustrating an example of a multiprocessor system that connects a shared bus and a CPU with a bus converter.

FIG. 4 is a block diagram showing a conventional multiprocessor system to which a conflict detection failure determination method having a duplicated conflict detection circuit is applied.

[Explanation of symbols]

 101 CPU 102 Cache 103 Bus Converter 104, 106 Buffer 105 Conflict Detection Circuit 107 Tag Memory Control Circuit 108 Tag Memory 109 Shared Bus 110 Local Bus 120 Recording Medium

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G06F 12/08 541 G06F 12/08 541Z 15/177 678 15/177 678A

Claims (8)

(57) [Claims] 1. A plurality of central processing units are connected to a main storage device via a shared bus, and a cache state of an upper central processing unit is stored between the plurality of central processing units and the shared bus. A method of diagnosing a conflict detection failure in a multiprocessor system provided with bus converters each having a tag memory, wherein each of the bus converters stores data of the main storage device issued from an upper central processing unit. When a conflict between a write instruction for performing an update and a read instruction issued from another central processing unit for reading data from the main storage device is detected, a predetermined instruction is shared instead of the write instruction. Contention detection means issued on the bus, and when a read instruction to read data from the main storage device is received from a higher-level central processing unit, When the memory address of the data read by the read instruction is registered in its own tag memory and another central processing unit issues a read instruction on the shared bus to read data from the main storage device. It checks whether the memory address of the data read by the read instruction is registered in its own tag memory, and if it is registered, notifies the higher order central processing unit of the read instruction and Tag memory control means for transferring the data to be transferred to the main storage device and deleting the memory address of the data from its own tag memory, wherein the tag memory control means When a write command to update data stored in the main storage device is issued on the bus, the write command is issued. It checks whether the same memory address as the memory address of the data updated by the instruction is registered in its own tag memory. If the memory address is registered, the conflict detection function of the bus converter that issued the write instruction fails. A conflict detection failure diagnosis method characterized in that it is diagnosed that a failure has occurred. 2. The conflict detection failure diagnosis method according to claim 1, wherein the conflict detection means provided in each of the bus converters updates data in the main storage device issued from a higher-level central processing unit. A conflict detection circuit for comparing an address of a write command to the effect of the fact and a read command issued from another central processing unit to read data from the main storage device. Failure diagnosis method. 3. The conflict detection failure diagnosis method according to claim 2, wherein each of the bus converters stores a write instruction issued from a higher-level central processing unit to update data in the main storage device. And a second buffer for storing a read command issued from another central processing unit for reading data from the main storage device. Tag memory control means checks whether the memory address of a read instruction issued from the other central processing unit issued on the shared bus is registered in its own tag memory, and only when it is registered, A memory address of a read command is stored in the second buffer means, and the contention detection circuit stores the memory address stored in the first and second buffer means. Conflict detection failure diagnosis method, characterized by detecting conflicts by comparing the. 4. A plurality of central processing units are connected to a main storage device via a shared bus, and a state between the plurality of central processing units and the shared bus stores a state of a cache of an upper central processing unit. Each of the bus converters is connected by a bus converter having a tag memory, and each of the bus converters issues a write instruction for updating data of the main storage device issued from a higher-level central processing unit and a command issued from another central processing unit. When a conflict with a read instruction for reading data from the main storage device is detected, a multi-processor system having a function of issuing a predetermined instruction on the shared bus instead of the write instruction is executed. A method of diagnosing a conflict detection failure, wherein each of the bus converters receives data from the main storage device from a host central processing unit. When a read instruction to read the data is received, the memory address of the data read by the read instruction is registered in its own tag memory, and the data from the main storage device is transferred from the other central processing unit onto the shared bus. When a read command for reading is issued, it is checked whether or not the memory address of the data read by the read command is registered in its own tag memory. Notifying the device of the read instruction to transfer the corresponding data to the main storage device, deleting the memory address of the data from the own tag memory, and issuing the data on the shared bus The memory address of the write instruction is registered in one of the tag memories of the bus converters other than the source of the write instruction. If it has, the conflict detection failure diagnosis method, characterized in that the diagnosis and the write instruction issuer conflict detection functions of the bus converters is faulty. 5. The state of a cache of a higher-level central processing unit, which is provided between a central processing unit of a multiprocessor system in which a plurality of central processing units are connected to a main storage device via a shared bus and a shared bus, is provided. A bus converter having a tag memory for storing, comprising: a write command issued from a higher-level central processing unit for updating data in the main storage device; and a main storage issued from another central processing device. Contention detection means for issuing a predetermined instruction on the shared bus in place of the write instruction upon detecting a contention with a read instruction to read data from the device; and When receiving a read command to read data from the device, the memory address of the data read by the read command is registered in its own tag memory, When a read instruction for reading data from the main storage device is issued from the central processing unit on the shared bus, whether the memory address of the data read by the read instruction is registered in its own tag memory It checks whether it is registered, and if it is registered, notifies the upper central processing unit of the read instruction to transfer the corresponding data to the main storage device, and reads the data from its own tag memory. Tag memory control means for deleting the memory address of the memory device, wherein the tag memory control means updates data stored in the main storage device on the shared bus from another central processing unit. When a write instruction is issued, the same memory address as the memory address of the data updated by the write instruction is registered in the own tag memory. Is performed of checks is, if it is registered, a bus converter, characterized in that the diagnosis and the write instruction issuer conflict detection functions of the bus converters is faulty. 6. The bus converter according to claim 5, wherein said contention detecting means includes a write command issued from a higher-level central processing unit to update data in said main storage device and another central processing unit. A bus converter comprising one conflict detection circuit for comparing an address with a read instruction issued to read data from the main storage device issued from the main storage device. 7. The bus converter according to claim 6, wherein the first buffer means stores a write instruction issued from a higher-level central processing unit to update data in the main storage device, and Second buffer means for storing a read command issued from a central processing unit for reading data from the main storage device, wherein the tag memory control means is provided on the shared bus. It is checked whether the memory address of a read instruction issued from another central processing unit is registered in its own tag memory, and only when it is registered, the memory address of the read instruction is changed to the second address. Stored in a buffer means, wherein the conflict detection circuit detects a conflict by comparing memory addresses stored in the first and second buffer means. Bus converter to. 8. A plurality of central processing units are connected to a main storage device via a shared bus, and a cache state of an upper central processing unit is stored between the plurality of central processing units and the shared bus. A recording medium used in a multiprocessor system provided with bus converters each having a tag memory of, when a read command to read data from the main storage device is received from an upper central processing unit, First processing for registering a memory address of data read by a read instruction in its own tag memory, and a read instruction for reading data from the main storage device on the shared bus from another central processing unit is issued. Then, it is checked whether the memory address of the data read by the read instruction is registered in its own tag memory. And if it is registered, notifies the upper central processing unit of the read instruction to transfer the corresponding data to the main storage device, and stores the data from its own tag memory. A second command for deleting the memory address of the main memory, a write instruction issued from a higher-level central processing unit to update the data of the main memory, and a write instruction issued from another central processing unit. Upon detection of a conflict between the read command to the effect that data is read, the write
A third process of updating the data in the main storage device in place of the instruction and issuing a predetermined instruction to return the updated data to the central processing device that is the source of the read instruction to the shared bus; When a write instruction for updating data stored in the main storage device is issued on the shared bus, the same memory address as the memory address of the data updated by the write instruction is assigned to the own tag memory. A fourth process for diagnosing that the contention detection function of the bus converter that has issued the write instruction has failed;
Recording a program that causes each of the bus converters to execute the above.