JPH04302044A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To improve a hit rate, and to shorten a retrieving time by using continuous (n) words as a cache block. CONSTITUTION:A first information table 21 which registers information at each cache block constituted of the continuous (n) words, has an address 211 of the cache block in cache memories 16a and 16b, and information 212 indicating the validity/invalidity of the cache block. A second information table 22 which registers information and data at each word, has information 221 indicating the occupancy/sharing and validity/invalidity of the word, and data 222 of the word. Then, the original valid data can be prevented from being handled as the invalid one, or an invalidation signal can be prevented from being transmitted at the time of writing the previously occupied data. Thus, the hit rate can be improved, and the retrieving time can be shortened.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors each having a shared memory cache device are connected through a bus.

0003

BACKGROUND OF THE INVENTION In multiprocessor systems, access to shared memory is accomplished through a common bus. Since this bus can only be used by one processor at a time, when multiple processors attempt to access the shared memory at the same time, a situation may occur in which one processor is forced to wait for access (an access conflict). To avoid this, a cache device is provided for each processor,
By copying the contents of the shared memory to the memory within the cache device, memory accesses by the processor are limited to accesses to the cache device and accesses to the bus are suppressed. In this case, the contents of the same address may be held in multiple cache devices,
It is necessary to maintain the consistency of the contents of these same addresses. Therefore, the memory in the cache device is divided into multiple areas (
Each cache unit is divided into cache units), and the state of whether it is occupied or shared, or whether it is valid or invalid, is maintained for each cache unit.
When e is executed, this cache unit is occupied, and an instruction to invalidate the cache units of other processors containing the same address is transmitted via the bus, making them invalid. This is called a write-invalid type. When a write is performed to the cache of one processor, a write is performed to the cache of another processor.
A method called a write-update type is used, in which content is transmitted via a bus and parts containing the same address are updated.

At this time, when reading a program or initializing data assigned to consecutive addresses, there is a high possibility that after accessing a certain address, the subsequent address will be accessed. From this, the hit rate improves and the access efficiency increases when the cache block size is large and one cache block includes a plurality of consecutive words.

However, when multiple processors frequently access different words in the same block, each time one processor writes data, the entire corresponding cache block of the other processors becomes invalid, and the word itself becomes invalid. Even though it is valid, it becomes invalid. Furthermore, if the cache block is made smaller, problems such as an increase in the area for storing cache block information such as addresses and states, and a decrease in efficiency when accessing continuous areas arise.

[0006] Conventionally, therefore, a cache block is made small, such as a word, which is the unit of access, and when an address that is not in the cache device is read, several words worth of space between the shared memory and the cache device are used. Read successive words from the buffer, and on subsequent reads,
If the desired data is in this buffer, methods have been used to read from this buffer without going to main memory to read it, thereby reducing access to the bus and increasing the hit rate including the buffer. Ta.

[0007]

[Problems to be Solved by the Invention] However, even with this method, there is an increase in cache block information, an increase in search time,
These problems are not solved, and there is also the problem that processing to guarantee the validity/invalidity of data in the buffer increases.

[0008] The present invention has been developed in response to these circumstances, and at the same time aims to improve the hit rate and shorten search time, and at the same time, prevents the situation where originally valid data is invalidated. The purpose is to provide a multiprocessor system that can.

[Configuration of the invention]

0010

[Means for Solving the Problems] In order to achieve the above object, a multiprocessor system of the present invention is configured by connecting a shared memory and a plurality of processors each having a cache device for the shared memory to a bus. In the multiprocessor system, the cache device of the processor includes means for holding, for each cache block consisting of n consecutive words, information as to whether or not all the words in the cache block are valid; For each word in the cache block, if all the words in the cache block are valid, information on whether the word is exclusive or shared; if not all the words in the cache block are valid, information on whether the word is valid or invalid. It is characterized by having a means for holding.

[0011]

[Operation] In the present invention, by using n consecutive words as a cache block, it is possible to improve the hit rate and shorten the search time. and information indicating for each word whether it is occupied or shared when all the words in the cache block are valid, or whether it is valid or invalid when all the words in the cache block are not valid. This makes it possible to avoid treating originally valid data as invalid or sending an invalidation signal when writing data that is already occupied.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, details of embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing the configuration of a multiprocessor system according to an embodiment of the present invention. As shown in the figure, this multiprocessor system is constructed by connecting a plurality of processors 11a, 11b and a shared memory 12 through a common bus 13, respectively. however,
Each processor 11a, 11b has a shared memory 1
Cache devices 14a, 14 that copy and hold the contents of 2.
It is connected to bus 13 via b. Each cache device 14a, 14b is composed of a cache controller 15a, 15b and a cache memory 16a, 16b, respectively.

Further, as shown in FIG. 2, the cache controllers 15a and 15b of each cache device 14a and 14b have a first information table 21 for registering information for each cache block consisting of n consecutive words, and a first information table 21 for registering information for each cache block consisting of n consecutive words. Second information table 2 for registering information and data
2. The first information table 21 includes addresses 211 of cache blocks in the cache memories 16a and 16b and information 212 indicating validity/invalidity of the cache blocks. The second information table 22 also includes information 221 indicating occupancy/sharing of a word, information 221 indicating validity/invalidity, and data 22 of the word.
It consists of 2.

Next, in the multiprocessor system of this embodiment, each cache device 1 when access (write operation or read operation) is performed by each processor 11a, 11b according to the access pattern shown in FIG.
The operations of 4a and 14b will be explained.

Incidentally, FIG. 4 shows the initial state of each information table 21, 22 of each processor 11a, 11b.

First, in step 1 of FIG. 3, when a read access to address 100 occurs in the processor 11a, as shown in FIG.
The cache controller 15a, which has received a read access from , refers to the first information table 21 to check whether a cache block including the read address exists in the cache memory 16a (step 501). Then, 100, which is the start address of the cache block including the address 100, is stored in the first information table 21.
Since it is not registered in the cache block, the cache block data starting from address 100 is read and registered (step 509). Here, the start address of the cache block is determined by (address of word to be accessed) - (address of word mod cache block size). This entire cache block is then validated (step 510) and all words are shared (
Step 511). Finally, the data of this word is passed to the processor 11a (step 508).

On the other hand, the re issued with the block read
The cache controller 15a that detected the ad signal,
As shown in FIG. 6, it is checked whether a cache block including address 100 is registered in the first information table 21 (step 601). In this case, since the corresponding block does not exist, nothing is done. As a result, each of the information tables 21 and 22 is updated to the contents shown in FIG.

Next, in step 2 of FIG. 3, when a read access to address 101 occurs in the processor 11a, the cache controller 15a that has received the read access from the processor 11a performs step 1.
Similarly, as shown in FIG.
The cache block containing 1 is the cache memory 16a.
It is checked whether it exists (step 501). in this case,
Since the corresponding cache block exists and the entire cache block is valid (step 502
), the data at the read address 101 existing in the cache memory 16a is passed to the processor 11a (step 508). In this step, each information table 21
, 22 remain unchanged.

Next, in step 3 of FIG. 3, when a read access to address 100 occurs in the processor 11b, the cache controller 15b that received the read access from the processor 11b performs the following steps as shown in FIG. , read address 10
The cache block containing 0 is the cache memory 16b.
It is determined that the cache block does not exist at address 100 (step 501), the data for the cache block starting from address 100 is block read, and this is registered (step 509).
. Then, this entire cache block is made valid (step 510), and all words are shared (step 511).
). Finally, the data of this word is passed to the processor 11b (step 508).

On the other hand, the re issued with the block read
The cache controller 15a that detected the ad signal,
As shown in FIG. 6, although it has been confirmed that a cache block including address 100 is registered in the first information table 21 (step 601) and that the entire cache block is valid (step 602), Because the word (address 100) is not occupied (step 6
03), no processing is performed in this case. As a result, the contents of each information table 21, 22 are updated as shown in FIG.

Steps 4 to 8 in FIG. 3 are processed in exactly the same way as step 2, and each information table 21, 2
There is no change in the contents of 2.

The next step 9 is also processed in the same way as step 1, and as a result, each information table 21, 2
The contents of 2 are updated as shown in FIG.

Further, in step 10, the same processing as in step 3 is performed, and as a result, the contents of each information table 21, 22 are updated as shown in FIG.

Next, in step 11 of FIG. 3, when a write access to address 100 occurs in the processor 11a, a write access is issued from the processor 11a.
The cache controller 15a that received the access determines that the cache block including the write address 100 exists in the cache memory 16a (step 1101) and that the entire cache block is valid, as shown in FIG. Step 110
2) Since the word at address 100 is not occupied (step 1106), an invalidation signal is sent to the bus 13 for address 100 (step 1107), and the word is made occupied (step 1108). Finally, the corresponding word portion of the cache memory 16a is updated with the data passed from the processor 11a (step 1109).

On the other hand, the cache controller 15b that has detected the invalidation signal from the bus 13 checks that the cache block containing the address 100 is registered in the first information table 21 (step 120), as shown in FIG.
1), further confirming that the entire cache block is valid (step 1202), and assuming that all words of the cache block are not valid (step 120).
3) Disable the word (address 100) and enable the other words (addresses 101, 102, 103) (step 1204). As a result, each information table 2
1 and 22 are updated as shown in FIG.

Next, in step 12 of FIG. 3, when a read access to the address 101 occurs in the processor 11b, the cache controller 1 that received the read access
5b, as shown in FIG. 5, a cache block exists in the cache memory 16a from address 100 including read address 101 (step 501), and although this entire cache block is not valid (step 5
02), the word at address 101 is valid (step 503), so the word r existing in the cache memory 16a
The data at the ead address 101 is passed to the processor 11b (step 508). In this step, there is no change in each information table 21, 22.

After this, in step 13 of FIG. 3, the processor 11b also executes wri for address 101.
When a te access occurs, the cache controller 15b that receives it performs a write access, as shown in FIG.
Although the cache block containing address 101 exists in the cache memory 16b (step 1101
), the entire cache is not valid (step 1
102), reads the word at address 100, which is an invalid word in the cache block (step 1103).
). Then, an invalidation signal is sent to address 101 (step 1104), and the word of address 101 is occupied and the words of other addresses 100, 102, and 103 are shared (step 1105). Finally, the corresponding word portion of the cache memory 16b is transferred to the processor 11b.
It is updated with the data passed from (step 1109).

On the other hand, the cache controller 15a that has detected the invalidation signal registers the cache block including the address 101 in the first information table 21 (step 1201), as shown in FIG. After confirming that the cache block is valid (step 1202), all words in the cache block are considered invalid (step 1203), the word (address 101) is invalidated, and the other words (address 100) are invalidated.
, 102, 103) (step 1204)
. As a result, the information tables 21 and 22 are updated to the contents shown in FIG. 14.

Step 14 in FIG. 3 is the same as step 12, in which the cache memory 1 of the own processor 11a is
Read from 6a.

In step 15 of FIG. 3, when a write access to the address 102 occurs in the processor 11b, the cache controller 1 that received the write access
5b, as shown in FIG. 11, write address 1
The cache block containing 02 is cache memory 16
b (step 1101), and the entire cache block is valid (step 1102).
, since the word at address 102 is shared (step 1
106), sends an invalidation signal to the address 102 (step 1107), makes this word exclusive (step 1108), and updates the corresponding word portion of the cache memory 16b with the data passed from the processor 11b (step 1109).

On the other hand, as shown in FIG. 12, the cache controller 15a detecting the invalidation signal registers the cache block including the address 102 in the first information table 21 (step 1201). Since the whole is not valid (step 12
02), invalidate the word (address 102) (step 1205). As a result, information tables 21 and 22
The contents of are updated as shown in FIG.

Next, in step 16 of FIG. 3, when a read access to the address 101 occurs in the processor 11a, the cache controller 1 that received the read access
5a is the read address 10 as shown in FIG.
The cache block containing 1 is the cache memory 16a.
(step 501), but this entire cache block is not valid (step 502) and the word at address 101 is invalid (step 503).
), reads the word at address 101 and re
An ad signal is sent (step 504), and the word is made valid (step 505). However, at this stage, all the words in the cache block starting from address 100 including this word are not valid, so the entire information in the cache block remains invalid (step 506). The last read data is passed to the processor 11a (step 508).

On the other hand, the cache controller 15b detecting the read signal issued with the read registers the cache block including the address 101 in the first information table 21 (step 601), as shown in FIG.
The entire cache block is valid (step 602).
, and since the word (address 101) is occupied (step 603), the word is shared (step 60).
4). As a result, the contents of the information table are updated as shown in FIG.

FIG. 17 shows the operations on the bus according to this embodiment.
Conventional write-invalid method (conventional method 1
) and Conventional Method 2 in which a 4-byte input buffer is provided with a cache block size of 1 word.

According to this, in the case of conventional method 1, originally valid words are determined to be invalid in steps 12, 14, etc., and unnecessary block reads occur, whereas in the case of the present embodiment, such words are determined to be invalid. This reduces the number of bus accesses and increases the overall efficiency of the multiprocessor system. Furthermore, in Conventional Method 2, the use of the bus is the same as in this embodiment, but since the cache block is small, the time required to search for which cache block stores data at a certain address increases. Problems arise such as the addition of buffers increases the complexity of the hardware and increases the amount of information in blocks.

[0037]

As described above, according to the present invention, by using n consecutive words as a cache block, it is possible to improve the hit rate and shorten the search time. Furthermore, it is possible to avoid treating originally valid data as invalid or sending an invalidation signal when writing data that is already occupied.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a diagram showing the structure of first and second information tables held by the cache device in FIG. 1;

FIG. 3 is a diagram showing an example of an access pattern between processors in the multiprocessor system of this embodiment.

FIG. 4 is a diagram showing the initial state of each information table in FIG. 2;

FIG. 5 is a flowchart showing the flow of processing when a processor reads a word.

FIG. 6 is a flowchart showing the flow of processing when a processor detects a read signal.

7 is a diagram showing the contents of each information table after step 1 in FIG. 3 is executed; FIG.

FIG. 8 is a diagram showing the contents of each information table after step 3 is executed.

FIG. 9 is a diagram showing the contents of each information table after step 9 is executed.

FIG. 10 is a diagram showing the contents of each information table after step 10 is executed.

FIG. 11 is a flowchart showing the flow of processing during word write by the processor.

FIG. 12 is a flowchart showing the flow of processing when a processor detects an invalidation signal.

FIG. 13 is a diagram showing the contents of each information table after step 11 is executed.

FIG. 14 is a diagram showing the contents of each information table after step 13 is executed.

FIG. 15 is a diagram showing the contents of each information table after step 15 is executed.

FIG. 16 is a diagram showing the contents of each information table after step 16 is executed.

FIG. 17 is a diagram illustrating operations on a bus according to this embodiment in comparison with a conventional method.

[Explanation of symbols]

11a, 11b... Processor 12... Shared memory 13... Buses 14a, 14b... Cache devices 15a, 15b... Cache controllers 16a, 1
6b...Cache memory

Claims (1)

[Claims] 1. A multiprocessor system configured by connecting a shared memory and a plurality of processors each having a cache device for the shared memory to a bus, wherein the cache device of the processor has a cache block consisting of n consecutive words. means for maintaining information as to whether all words in the cache block are valid or not for each word in the cache block; A multiprocessor system comprising: means for holding information on whether a word in the cache block is occupied or shared, and information on whether the word in the cache block is valid or invalid when all of the words in the cache block are not valid.