JPH07210526A - Parallel computer - Google Patents

Abstract

PURPOSE:To reduce directory capacity in the parallel computer which is provided with a distributed shared memory and performs the coincidence control of a cache memory by a directory. CONSTITUTION:In the parallel computer provided with plural processors and plural distributed shared memories to be accessed by the respective processors and providing cache memories for registering the data of the shared memories for the unit of a line in the respective processors, concerning the shared memory, a page directory 70 is prepared for each page of the shared memory, and the page directory 70 stores the processor which registers the line of that page in the cache memory. Then, a line directory is prepared for each line of the shared memory, and the position of the processor registering the line in the cache memory corresponding to the position on the page directory is stored in the line directory by a bit map.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer having a plurality of cache memories and a shared memory, and the shared memory having a directory.

[0002]

2. Description of the Related Art In order to improve computer performance, a parallel computer for operating a large number of processors in parallel is considered promising. A parallel computer requires a communication means between processors. As communication means, there are a message passing method of exchanging messages via a network and a shared memory method of preparing a shared memory area accessible by each processor. Exchange of messages in the message passing method is generally realized by starting an operating system. Booting an operating system is a very heavy overhead, especially for communicating short messages. On the other hand, the method using the shared memory realizes communication without starting the operating system. Therefore, the shared memory method is
The load on the processor in communication can be reduced.

As a shared memory system for a large-scale parallel computer, a distributed shared memory system in which a shared memory is divided and distributed and prepared is effective. Distributing the shared memory allows multiple processors to access the shared memory at the same time, and realizes highly parallel processing.
The distributed shared memory system includes (A) a homogeneous distributed shared memory system in which a constituent element having a processor and a constituent element having a part of shared memory are connected by a network (B) a processor and a part of a shared A heterogeneous distributed shared memory system is known in which components having a memory are connected by a network. As a homogeneous distributed type shared memory system (with no variation in access time), Japanese Patent Application Laid-Open No.
As a distributed shared memory system in which 128071 or the like is heterogeneous (variation in access time), there is JP-A-5-89056. In these schemes, when the processor accesses the shared memory, the homogeneous distributed shared memory scheme transfers data through the network with a high probability even in the heterogeneous distributed shared memory system. The recent improvement in the processing speed of the processor is remarkable as compared with the improvement in the network speed. For this reason,
When accessing via a network, the delay time becomes a big problem.

As a means for accelerating the shared memory access of each processor, a method of preparing a cache memory for each processor is effective. The cache memory is a high-speed buffer that registers part of the contents of the shared memory. In a shared memory type parallel computer having a cache memory, a plurality of processors may register the same data in their respective cache memories. In this case, a means for guaranteeing the match of the cache memory contents of each processor is required. The parallel computers connected by the bus guarantee the matching of the contents of the cache memory by using the snooping method. However, it is difficult to use the snooping method in the distributed shared memory system using the network. This is because the communication overhead required for the snooping technique to communicate the matching management information to all the processors becomes very large in the network. As means for guaranteeing cache memory match in a distributed shared memory system, Japanese Patent Laid-Open No. 328653/1992 discloses a system in which a bus is provided for addresses / commands and a network is provided for data. With this method, parallel processing of address / command transmission is impossible, and highly parallel processing is difficult to realize.

As a match management with improved parallelism, "The
Stanford Dash Multiproce
ssor, IEEE Computer, March
1992 pp. 63-78 "discloses a directory system. In the directory method, for each line that is a unit to be registered in the cache memory from the shared memory,
Prepare a directory to store the processor that registers the line in the cache memory. Further, a directory control circuit for controlling a directory is prepared for each distributed shared memory. When one or more processors register a line in the cache memory, the directory control circuit registers all the processors in the directory prepared in the line. When a processor updates the contents of a certain line, the directory control circuit checks the directory of the line to be updated and identifies the processor (other than the main processor that updates the line) in the cache memory. . Furthermore, the directory control circuit
For the cache memory of the specified processor,
Through the network, (A) The information of the line to be updated from the cache memory (after writing back to the shared memory if necessary)
Delete (B) Instruct either processing to update the information in the cache memory. By performing the above management, the same information is registered for the same line in all cache memories.

The directory system includes a full map system and a limited pointer system. The full map method is 1
This is a method of constructing a directory with a bitmap in which bits correspond to one processor. The limited pointer method is a method of forming a directory with a finite length pointer array that can store several processor IDs. In the limited pointer method, the number of processors that register the same line in the cache memory at the same time is generally small.
To utilize the characteristic. The redundancy of the directory that occurs in the full map method (most of the bits in the directory are 0) is reduced in the limited pointer method. As a result, the directory capacity can be reduced. In the limited pointer method, when a directory on a certain line overflows, it is necessary to take measures such as replacement processing. The replace process is a process in which one of the processors already stored in the directory writes the line back from the cache to the shared memory, deletes the processor from the directory, and registers a new processor. "The Stanford
Dash Multiprocessor, IEEE
Computer, March 1992 pp. 6
3 to 78 ", the full map method is used, and in JP-A-5-128071, the limited pointer method is used.

[0007]

When a large-scale parallel computer having a distributed shared memory is constructed using the above directory system, an extremely large directory capacity is required. As an example, a case where a full-map type directory is prepared in a parallel computer in which 4096 processors are connected via a network will be described. The size of page and line is 64 lines per page and 512 lines per line.
Bit (4K bytes per page). In the full map method, a directory of 4096 bits = 512 bytes is required for each line, and the directory capacity required for each page of shared memory is 512 bytes × 64 lines = 3.
It will be 2K bytes. That is, a directory having a capacity eight times as large as the shared memory capacity is required, which is not practical.
A case where the limited pointer method is prepared in the same parallel computer will be described. If up to 16 processors can be registered in the directory of one line, the directory capacity required for each page of the shared memory is:
(12 + 1) / 8 bytes x 16 pointers x 64 lines =
1664 bytes (1 pointer of the line directory for 4096 units requires 12 bits to represent each processor number. Further, each pointer has
Vali indicating if the pointer is used
1 bit is required for d bits). In the limited pointer directory method, the capacity of the directory is about 2/5 of the shared memory capacity, which is significantly reduced as compared with the full map method, but it is still considerably large. As described above, the full map method requires a directory with a capacity that is not practical for a large-scale parallel computer. Even with the limited method, the size of the directory is not negligible.
An object of the present invention is to realize a large-scale parallel computer having a directory type distributed shared memory with a small directory capacity.

[0008]

In order to achieve the above object, the present invention comprises a plurality of processors and a plurality of distributed shared memories which can be accessed by the respective processors, and each of the processors transfers data in the shared memory to a line. In a parallel computer having a cache memory that is registered in units, the shared memory is prepared for each page of the shared memory, and a page directory for storing a processor that registers some or all lines of the page in the cache memory A line directory that is prepared for each line of the shared memory and that stores the position on the page directory of the processor that registered the line in the cache memory in the bitmap format is provided. The line directory is prepared for each line of the shared memory, and the position on the page directory of the processor that registered the line in the cache memory is stored in the pointer format. Further, the plurality of shared memories and the plurality of processors are connected by a network. Further, a node is configured by the shared memory and the processor, and a plurality of the nodes are connected by a network. Further, each page directory is provided with a page directory pointer which points to a processor having the earliest stored time among the processors stored in the page directory. Further, each processor stored in the page directory is provided with a lock bit indicating whether or not the processor can delete the memory from the page directory.

[0009]

According to the present invention, since the shared memory is provided with the page directory and the line directory, the space required for the line directory can be significantly reduced, and thus the space required for the entire directory can be greatly reduced. Can be achieved.

[0010]

1 to 6 show an embodiment of the present invention. Further, FIG. 9 shows a page directory 70 according to the present embodiment.
An example of the contents of the line directory 90 is shown. At first,
The outline of the present embodiment will be described with reference to FIGS. Eight processors I-VIII are each connected to shared memory 6
FIG. 7 shows an example of the contents of the cache memory having the cache memories 20-0 to 20-7 capable of registering only lines. When the cache memory 20 of each processor has the registration status shown in FIG. 7, the page directory 70 and the line directory 90 when the processor in which each line is registered are stored by the method shown in this embodiment are shown in FIG. Show. However, one line of the shared memory is made up of eight lines 0 to 7, and only the contents of the page directory 70 of that page and the line directories 90-0 to 90 corresponding to the lines 0 to 7 are shown.

Since the processors storing the lines 0 to 7 are the processors I, II, III and VI, the pointer 94 of the page directory 70 stores the four processor IDs of the processors I, II, III and VI. To do. Furthermore, for each line, the line directory 90-
Prepare 0-7. Line directory 90-0 to 7
Stores, in a bitmap format, which of the processors stored in the page directory 70 is the processor that registered the line in the cache memories 20-0 to 20-7. In this example, 4 corresponding to the 4 processors stored in the page directory 70
Bit directory, line directory 90-0
~ 7 are configured. For example, if all the line directories 90-0 prepared for the line 0 are 1, all the processors I, I stored in the page directory
It means that I, III, and VI have registered line 0 in the cache. The line directory 90-0
.About.7 can also be configured in a pointer format, that is, a pointer string. In this case, each pointer indicates the processor registration position in the page directory 70. For example, in the case of FIG. 9, four processor IDs are registered in the page directory, but pointers 00, 01, 10 and 11 are given to the registered positions, respectively, and these pointers are stored in the line directory.
Each of the pointers 94 of the page directory 70 may or may not be provided with a flag indicating use / unuse of the pointer. If not prepared, the page directory always stores a fixed number of processors. In this case, although there are processors stored in the page directory 70, all the bits of the corresponding line directories 90-0 to 90-7 may be 0.

Lines 0 to 0 when the registration status shown in FIG. 7 is stored in the limited pointer type directory.
8 shows the contents of the directories 92-0 to 92-7 prepared in FIG.
Shown in. Directories 92-0 to 92-0 prepared for each line
The pointer 94 of 7 indicates the line to the cache memory 2
The IDs of the processors registered in 0-0 to 7 are stored as they are. For example, line 0 is processor I, II,
Since it is registered in the four cache memories 20-0 to 7 of III and VI, the four processor IDs of processors I, II, III, and VI are stored in the directory 92-0.
Is remembered. It should be noted that each pointer 94 needs a Valid flag 96 indicating whether it is used or not.

Generally, a processor that registers a certain line in the cache memory has a high probability of registering an adjacent line in the cache memory. This is because a program having a loop structure often processes a continuous area (generally, the program is optimized to process a continuous area). For example, like the cache memory 20-4 of the processor V in FIG. 7, there is a high probability that consecutive lines will be registered in the cache memory. In the case of the above-mentioned characteristics, in the limited pointer method, the ID of the same processor is repeatedly registered in the adjacent directories. In this case, redundancy occurs in the information that the directory has. For example, a total of 22 processor IDs are stored in the eight directories 92-0 to 7 in FIG.
Are stored, but only the four processors I, II, III, and VI are stored. In the method of this embodiment, the capacity of the directory is reduced by utilizing this redundancy. In the examples of FIGS. 8 and 9, the required directory capacity is calculated for each. Since there are a total of eight processors, the pointer 94 requires 3 bits. The limited pointer method requires a directory capacity of (3 + 1) bits × 4 pointers × 8 lines = 128 bits in total including the Valid bit 96. On the other hand, in the method of this embodiment, the page directory 70 has 3 bits × 4 pointers = 12 bits, and the line directory 90−
4 bits for 0 to 8 x 32 lines = 32 bits, 44 bits in total, about 1/3 of the limited pointer method
Capacity is enough. Further, a parallel computer in which 4096 processors are connected via a network calculates the directory capacity required in this embodiment. Similar to the case where the directory capacity is calculated by the full map method and the limited pointer method, the size of page and line is set to 64 lines per page, 512 bits per line (4 Kbytes per page). If the number of processors that can be registered in the page directory of each page is 16,
12/8 bytes x 16 pointers + 16/8 bytes x 64
Line = 152 bytes. Further, even when the number of processors that can be registered in the page directory of each page is 64, it will be 12/8 bytes × 64 pointers + 64/8 bytes × 64 lines = 608 bytes. This is smaller in directory capacity than the full-map type 32 Kbytes and the limited pointer type 1664 bytes under the same conditions.

In this embodiment, there is a problem in processing when the page directory is completely used and it is necessary to store a new processor in the page directory. The outline of this process will be described with reference to FIG. In the present embodiment, when all the page directories 70 are used and a new processor needs to be stored in the page directory 70, among the processors stored in the page directory 70,
The message interpretation / execution unit 50 requests replacement processing to the processor pointed to by the page directory pointer 80 that points to the processor with the earliest stored time. For example, when replacing the processor 15 already stored in the page directory 70 with the processor 215, the message interpretation / execution unit 50 causes the processor 15 to notify the page directory 70.
From the page of the shared memory 45 to which all the lines registered in the cache memory 20 belong
, And the processor 15 is erased from the line directory 90 and the page directory 70, so that the new processor 215 is stored in the page directory 70 after the directory is emptied. The page directory pointer 80 can always point to the processor with the earliest stored time by incrementing (or decrementing) each replacement process. Furthermore, by providing each processor stored in the page directory 70 with a lock bit 75 indicating whether or not the memory can be erased, it is possible to prohibit the replacement of the processor whose memory is to be erased. In this case, when the replacement process becomes necessary, the page directory pointer 80 is incremented (or decremented) until the page directory pointer 80 points to a processor whose replacement is prohibited by the lock bit 75. By using the page directory pointer 80 and the lock bit 75, frequent replacement processing can be avoided and the time cost for replacement processing can be reduced.

The details of this embodiment will be described with reference to FIGS. FIG. 1 shows system units 0, 200 and 1000.
It is a distributed shared memory parallel computer. Each system unit includes a processor node 10, 210,
1010 and memory nodes 40, 240, 1040. In this embodiment, all processor nodes 1
0, 210, 1010 and memory unit nodes 40, 24
A uniform distributed shared memory in which 0 and 1040 are connected by a network 1500. A processor node 10 and a memory node 40 in the same system unit 0,
The connection between the processor node 210 and the memory node 240 in the system unit 200 and the connection between the processor node 1010 and the memory node 1040 in the system unit 1000 does not use the network 1500 but uses a separately prepared coupling method. This embodiment can be applied to various distributed shared memories. Further, in the present embodiment, the page directory 70 is always operated in a state of being used. In this case, page directory 7
When the processors 15, 215, and 1015 are newly stored in 0, the replacement process is necessary.

Only for the system unit 0, the configurations of the processor node 10 and the memory node 40 will be described. The other system units 200 and 1000 have the same configuration as the system unit 0. Processor node 10
Is a processor 15, a cache memory 20, a processor network connection circuit 25, a message assembly circuit 3
0, a message decomposition circuit 35. The processor network connection circuit 25 has a distributed memory map 27 for determining which memory node 40, 240, 1040 the request for the shared memory 45, 245, 1045 of the processor 15 is, and the processor 0 and the processor 0. It has a function of connecting the message assembling circuit 30 and the message disassembling circuit 35. The message assembling circuit 30 has a function of generating a message packet for the memory node number, address, data and command for the network 1500 from the processor network connection circuit 25 and sending the message packet to the network 1500. The message decomposing circuit 35 has a function of decomposing a message packet from the network into an address, data and a command, and sending it to the processor network connection circuit 25.

The memory node 40 includes a shared memory 45, a page directory 70, a lock bit 75, a page directory pointer 80, a line directory 90, a page directory control circuit 65, a line directory control circuit 85, a message assembly circuit 55, and a message disassembly circuit. It consists of 60. Message interpreter / executor 50
Responds to requests from processors 15, 215, 1015
In addition to sending the page number to the page directory 70, the lock bit 75, and the page directory pointer 80 via the address line 173, the page directory control circuit 6
5, address information in the line directory control circuit 85,
Data and control signals are sent to write or read the page directory 70 and line directory 90. In addition, writing to and reading from the shared memory 45 are performed. In this embodiment, the message interpretation / execution unit 50 is a control system having a processor, a memory, and an I / O therein, but it may be configured by a circuit. The page directory control circuit 65 receives the page directory 7 according to the control signal from the message interpreting / executing unit 50.
0, lock bit 75, page directory pointer 8
It is a circuit that operates 0. The line directory control circuit 85 is a circuit for operating the line directory 90 by a control signal from the message interpreting / executing unit 50.

FIG. 2 shows the configuration of the page directory control circuit 65. Here, the number of processors that can be registered in the page directory 70 for each page is m.
The processor number register 101 stores message interpretation /
The processor number sent from the execution unit 50 via the data line 157 is entered. Processor number registers 110-114
In, the processor number stored in the page directory 70 sent from the data line 170 is entered. The number of processor number registers 110 to 114 is m.
The comparators 105 to 109 are the processor number register 10
1 and the processor numbers of the processor number registers 110 to 114 are compared, and the coincidence determination result is determined by the bit calculator 12
It is a circuit for sending to the bit calculator 180 of the line directory control circuit 85 via 0 and the data line 160.
If all the comparison results do not match, the data line 145 outputs the mismatch to the message interpretation / execution unit 50. The multiplexer 117 is a circuit that outputs one of the processor numbers stored in the processor number registers 110 to 114, which is determined by the signal from the selector 118, to the message interpretation / execution unit 50. In response to the control signal 150 from the message interpreting / executing unit 50, the demultiplexer 119 sets the processor number stored in the processor number register 101 to one of the processor number registers 110 to 114 indicated by the pointer information register 122. It is a circuit that outputs to a register. The lock information register 121 stores the lock information for one page of the lock bit 75 sent from the data line 171. The bit calculator 120 is a circuit that sets the contents of the lock information register 121 according to the control signal 151 from the message interpreting / executing unit 50 and resets it according to the control signal 152. Which bit of the lock information register 121 is set / reset is determined by a match signal from the comparators 105 to 109. Further, the bit calculator 120 interprets the message /
It has a function of testing whether the bit of the lock information register 121 is 0 or 1 according to the control signal 153 from the execution unit 50 and sending the result to the message interpretation / execution unit 50 via the data line 146. The bit to test is determined by the data from the pointer information register 122. Information for one page of the directory page pointer 80 sent from the data line 172 is stored in the pointer information register 122. The contents of the pointer register are the data line 16
It is also output to the bit calculator 180 of the line directory control circuit 85 via 1. Increment circuit 12
Reference numeral 3 is a circuit that increments the contents of the pointer information register 122 according to the control signal 156 from the message interpreting / executing unit 50. The priority encoder uses the data line 1 from the line directory control circuit 85.
It is a circuit that encodes the contents of the line information register 179 sent in 65. When there are a plurality of encoded results, one is selected by a fixed method or a random method and output to the selector 118. The control line 155 from the message interpretation / execution unit 50 also has a function of sequentially outputting a plurality of encoded results to the selector 118. The selector 118 outputs the signal output to the multiplexer 117 according to the control signal 154 from the message interpretation / execution unit 50 to the pointer information register 122.
Or the content of the priority encoder 124.

FIG. 3 shows a line directory control circuit 90.
Shows the configuration of. The line number generator 175 is a circuit that sequentially generates all the line numbers according to the control line 188 from the message interpretation / execution unit 50. The generated line number is output to the selector 176. The line number generator 175 also outputs a test request to the bit calculator 180. The selector 176 receives the line number generator 1 according to the control line 187 from the message interpretation / execution unit 50.
75 output line number or address line 185
This is a circuit for outputting either of the line numbers from the message interpretation / execution unit 50 obtained further. Mixer 178
Is the address line 186 from the message interpreter / executor 50.
It is a circuit for synthesizing the page number and the line number sent from the selector 176, which are sent in step S1, and outputting the result to the address line 160 of the line directory 90. The line information register 179 stores information for one line of the line directory 90 sent from the data line 197. The content of the line information register 179 is the data line 16
5 is output to the priority encoder 155 of the page directory control circuit 65. Bit calculator 18
Reference numeral 0 is a circuit that sets the content of the line information register 180 according to the control signal 189 from the message interpreting / executing unit 50 and resets it according to the control signal 190.
Which bit of the line information register 179 is set / reset is determined by the coincidence signal 160 from the comparators 105 to 109 of the page directory control circuit 65. Further, the bit calculator 180 is the line number generator 1
In response to a control signal from 75, the line information register 17
It has a function of testing whether the 9th bit is 0 or 1 and outputting the result to the line number latch 177. The bit to be tested is determined by the data from the pointer information register 161 of the page directory control circuit 65. The line number latch 177 is a circuit that outputs the line number output by the selector 176 to the message interpretation / execution unit 50 when the test result of the bit calculator 180 is true.

The processor 1 according to the method of the present invention will be described below.
The operation of the memory control mechanism at the time of executing load, store, and flush according to No. 5 will be described. It is assumed that the processor 15 has a store-in type cache memory 20. In this,
Page directory control circuit 65, line directory control circuit 85, page directory check 2000, page directory storage 2100,
Processor search 2200, all processor search 2300,
Details of the line directory storage 2400, the line directory deletion 2500, the lock bit set, and the lock bit reset will be described later.

[1] When the processor 15 loads the data in the shared memory 45 When the line containing the target data is registered in the cache memory 20, the load request is sent from the processor 15 to the processor network connection circuit 25. No operation is output and all operations are completed. When the line including the target data is not registered in the cache memory 20, the processor 15 connects the processor network connection circuit 25 to the processor network connection circuit 25.
A load request is output to and the following operation is performed. In the processor network connection circuit 25, the distributed memory map 27 is checked, and the load request is determined to be a load request to the shared memory 45. The processor network connection circuit 25 includes a message assembly circuit 30, a network 1
A load command is sent to the message interpretation / execution unit 50 via the message decomposition circuit 60.

Message interpretation for load command /
The operation of the execution unit 50 is shown in FIG. 4 and will be described below. Upon receiving the load command, the message interpreting / executing unit 50 performs page directory check 2000, and the processor 1
Check whether 5 is stored in the page directory 70. Page directory storage 2 if not stored
100, processor 15 to page directory 7
Store to 0. Next, another processor 215, 1015
Performs a processor search 2200 to see if the line is registered in the cache memories 220 and 1020. As a result, for example, if it is registered in the cache memory 220 of the processor 215, the message interpretation / execution unit 50 causes the message assembling circuit 55, the network 15
00, the message decomposing circuit 235, and the processor network connecting circuit 225 to request the processor 215 to transfer the line to the processor 15. The requested processor 215 reads the line from the cache memory 220, and the processor network connection circuit 2
25, message assembly circuit 230, network 150
0, the message decomposition circuit 35, and the processor network connection circuit 25 to transfer the line to the processor 15. If the line is not registered in the cache memories 220 and 1020, the message interpretation / execution unit 50 reads the line from the shared memory 45, and the line is assembled into the message assembly circuit 55, the network 1500, the message decomposition circuit 35, the processor network. Connection circuit 2
5 to the processor 15. Finally, the message interpreter / executor 50 uses the line directory store 240
0 to run processor 15 in line directory 90
To memorize. With the above processing, the processor 15 causes the shared memory 4
The description of the operation for loading data No. 5 is finished.

[2] When the processor 15 stores in the data of the shared memory 45 When the line including the data to be stored in the cache memory 20 is not registered, the same operation as the above-mentioned data loading is first performed. The following operation is performed while the line including the target data is registered in the cache memory 20. When the processor 15 executes the store,
Cache memory 22 of other processors 215, 1015
A request for invalidating the line registered in 0, 1020 is output to the processor network connection circuit 25. The processor network connection circuit 25 checks the distributed memory map 27 to determine that the data to be stored is originally the data in the shared memory 45,
An invalidate command is sent via the message assembly circuit 30, the network 1500, and the message decomposition circuit 60. The operation of the message interpreter / executor 50 for the invalidate command is shown in FIG. 5 and described below.
The message interpretation / execution unit 50 that has received the invalidate command sets the line to the cache memories 220, 10
An all processor search 2300 for extracting all processor numbers registered in 20 is performed. As a result, for example, when the processor 15, the processor 215, and the cache memory 20 of the processor 1015, the cache memory 220, and the cache memory 1020 are registered, the message interpreting / executing unit 50 excludes the processor 15 that is the invalidation request source. 215, processor 10
15, message assembly circuit 55, network 150
0, the message decomposing circuit 235 and the message decomposing circuit 1035, the processor network connecting circuit 225, and the processor network connecting circuit 1025 are requested to invalidate the line. Processor 215
And the processor 1015 invalidates the line from the cache memory 220 and the cache memory 1020, and then the processor network connection circuit 225 and the processor network connection circuit 1025, the message assembly circuit 230 and the message assembly circuit 103.
0, the network 1500, and the message decomposing circuit 60 to notify the message interpreting / executing unit 50 of the invalidation end. Each time the message interpretation / execution unit 50 receives the invalidation completion, it erases the memory of the invalidated processor 215 or the processor 1015 from the line directory 90 of the line, and performs line directory elimination 2500. Processor 1 that requested the invalidate command
After completing the invalidation termination acceptance and line directory deletion 2500 of the processors 215 and 1015 other than 5, the message interpreting / executing unit 50 causes the message assembling circuit 55, the network 1500, the message disassembling circuit 35, and the processor network connecting circuit 25 to operate. Via the end of the invalidation command, the processor 15 is notified of the completion. With the above processing, the processor 15 causes the shared memory 45
This ends the description of the operation for storing in the data.

[3] When Processor 15 Flushes Line to Shared Memory 45 The processor 15 outputs a flush request to the processor network connection circuit 25 together with the line to be flushed. The processor network connection circuit 25 checks the distributed memory map 27 to determine that the line to be flushed is originally the line of the shared memory 45, and the message assembly circuit 30 and the network 15
00, send a flush command with the line via the message decomposition circuit 60. The operation of the message interpretation / execution unit 50 for the flash command is shown in FIG.
This will be described below. The message interpretation / execution unit 50 that has received the flush command writes the line back to the shared memory 45. In addition, the line directory 9 for that line
The line directory deletion 2500 that deletes the memory of the processor 15 from 0 is performed. Finally, the message interpreter / executor 50 includes a message assembling circuit 55, a network 1
The end of the flash command is notified to the processor 15 via the 500, the message decomposition circuit 35, and the processor network connection circuit 25. This is the end of the description of the operation when the processor 15 flushes the line of the shared memory 45.

Below, the page directory control circuit 6
5, page directory check 2000 that requires the operation of the line directory control circuit 85, page directory storage 2100, processor search 2200, all processor search 2300, line directory storage 240
Detailed operations of 0, line directory deletion 2500, lock bit set, and lock bit reset will be described.

<1> Page directory check 200
0 Page Directory Check 2000 is for Processor 1
This is an operation for checking whether 5, 215 and 1015 are stored in the page directory 70. As an example, let us consider the processor 15. The message interpretation / execution unit 50 causes the processor number register 101 in the page directory control circuit 65 to store the ID number of the processor 15 through the data line 157. Further, the message interpreting / executing unit 50 informs the page directory 70 of the page number to be investigated through the address line 173. The page directory information of the page to be investigated is the data line 17
It goes through 0 and is stored in the processor number registers 110-114. The contents of the processor number register 101 and the contents of the processor number registers 110 to 114 are compared in the comparators 105 to 109, and if the results are all inconsistent, the message line interpreting / executing unit indicates that the inconsistencies are from the data line 145. 50 is notified. With the above, the operation of checking whether the processor 15 is stored in the page directory 70 ends.

<2> Page Directory Storage 2100 The page directory storage 2100 is an operation for newly registering the processors 15, 215, and 1015 by performing the above-mentioned replacement processing from the page directory 70. As an example, the operation of deleting the processor 215 from the page directory 70 and newly registering the processor 15 will be described. The message interpretation / execution unit 50
The address line 173 informs the page directory 70, the lock bit 75, and the page directory pointer 80 of the page number to be examined. The page directory information of the page to be investigated passes through the data line 170 to the processor number registers 110 to 114, the lock information passes through the data line 171 to the lock information register 121, and the pointer information passes through the data line 172 and the pointer information register 122.
Memorized in. The message interpreter / executor 50 sends the bit calculator 120 through the control line 153 to the bit calculator 120 of the bit indicated by the pointer information register 122 of the lock information register 121.
Request a test. The bit calculator 120 uses the data line 1
The result is sent to the message interpreter / executor 50 via 46. If the message interpretation / execution unit finds that the test result is in the locked state, the message interpretation / execution unit issues an increment request to the increment circuit 123 via the control line 156. The increment circuit 123 increments the content of the pointer information register 122 when an increment request is made. When the message interpreter / executor 50 increments, the message interpreter / executor 50 sends the bit calculator 12 from the control line 153 again.
0 is requested to test the bit indicated by the pointer information register 122 of the lock information register 121. The above operation is repeated until the test result is unlocked. If there is no unlock state even after repeating m times, the message interpretation / execution unit 50 terminates abnormally.

When the unlocked state is found for the processor 215, the message interpreter / executor 50 sets the output of the selector 118 to the data on the side of the pointer information register 122 through the control line 154. Based on the output of the selector 118, the multiplexer 117 causes the pointer information register 12 out of the processor number registers 110 to 114.
The content indicated by 2, that is, the ID number of the processor 215 to be deleted in the replacement process is output. This output is sent to the message interpreter / executor 50 via the data line 140. As a result, the message interpretation / execution unit 50
Obtains the ID number of the processor to be deleted in the replacement process.

Next, the message interpreting / executing unit 50 uses the control line 187 to switch the selector 176 of the line directory control circuit 85 to the line number generator 175 side. Further, the message interpreting / executing unit 50 sends the page number to the mixer 178 via the address line 186. Further, the message interpreting / executing unit 50 activates the line number generator 175 through the control line 188.

The line number output from the line number generator 175 passes through the selector 176, is mixed with the page number in the mixer 178, and is output to the line directory 90 from the address line 195. Information in the line directory 90 enters the line information register 179. The line number generator 175 inputs the test request signal to the bit calculator 180. Here, the bit line 180 is connected to the data line 1
Through 61, the contents of the pointer information register 122 of the page directory control circuit 65, that is, the position of the processor 215 to be replaced in the page directory 70 is input. As a result, the bit calculator checks whether or not the processor 215 to be replaced is stored in the line directory 90 of the line output by the line number generator 175. As a result of the check, if it is stored, the line number latch 177
To the output request signal. Upon receiving the output request signal, the line number latch 177 outputs the output of the selector 176 to the message interpretation / execution unit 50 via the data line 181. The line number generator 175 generates a new line number until the line number makes a round, and the bit calculator 18
The test request signal is output to 0. As a result, the message interpretation / execution unit 50 obtains all the line numbers of the page registered in the cache memory 220 by the processor 215 to be deleted in the replacement process.

Processor 2 to be erased by the replacement process
After obtaining all the ID numbers of 15 and the line numbers of the page registered in the cache memory 220, the message interpreting / executing unit 50 causes the message assembling circuit 5 to execute.
5, network 1500, message decomposition circuit 23
5. Requests the processor 215 to flush the line via the processor network connection circuit 225.
From processor 215, processor network connection circuit 225, message assembly circuit 230, network 1
When the flash data is sent to the message interpretation / execution unit 50 via the message decomposition circuit 60, the message interpretation / execution unit 50 writes the data back to the shared memory 45.

Then, using the data line 157, the ID number of the processor 215 to be replaced is input to the processor number register 101 of the page directory control circuit 65. Since the processor number registers 110 to 114 store the information of the page directory 70 of the page, the data lines 160 are compared by the comparators 105 to 109, and the data line 160 has the page directory 70 of the processor 215 to be replaced. The position at is output. The position of the processor 215 to be replaced in the page directory 70 is input to the bit calculator 180 of the line directory control circuit 85 by the data line 160. In this state, the message interpreting / executing unit 50 issues a control signal 187 so that the signal on the address line 185 is output from the selector 176.

Further, the message interpreting / executing unit 50 sends the flushed line number to the mixer 178 through the address line 185 and the selector 176. Address line 1
Since the page number is input to 86, the line number for which the flash is completed is input to the line directory 90 from the address line 195. From the line directory 90, the information of the line is the data line 197.
And is input to the line directory register 179. Here, from the message interpretation / execution unit 50 to the control line 1
At 90, a reset request is output. Bit calculator 180
Since the position of the processor 215 to be replaced in the page directory 70 is input to the data line 160, the memory of the processor 215 is deleted from the line directory register 179. The erased data is written back to the line directory 90 through the data line 197. The message interpretation / execution unit 50 repeats the erasure process described above for all the flushed lines.

After the processing of deleting the processor 215 from the line directory 90 is completed, the message interpreting / executing unit 5
0 indicates the ID number of the processor 15 to be newly stored in the page directory 70 through the data line 157 and the processor number register 1 of the page directory control circuit.
Put it in 01. Here, the pointer information register 122
Indicates the processor number registers 110 to 114 stored in the processor 215. In this state, the message interpreting / executing unit issues an output request signal to the demultiplexer 119 by the control signal 150. The demultiplexer uses the ID number of the processor 15 stored in the processor number register 101 and the processor number registers 110 to 114 in which the processor 215 was stored.
Output to. Processor number registers 110-114
To the page directory 70 through the data line 170.
Write back to. As described above, the operation of newly storing the processor 15 in the page directory 70 ends.

<3> Processor search 2200, all processor search 2300 The processor search 2200 includes the processors 15, 215,
1015, a certain line is set to the cache memory 20,
Only one operation registered in 220, 1020 is checked, and all processor search 2300 is checked. The message interpreter / executor 50 notifies the page directory 70 of the page number to be examined through the address line 173. The page directory information of the page to be examined is stored in the processor number registers 110 to 114 through the data line 170. Next, the message interpretation / execution unit 50 uses the control line 187 to switch the selector 176 of the line directory control circuit 85 to the address line 185 side. In addition, the message interpreting / executing unit 50 sends the page number from the address line 186 to the mixer 1
Send to 78. Also, the message interpreting / executing unit 50 determines the line number to be investigated by the address line 185, the selector 1
It is sent to the mixer 178 through 76. The page number and the line number are mixed by the mixer 178 and output to the line directory 90 through the address line 195.

The information in the line directory 90 enters the line information register 179. The information of the line information register 179 is input to the priority encoder 124 of the page directory control circuit 65. The priority encoder 124 uses the processor 15, 215, 101 on the page directory stored in the line information.
One of the five pieces of position information is output to the selector 118. The message interpreting / executing unit 50 uses the control line 155 to set the selector 118 to the priority encoder 124.
Switch to the side. As a result, of the processor ID numbers stored in the processor number registers 110 to 114, the processor number at the position selected by the priority encoder 124 is sent to the message interpretation / execution unit 50 by the multiplexer 117. In the case of the all processor search 2300 that requires all the processor numbers, the control signal 155 to the priority encoder 124 includes
The message interpreting / executing unit 50 issues a priority change request. If the priority is changed once, the message interpreter / executor 50 can obtain all the processors. By the above, a certain line is set to the cache memory 20, 22
The operation of checking one or all of those registered in 0, 1020 is completed.

<4> Line directory storage 2400,
Line directory deletion 2500 The line directory storage 2400 refers to the line directory 90 of a certain line from the processors 15, 215,
1015 is an operation of storing any of them, and the line directory deletion 2500 is an operation of deleting the storage.
From the data line 157, the message interpretation / execution unit 50
The ID number of the processor 15 is stored in the processor number register 101 in the page directory control circuit 65. Further, the message interpreting / executing unit 50 informs the page directory 70 of the page number to be investigated through the address line 173. The page directory information of the page to be examined is stored in the processor number registers 110 to 114 through the data line 170. Contents of processor number register 101 and processor number registers 110-110
The contents of 114 are compared with each other in the comparators 105 to 109, and if the results are all inconsistent, the inconsistency is notified to the message interpretation / execution unit 50 from the data line 145, resulting in abnormal termination. If there is a match, the processor 15 or 21 to be stored / erased from the data line 160.
The storage / erasure positions of 5, 1015 are input to the bit calculator 180 of the line directory control circuit 85. Next, the message interpretation / execution unit 50 uses the control line 187 to select the selector 176 of the line directory control circuit 85.
To the address line 185 side. Further, the message interpreting / executing unit 50 sends the page number to the mixer 178 via the address line 186. The message interpreting / executing unit 50 also sends the line number to be stored / deleted to the mixer 178 through the address line 185 and the selector 176. The page number and the line number are mixed by the mixer 178 and output to the line directory 90 through the address line 195. Information in the line directory 90 enters the line information register 179. In this state, the message interpretation / execution unit 50 sends a storage request by the control signal 189 to the bit arithmetic unit 180 to store the control signal 1
Erasure is executed by issuing a erasure request by 90. Finally, the line information register 179 writes the information back to the line directory 90. As described above, the line directories 90 of a certain line allow the processors 15, 21
The operation of storing / deleting any one of 5, 1015 ends.

<5> Lock Bit Set, Lock Bit Reset The lock bit set is the lock bit 7 of a page.
5 is an operation for putting the processor 5 into a locked state with respect to a specific processor 15, 215, 1015, and a lock bit reset is an operation for bringing it into an unlocked state. Message interpretation /
The execution unit 50 transfers the data line 157 to the processor number register 101 in the page directory control circuit 65,
The ID number of the processor 15 is stored. The message interpreting / executing unit 50 also notifies the page directory 70 and the lock bit 75 of the page number through the address line 173. Page directory information is data line 170
To the processor number registers 110 to 114, and the lock information passes through the data line 171 to the lock information register 12
Stored in 1. The contents of the processor number register 101 and the contents of the processor number registers 110 to 114 are compared in the comparators 105 to 109, and if the results are all inconsistent, the message line interpreting / executing unit indicates that the inconsistencies are from the data line 145. It is notified to 50 and ends abnormally. If there is a match, the storage / erasure positions of the processors 15, 215, 1015 to be stored / erased are input to the bit arithmetic unit 120 of the page directory control circuit 65 from the comparators 105 to 109. In this state,
From the message interpreting / executing unit 50 to the bit arithmetic unit 120, a lock request is issued by the control signal 151, and a lock is issued by issuing a delete request by the control signal 152. Finally, the information is written back to the lock bit 75 from the lock information register 121. From the above,
Lock bit 75 of a page to a specific processor 1
The operation of setting the locked / unlocked state for 5, 215, and 1015 ends.

This is the end of the description of the operation of the memory control mechanism at the time of loading, storing, and flushing by the processors 15, 215, and 1015 according to the method of the present invention. With the circuit and control method described above, a shared memory parallel computer having the page directory 70, the lock bit 75, the page directory pointer 80, and the line directory 90 is realized.

[0040]

According to the present invention, the capacity of the directory provided in the shared memory for performing the cache memory matching control can be significantly reduced as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a parallel computer having a shared memory mechanism according to an embodiment.

FIG. 2 is a diagram showing a page directory control circuit in the shared memory mechanism of the embodiment.

FIG. 3 is a diagram showing a line directory control circuit in the shared memory mechanism of the embodiment.

FIG. 4 is a diagram showing a flowchart of processing for a load command of a message interpreting / executing unit in the shared memory mechanism of the embodiment.

FIG. 5 is a diagram showing a flowchart of processing for an invalidate command of a message interpretation / execution unit in the shared memory mechanism of the embodiment.

FIG. 6 is a diagram showing a flowchart of processing for a flash command of a message interpretation / execution unit in the shared memory mechanism of the embodiment.

FIG. 7 is a diagram showing a storage state of a line in a cache memory of a parallel computer.

FIG. 8 is a diagram showing a directory of a limited pointer type.

FIG. 9 is a diagram showing a directory of a parallel computer having a shared memory mechanism of the embodiment.

[Explanation of symbols]

0, 200, 1000 system unit 10, 210, 1010 processor node 15, 215, 1015 processor 20, 220, 1020 cache memory 25, 225, 1025 processor network connection circuit 27 distributed memory map 30, 55, 230, 1030 message assembly circuit 35, 60, 235, 1035 Message decomposition circuit 40, 240, 1040 Memory node 45, 245, 1045 Shared memory 50 Message interpretation / execution unit 65 Page directory control circuit 70 Page directory 75 Lock bit 80 Page directory pointer 85 Line directory control circuit 90 line directory 92 full map directory 94 limited pointer directory 96 directory valid bit 101 processor number register 105-109 comparator 110-114 processor number register 117 multiplexer 118 selector 119 demultiplexer 120 bit calculator 121 lock information register 122 pointer information register 123 increment circuit 124 priority encoder 175 line number generator 176 selector 177 lines Number Latch 178 Mixer 179 Line Information Register 180-bit Operation Unit 1500 Network

Claims (6)

[Claims] 1. A parallel computer comprising a plurality of processors and a plurality of distributed shared memories accessible by the respective processors, each processor comprising a cache memory for registering data of the shared memory in line units, Is prepared for each page of the shared memory, and is provided for each line of the shared memory and a page directory for storing a processor in which some or all lines of the page are registered in the cache memory, and the line is cached. A parallel computer, comprising: a line directory that stores a position on a page directory of a processor registered in a memory in a bitmap format. 2. A parallel computer comprising a plurality of processors and a plurality of distributed shared memories accessible by the respective processors, each processor comprising a cache memory for registering data of the shared memory in line units, Is prepared for each page of the shared memory, and is provided for each line of the shared memory and a page directory for storing a processor in which some or all lines of the page are registered in the cache memory, and the line is cached. A parallel computer, comprising: a line directory that stores, in a pointer format, a position on a page directory of a processor registered in a memory. 3. The parallel computer according to claim 1, wherein the plurality of shared memories and the plurality of processors are connected via a network. 4. The parallel computer according to claim 1, wherein the shared memory and the processor constitute a node, and a plurality of the nodes are connected by a network. 5. The parallel computer according to claim 1, wherein, for each page directory, a page directory pointer that points to a processor having the earliest stored time among the processors stored in the page directory. A parallel computer comprising: 6. The parallel computer according to claim 1, further comprising a lock bit for each processor stored in the page directory, the lock bit indicating whether or not the processor can delete the memory from the page directory. A characteristic parallel computer.