JP2862424B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache memory, and more particularly, to an information processing apparatus having a cache memory that is devised not only so that operation can be continued in the event of a failure, but also for a subsequent recovery measure.

[0002]

2. Description of the Related Art With the expansion of fields of use of information processing devices,
The demand for higher performance and higher reliability of information processing equipment
Always improving.

As a method for improving the performance of an information processing device,
One of them is to use a cache memory.
As typical methods of the cache memory, there are a write-through method of immediately rewriting the main memory when data stored in the cache memory is rewritten, and a copy-back method.

The copy-back method has the advantage that the number of times of writing from the cache memory to the main memory is smaller than that of the write-through method, so that the load on the bus connecting the processor unit and the main memory is small. Suitable for multi-processor configuration with shared main memory.

Another method for improving the performance of an information processing apparatus
As one of the methods, there is a method of using a multiprocessor configuration. There are two main types of multiprocessor configurations: a main memory sharing type (tightly coupled type) in which processor units are coupled by a memory bus, and a loosely coupled type in which the processor units are connected by a network or a communication line. The overhead of communication between the processor units is advantageously shorter in the shared main memory type than in the loosely coupled type since the transmission time of the network or communication line is not included.

In order to use a combination of a cache memory and a shared-memory multiprocessor configuration, it is necessary to control matching of data shared by a plurality of processor units in a cache memory in each processor. That is, since the data on the main memory can be stored in the cache memory in a plurality of processor units, when a certain processor unit rewrites the data, the data in another processor unit is invalidated or Data needs to be updated. Usually, this matching control is performed by a function called a bus snoop.

The bus snoop function is realized by means of a snooper which monitors information of a bus in a cache memory. Means (directory) for storing information on which address of main memory is stored in the cache memory and the state of data in the cache memory (whether the data has been rewritten by the processor unit or the like) in the snooper. There is. The snooper constantly monitors access on the bus, and when an address on the bus matches an address stored in the directory, that is, access to data stored in the cache memory is performed on the bus. Is detected, if an access occurs in which the contents of the cache memory may be inconsistent due to the access, the above-described matching control is performed.

The details of the control method of the bus snoop function are described in Nikkei BP, Nikkei Electronics No. 4
78 (issued July 24, 1989) ”on page 173 to page 179,“ 32-bit MPU, built-in bus snoop function for multiprocessors (Eiji Yokota,
By Naoki Asami)).

As one of methods for increasing the reliability of an information processing apparatus, as described in US Pat. No. 4,939,643, main components such as a processor unit, a bus, and a main memory are multiplexed to form one component. There is a method that enables operation to be continued even if a failure occurs.

[0010]

When the conventional example relating to the cache memory is applied to the multiplexed system as it is, it is possible to achieve higher reliability by multiplexing the cache memory. In a system configuration in which the cache memory, bus, and main memory are duplicated and the main memory is shared with a multiprocessor configuration to further improve performance, it is possible that any one of the cache memory, bus, and main memory fails. However, operation can be continued using another system.

However, if one of the multiplexed buses or the main memory connected to the bus fails and becomes inoperable, the cache memory connected to the bus becomes inoperable. Since the above normal data transfer cannot be guaranteed, normal bus snoop cannot be executed. Therefore, before the bus becomes operable again and the operation of both systems is resumed, it is necessary to match the directories of the snoopers of the cache memories of both systems. The snooper directory contains, in addition to the address of the main memory of the data in the cache memory, information as to whether the data has been rewritten by the processor unit. Therefore, simply disabling the Snooper directory in order to match the Snooper directory in both systems will result in the cache memory storing the data rewritten by the processor unit. Will not match the information.

In the conventional example relating to the cache memory, no consideration is given to the matching of Snooper directories when recovering from a single-system failure in the case of such multiplexing, and the conventional technique cannot be applied to a multiplexing system. was there.

An object of the present invention is to enable a cache memory having a bus snoop function to be applied to a multiplexed system.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object. In one aspect, the present invention provides a multiplexed bus comprising a plurality of multiplexed buses. A plurality of main memories, each main memory having a plurality of sets of a multiplexed main memory accessible via any of the buses and a cache memory and a processor, each set being connected to a different bus And a disconnection unit for logically disconnecting the cache memory connected to the malfunctioning main memory from the bus when the malfunction occurs in a certain main memory in the information processing apparatus including the processor unit. Copying means for copying the contents of the main memory to another main memory multiplexed with the main memory, wherein the processor unit becomes usable when the malfunctioning main memory becomes usable. The copying means copies the data to the main memory, then writes the data stored in the cache memory to the main memory, further inhibits the operation of the cache memory, and invalidates the contents. Initialize the separated cache memory, and then release the operation prohibition of all cache memories,
There is provided an information processing apparatus having a function of continuing operation using a processor connected to the main memory which has failed.

In this case, there is provided a buffer means for transferring addresses and data between a cache memory connected to a certain main memory and a cache memory connected to another main memory. When a malfunction occurs in a certain main memory, a function of receiving an address and data on another bus via the buffer means until the malfunctioning main memory is restored, and using the information to continue the operation. May be provided.

According to another aspect of the present invention, a multiplexed bus comprising a plurality of multiplexed buses and a plurality of multiplexed main memories are provided, each of which is connected via one of the buses. An information processing apparatus including: a multiplexed main memory accessible to a plurality of processors; and a plurality of sets of a cache memory and a processor, each set including a processor unit connected to a different bus. When a malfunction occurs in the cache memory, a disconnection unit for logically disconnecting the cache memory connected to the malfunctioning main memory from the bus, a cache memory connected to a certain main memory, and a cache memory connected to another main memory. And a buffer means for transferring addresses and data between the memory and the memory, wherein when a malfunction occurs in a certain main memory, the processor transmits the address and data to the other memory via the buffer means. Receive bus address and data, the information processing apparatus characterized by having a function to continue the operation by using the information is provided.

The information processing apparatus described above has monitoring means for monitoring the operation state of the main memory. The disconnecting means detects the malfunction of the hand memory via the monitoring means. The processor unit may detect, via the monitoring means, a malfunction of the main memory and / or the fact that the malfunctioning main memory has become available.

According to another aspect of the present invention, different addresses are assigned twice as many times as the number of overlapping sets of storage areas in the cache memory which are allocated to the same storage area of the main storage device in an overlapping manner. And a method of updating a cache memory, wherein data is read using the data.

[0019]

The monitoring means monitors whether the bus and the main memory are operating normally. When the monitoring unit detects that the bus is unusable, the disconnecting unit logically disconnects the cache memory connected to the bus from the processor.

In this case, for a processor which is not separated from the cache memory, the processing is continued as it is.
You . On the other hand, the processor disconnected from the cache memory receives the address and data of another bus via the buffer means, and continues the operation using the information.

By replacing the main memory, for example,
When the monitoring means detects that the unusable bus has become usable again, the copying means copies the contents of another main memory multiplexed with the main memory into the main memory which has become usable. Copy to means. When the copying is completed,
With respect to all the cache memories, all the data which is rewritten only in the cache memory and not in the main memory is written in the main memory. Further, the operation is prohibited and its contents are invalidated, and the separated cache memory is initialized. Thereafter, the operation prohibition of all the cache memories is released, and the operation is resumed using the processor connected to the unusable bus.

The invalidation of the cache memory may be performed by the following method.

Data is read using a different address twice as many times as the number of duplicate sets of storage areas in the cache memory which are allocated to the same storage area of the main storage device in an overlapping manner. . Then, even if the address includes all of the addresses already stored in the cache memory (the number of overlapping sets), a cache miss occurs at least as many times as the number of overlapping sets. When a cache miss occurs, data previously stored in the cache memory is stored in the main memory. That is, all data in the cache memory can be updated by causing the same number of cache misses as the number of duplicate sets.

[0024]

Embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to this.

FIG. 1 is a diagram showing an embodiment of the present invention.

The information processing apparatus 1000 includes a processor unit 110, a processor unit 120, a multiplex bus 200, and a multiplex main memory 300.
The multiplexed bus 200 is duplicated and has a bus 210 and a bus 220 which are independent from each other. Similarly, the multiplexed main memory 300 is also duplicated, and has a main memory 310 and a main memory 320 which are independent from each other.

Each of the processor units 110 and 120 is internally redundant, so that even if a failure occurs inside the processor units, the processor units can continue to operate. Note that two processor units (processor unit 1)
10 and 120) are provided not only to improve processing capability but also to improve reliability. For example, when a failure occurs inside the processor unit 110, the processor unit continues to operate and the processor unit 110
Is replaced with a non-defective processor unit 110 ', the processor unit 120 takes over the processing of the processor unit 110 and executes it. When the processor unit 110 is replaced with the processor unit 110', the processor unit 110 ' The operation is resumed, and the operation can be continuously performed from the occurrence of the failure until the replacement of the unit including the failed part is completed.

The inside of the processor unit will be described using the processor unit 110 as an example. As described above, the processor unit 110 is internally redundant to improve reliability, and has two processors that perform exactly the same operation. In order to improve the processing speed, each processor has a cache memory 41.
1 and a cache memory 412 are provided. The cache memory is also duplicated for high reliability, and is connected to each of the duplicated buses. That is, the cache memory 411 is connected to the bus 210 by the cache memory 4.
12 is connected to the bus 220.

Since the information processing apparatus of this embodiment has a multi-processor configuration of shared main memory, the cache memories 411 and 412 have bus snoops substantially equivalent to those cited in the section of the prior art. Has a function. The bus snoop function is provided by snoopers 1411 and 141 built in cache memories 411 and 412.
The snooper 1411 of the cache memory 411 monitors the bus 210, and the snooper 1412 of the cache memory 412 monitors the bus 220, and checks the cache memory in the processor unit 110 and the cache memory in the processor unit 120. Perform matching control. FIG. 5 shows a state transition matrix of the cache memory, but the details of the bus snoop function are not the gist of the present invention, and thus the description thereof is omitted.

In addition to the above, the processor unit includes a copy unit.
It has a controller 610, a check mechanism 510, and the like. The copy controller 610 has a function of copying data between the main storage 310 and the main storage 320. The details will be described together with the operation description described later. The check mechanism 510 monitors whether the main memory or the bus is operating normally by monitoring the operation of the cache memory or the like. However, the specific method of detection is not limited to this, and may directly monitor the operation states of the main memory and the bus.

The main memory is realized by a hard disk, a semiconductor memory, or the like. However, it is not limited to this.

Hereinafter, the bus 210 of the multiplexed bus 200
Becomes inoperable due to the failure of the main memory 310, the main memory 310 is replaced with a non-defective main memory 310 ′,
Control of the cache memory until the bus 210 becomes operable again will be described with reference to the flowchart of FIG.

[0033] When the main memory 310 fails, the bus 210 becomes inoperable. Note that the “failure of the main memory” here is not limited to the main memory 310 alone, but
This concept includes even a failure of the bus 210.

When the bus 210 becomes inoperable (step 31), the operations of the snooper 1411 of the cache memory 411 and the snooper 1412 of the cache memory 412 become inconsistent, and the check mechanism 510 detects an abnormality in the cache memory 411. Is done. Then, the bus interface 811 stores the cache memory 411 in the bus 21.
Separate from 0 (step 32).

Until the main memory 310 is replaced with a non-defective main memory 310 ', the bus 22 in which no failure has been detected.
Only 0 is an online system and the operation is continued. That is, the processor unit 110 includes the cache memory 4
Processing is continued using only 12. In parallel with this, the processor unit 110 continues to monitor whether or not the cause of the failure of the bus 210 has been removed (step 33). When the main memory 310 is replaced with a non-defective main memory 310 ',
The copy controller 610 stores the online main memory 3
From step 20, the data is copied to the main storage 310 '(step 34). In this embodiment, the copy controller is built in the processor unit 110, but may be located in a place other than the processor unit 110 as long as it is a unit connected to both systems of the multiplex bus 200. .

The copy is apparently executed in parallel with the processing of the information processing apparatus. That is, when the bus 200 is not used, the copy controller 610 copies data of a fixed number of words from the main memory 320 to the main memory 310 '. During this time, the bus 200 is occupied (reserved) so that other bus masters cannot use it. The copy controller 610 reads data from the online main memory 320. On the other hand, data is written to both the main memories 320 and 310 '. The reading and writing of the main memory during copying by the copy controller 610 is performed by using a different command from the reading and writing of the main memory by the normal bus master. This is because there is no need for a snooper to control cache memory matching.

During this time, the processor units 110 and 120 read and write the main memories 320 and 3
The processing is performed for both systems 10 ', but the processing is performed using only the data read out from the online main storage 320 among the read data. This is because the contents of the main memory during the recovery from the failure and the contents of the online main memory are partially inconsistent.

When the copying is completed, the processors 110 and 120 update only the cache memory in the processor unit, and write all the data whose main storage has not been updated to the main storage (step 35).

In this embodiment, software is used to read all cache memory addresses from a main memory address of twice the number of cache memory sets, and a cache memory miss is intentionally generated. This is realized by causing replacement (replacement) with all cache memory addresses and sets.

Hereinafter, in this embodiment, the cache memory 4
Assuming that the cache memories 11 and 412 are the cache memories of the two-way set associative system, the reason why the reading is performed for the main memory addresses of twice the number of sets of the cache memories will be described.

In the two-way set associative cache memory, two pieces of data of an address having the same bit used for accessing the cache memory in the main memory address exist in the cache memory. For example, in an information processing device having a main memory address of three digits in hexadecimal, an address used for cache memory access
It is assumed that the hexadecimal number of the main storage address is the last two digits. At address 00 of the cache memory, two pieces of data whose lower two digits are 00 in hexadecimal of the main storage address can be stored.

Here, it is assumed that the data of the main memory address 100 and the data of the main memory address 200 are stored at the address 00 of the cache memory. When both of these are rewritten by the processor unit and the main memory is not rewritten, two main memory addresses, which are neither address 100 nor address 200 and whose last two digits are 00 in hexadecimal, For example, if addresses 300 and 400 are not accessed, the replacement of the cache memory does not occur, and neither data whose main memory has been rewritten cannot be written to the main memory.

On the other hand, the main memory address of the data stored in the cache memory is normally not known from the processor unit, and the processor unit can access the main memory by accessing any two main memory addresses. It is not known whether both unwritten data can be written to the main memory. Even if the main memory address of the data stored in the cache memory is known from the processor unit, the processor unit checks the main memory address of the data stored in the cache memory and accesses the main memory. If the cache memory is accessed after the address is determined, the processing time will be long.

Therefore, in this embodiment, if a certain cache memory address is read out with four types of main storage addresses, two of the main storage addresses are the main storage addresses of the data stored in the cache memory. Even if they match, attention is paid to the fact that a cache memory miss occurs at least the remaining two times. That is, when a cache miss occurs, the data in the cache memory becomes
Replaced with the data in main memory. At the same time, data that has been rewritten only in the cache memory but not in the main memory is stored in the main memory. By executing this for all cache memory addresses, the main memory unrewritten data in the cache memory is
All can be stored in main memory.

[0045] After writing into the main memory of the main memory un rewrite data in the cache memory 412 is completed, the processor unit 110 prohibits the operation of the cache memory 412 (Step 3 6), a cache memory 412 and snoop - the path 1412 Disable all tags (Step 3
7 ). Further, the processor unit 110 clears the error state of the snooper 1412 of the cache memory 411 (step 38), and releases the operation prohibition of the cache memories 411 and 412 (step 39). Thereafter, the cache memories 411 and 412 resume normal operation. At this point, there is no data rewritten by the processor in the cache memory, so that even if the snooper directory is in the initial state, there is no mismatch with the cache memory.

In this embodiment, a software program for performing a series of these controls is stored in a read-only memory (not shown) provided in the processor unit 110. This is because when these programs are stored in the main memory, it is necessary to access the main memory during execution of the program, thereby preventing the control from becoming complicated.

Thus, even if one of the multiplexed buses 200, for example, the bus 210, becomes inoperable, the processor unit 110 can continue to operate. When the cause of the inoperability of the bus 210 is removed and the bus 210 becomes operable again, the consistency of the cache memories is guaranteed.

Another embodiment will be described.

The information processing apparatus of this embodiment is different from the above embodiment in the internal configuration of the processor unit 110. The basic configuration of the entire apparatus is the same.

FIG. 2 shows the processor unit 11 of this embodiment.
0 shows the internal configuration. In this embodiment, the bus buffer 7 is provided so that the information of the bus interface can be transferred between the cache memories 411 and 412.
10 are provided. That is, the bus buffer 710 is normally in a high impedance state,
When the bus is disabled, the bus buffer 710 causes the bus 220 and the cache memory 411 to be logically connected. When the bus 220 is disabled, the bus buffer 710 controls the bus 210 and the cache memory 412.
Function to be logically connected.

Hereinafter, the bus 210 of the multiplexed bus 200
Becomes inoperable due to the failure of the main memory 310, the main memory 310 is replaced with a non-defective main memory 310 ′,
Control of the cache memory until the bus 210 becomes operable again will be described with reference to the flowchart of FIG.

When a failure is detected in the main memory 310, the bus 210 becomes inoperable (step 41). Bus 210
Becomes inoperable, the bus interface 811 logically disconnects the cache memory 411 from the bus 210. On the other hand, the bus buffer 710 logically connects the bus 220 to the cache memory 411. During this time, the cache memory 411 continues to operate based on the information on the bus 220 (Step 42). In parallel with this, the processor unit continues to monitor whether or not the cause of the failure of the bus 210 has been removed (step 43).

The main memory 310 'is a non-defective main memory 310'.
When the cause of the failure of the bus 210 is removed by the exchange or the like, the data of the main memory 320 is copied to the main memory 310 'by the copy controller 610. When the copying of the data is completed, the bus buffer 710 becomes the high impedance state again, and the cache memory 41
1 is logically connected to the bus 210 after being disconnected from the bus 220, and continues processing based on the information on the bus 210 (step 44).

In this way, even if one of the multiplexed buses 200 becomes inoperable, the processor unit 110 can continue to operate.
Even if the factor that has become inoperable is removed and operation becomes possible again, consistency of the cache memories is guaranteed.

[0055]

According to the present invention, a cache memory can be used in an information processing apparatus in which main components are multiplexed,
In addition, there is an effect that the main memory sharing type multiprocessor configuration can be obtained. In this case, even if a failure occurs, the operation can be continued, and at the time of recovery from the failure, loss of data existing in the cache memory can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a flowchart showing processing from the occurrence of a failure in the main memory 310 to the replacement of the main memory 310 'and the return to the normal operation in the first embodiment.

FIG. 4 shows a main memory 310 according to a second embodiment of the present invention.
5 is a flowchart showing processing from the occurrence of a failure to the return to normal operation after being replaced by the main memory 310 '.

FIG. 5 is a diagram showing a state transition of a cache memory according to an embodiment of the present invention.

[Explanation of symbols]

110 processor unit, 120 processor unit, 200 multiplexed bus, 210 bus, 2
20 bus, 300 multiplexed main memory, 310 main memory, 320 main memory, 411 cache memory, 412 cache memory, 510 check mechanism, 610 copy controller, 710 ..Bus buffer, 811..Bus interface, 812 ..
Bus interface, 1000 information processing devices, 14
11. Snooper, 1412 Snooper

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Soichi Takaya 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Nobuyasu Kanakawa 4026 Kujimachi, Hitachi City, Ibaraki Co., Ltd. Hitachi, Ltd.Hitachi Laboratory (72) Inventor Hiroshi Watanabe 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Omika Plant (72) Inventor Toshio Matsumoto 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture (72) Inventor Kazuji Yokoyama 5-2-1 Omikacho, Hitachi City, Ibaraki Pref. Hitachi, Ltd. Omika Plant (56) References JP-A-2-17550 (JP, A) JP-A-2-147475 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 15/163 G06F 12/08

Claims (5)

(57) [Claims] 1. A multiplexed bus comprising a plurality of multiplexed buses, and a plurality of multiplexed main memories, each main memory comprising:
Information comprising: a multiplexed main memory accessible via any of the buses; and a processor unit having a plurality of sets of a cache memory and a processor, each set being connected to a different bus. In the processing device, when a malfunction occurs in a certain main memory, a disconnecting means for logically separating the cache memory connected to the malfunctioning main memory from the bus, and multiplexing the contents of the certain main memory with the main memory. And copying means for copying to another main memory, wherein the processor unit is multiplexed when the malfunctioning main memory becomes available.
The data is copied from the other main memory to the available main memory by the copying means, and then the data stored in the cache memory that has been operating is written to the main memory. Additionally, or disable the prohibition and the contents of the operation of the cache memory, also the disconnected cache memory is initialized, then with the operation prohibition Ru solutions dividing <br/> function of all of the cache memory An information processing apparatus characterized by the above-mentioned. 2. The system according to claim 2, further comprising buffer means for transferring addresses and data between a cache memory connected to a certain main memory and a cache memory connected to another main memory. When a malfunction occurs in the main memory, the address and data on another bus are received via the buffer means until the malfunctioning main memory is restored,
The information processing apparatus according to claim 1, further comprising a function of continuing the operation using the information. 3. A multiplexed bus comprising a plurality of multiplexed buses and a plurality of multiplexed main memories, each main memory comprising:
Information comprising: a multiplexed main memory accessible via any of the buses; and a processor unit having a plurality of sets of a cache memory and a processor, each set being connected to a different bus. In the processing device, when a malfunction occurs in a certain main memory, a disconnecting unit that logically separates the cache memory connected to the malfunctioning main memory from the bus, a cache memory connected to the certain main memory, and another A buffer unit for transferring addresses and data to and from a cache memory connected to the main memory, wherein the processor is configured to transmit the address and data to the other memory via the buffer unit when a malfunction occurs in the main memory. An information processing apparatus having a function of receiving an address and data of the bus and continuing the operation using the information. 4. A monitoring means for monitoring an operation state of the main memory, wherein the disconnecting means detects a malfunction of the main memory via the monitoring means, and the processor controls the operation state of the main memory via the monitoring means. 4. The information processing apparatus according to claim 1, wherein the malfunction of the main memory and / or the fact that the malfunctioning main memory becomes available are detected. 5. A method of reading data by using a different address twice as many times as the number of overlapping sets of storage areas in the cache memory which are allocated to the same storage area of the main storage device in an overlapping manner. A cache memory updating method.