JPH06259269A - Diagnostic circuit for multiprocessor - Google Patents

Abstract

PURPOSE:To specify a fault multiprocessor (MPU) in the case of error generation with a diagnostic method for detecting the fault of the MPU by duplexing the MPU and comparing the addresses and data. CONSTITUTION:This circuit is provided with a mechanism equipped with a built-in cache 10 so as to make invalid a comparator circuit for the address and data outputted from a duplex MPU 1 and to enable operations with only one MPU and a means for reading the data of an LSU 3 at the address shown by a comparative address, setting them to an LSU-Data 24 and comparing them with the contents of comparative data 21 corresponding to the instruction of the LSU 3 at the address shown by the comparative address register 20 according to data in the built-in cache, data 24 in a local strage unit 23 and an instruction from the MPU 1. Then, the data in the cache storage circuit built in the MPU 1 are compared with the data of the LSU at each MPU, and the fault MPU is specified.

Description

Detailed Description of the Invention

[0001]

This invention relates to a multiprocessor (MP
U) is duplicated and the duplicated multiprocessor (MPU)
The present invention relates to a diagnostic circuit in a computer system that detects a failure of a multiprocessor by comparing the addresses and data of each.

With the recent diversification of data processing, a plurality of processors (MPUs), for example, bus controllers (BC)
A multiprocessor system has been constructed in which a plurality of multiprocessors (MPUs) perform the various data processes described above while being connected to each other and communicating with each other.

Further, with the recent improvement in the degree of integration of semiconductors,
In order to improve the processing capacity of such a multiprocessor system, each multiprocessor (MPU) has a built-in large capacity cache memory circuit.

Therefore, there is a high possibility that each multiprocessor (MPU) will fail, and the multiprocessor (MPU)
Are duplicated, run the same program, and compare the address and data.
A high-reliability multiprocessor system that detects a failure of (PU) is built, but when a comparison error occurs,
It was difficult to identify the failed multiprocessor (MPU), and in the worst case, it was necessary to replace two duplicated multiprocessors (MPU).

Under these circumstances, there is a need for a multiprocessor diagnostic circuit capable of effectively detecting the fault side of a dual multiprocessor (MPU).

[0006]

2. Description of the Related Art FIG. 4 is a diagram for explaining a conventional diagnostic circuit for a dual MPU. The multiprocessor system shown in FIG. 4 has a bus controller (BC) 5
A plurality of multiprocessors (MPU) 1 execute different programs and data stored in, for example, a local storage unit (LSU) 3 in each of the multiprocessors (MPU) 1 while communicating with each other.

As described above, in order to improve the processing capacity of such a multiprocessor system with the recent increase in the degree of integration of semiconductors, each multiprocessor (MPU) 1 is provided with a large capacity cache memory circuit 10. Is being done.

Therefore, there is a high possibility that each multiprocessor (MPU) 1 will fail, and as shown in this figure, the multiprocessor (MPU) 1 is duplicated and the same program is run. Address, data, address,
A highly reliable multiprocessor system for detecting a failure of the multiprocessor (MPU) 1 is constructed by performing comparison by the data comparison circuit 26.

[0009]

[Problems to be Solved by the Invention]
In a duplicated system, it is difficult to identify the failed multiprocessor (MPU) 1 when a comparison error occurs, and in the worst case, it is necessary to replace two duplicated multiprocessors (MPU) was there.

If the multiprocessor (MPU) 1 is not mounted in the socket, the failed multiprocessor (MPU)
If there is no means to identify PU) 1, both boards equipped with such multiprocessor (MPU) 1 will be discarded.

In view of the above-mentioned conventional drawbacks, the present invention provides a comparison error in a multiprocessor system which detects a failure of the multiprocessor (MPU) by duplicating the multiprocessor (MPU) and comparing addresses and data. It is an object of the present invention to provide a diagnostic circuit capable of identifying a faulty multiprocessor (MPU) in the case of occurrence of a fault.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. The above problem is solved by a multiprocessor diagnostic circuit configured as follows.

(1) A main memory circuit 3 in which programs and processing data are stored and which can be read and written, and the main memory circuit 3
A multiprocessor 1 incorporating a cache memory circuit 10 having a copy of the data stored in the multiprocessor 1 and a plurality of the multiprocessor 1 are connected to each other, and the same program is run to compare the output address / data. Circuit 26
And a main memory control unit 23 that controls main memory in response to a main memory access request from the multiprocessor 1 and the multiprocessor 1 writes data to the main memory circuit 3, In a processor module having a memory control circuit 2 having a function of invalidating a predetermined block of the internal cache memory circuit 10, the data of the internal cache memory circuit 10 of the multiprocessor 1 and the data of the main memory circuit 3 are compared. By the comparison address register 20 that stores the address, the comparison data register 21 that stores the read data of the multiprocessor 1, and the instruction from the multiprocessor 1,
Read the data in the main memory circuit 3 at the address indicated by the comparison address register 20, set it in the main memory data register 24, and compare the content of the comparison data register 21 with the comparison circuit 22 in the memory control circuit 2. In addition, the internal cache memory circuit 10 of the multiprocessor 1 and the main memory circuit 3 are compared with each other by the comparison circuit 22 to detect a failure of the multiprocessor 1.

(2) In the above processor module,
By disabling the comparison circuit 26 that compares the address and data output from multiple multiplexed multiprocessors 1 and switching the address and data to the address and data of one of the multiprocessors 1, one multiprocessor A switching means 25 that operates only by 1 is provided, and a faulty multiprocessor 1 is determined by running a predetermined diagnostic program on one of the switched multiprocessors 1 described above.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. For example,
A switch circuit that disables the address output from two duplexed multiprocessors (hereinafter sometimes referred to as MPU), the address that compares data, and the data comparison circuit, and that operates only on one of the MPUs, A comparison address register (Comp-Address) that stores an address for comparing the data in the cache memory circuit built into the MPU with the data in the local storage unit (main memory circuit) (hereinafter, also referred to as LSU), and the MPU read data ( A comparison data register (Comp-Data) for storing the data of the internal cache storage circuit when the internal cache storage circuit is hit.
Then, in response to an instruction from the MPU, the LSU data at the address indicated by the comparison address register (Comp-Address) is read out, and the main memory data register (LS
U-Data), a memory control circuit (hereinafter, sometimes referred to as MCM) has a comparison circuit for comparing with the comparison data register (Comp-Data), and one MPU has a predetermined diagnostic program. The MPU built-in cache and the LSU are compared with each other, and the failed MPU is specified.

The duplicated multiprocessor (M
PU) when a comparison error occurs while running the same program, the address / data comparison circuit is invalidated, and the address / data / control lines are switched to only one of the MPUs. When a diagnostic program for comparing data between the internal cache and the LSU is run and a mismatch is detected, the MPU that has just run can be identified as the failed MPU, so that the repair cost can be reduced.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings. The above-mentioned FIG. 1 is a principle configuration diagram of the present invention, and FIG.
FIG. 3 is a diagram showing an embodiment of the present invention.
3 shows a control method of the cache memory circuit, and FIG.
FIG. 4 is a flowchart showing the operation of the diagnostic program according to the present invention.

In the present invention, the cache memory circuit 1
A multiprocessor that has 0 and compares the address and data output from the duplicated multiprocessor (MPU) 1 with the address and data comparison circuit 26 to compare the normality of the multiprocessor (MPU) 1. In the processor module, the switching circuit that disables the address / data comparison circuit 26 and operates with only one of the MPUs 25
And the data of the cache memory circuit 10 with built-in MPU and the local storage unit, for example, the main memory circuit (LSU).
According to the instructions from the comparison address register (Comp-Address) 20 that stores the address to compare the data of 3, the comparison data register (Comp-Data) 21 that stores the read data of MPU, and the instruction from the multiprocessor (MPU) 1. The data in the main memory circuit (LSU) 3 at the address indicated by the comparison address register (Comp-Address) 20 above is read and set in the main memory data register (LSU-Data) 24.
(Comp-Data) 21 and a comparison circuit 22 for comparing
The data in the cache memory circuit 10 with built-in MPU and the data in the main memory circuit (LSU) 3 are compared to each multiprocessor (MP
The means for identifying the failed MPU performed in U) 1 is the means necessary for implementing the present invention. The same reference numerals indicate the same objects throughout the drawings.

The configuration and operation of the diagnostic circuit of the multiprocessor according to the present invention will be described below with reference to FIGS. As described above, MPU 1 is duplicated {MPU (# 0), MPU (# 1)} and normally runs the same program. Memory control circuit (MCM) 2 is MPU
(# 0) / MPU (# 1) 1 / L from the bus controller (BC) 5
Read / write to LSU 3 according to SU access request
Perform write access.

The address / data of the MPU (# 0) 1 and MPU (# 1) 1 are compared by the address / data comparison circuit 26,
The health of MPU 1 is constantly checked. {Refer to FIG. 4} Further, as described above, the MPU 1 includes the built-in cache memory circuit (built-in cache) 10 for improving the performance, and FIG. 2 shows a control method of the cache memory circuit 10.

That is, the MPU 1 receives the address H "80000.
When "00" is read, the internal cache memory circuit 10
Of the internal cache memory circuit 10 and read the data (data “A”) from the built-in cache memory circuit 10.
Next, when the MPU 1 reads the address H “8000010”, if it is not registered in the internal cache memory circuit 10, the data (data ') of the address is sent from the LSU 3.
E ') and the block to which the address belongs (data')
F ',' G ',' H ') are read and registered in the built-in cache memory circuit 10 (usually a replacement operation is performed).

Next, the MPU 1 sends the address H "80000.
When reading 14 ", the internal cache memory circuit 10
Read data from. If the MPU 1 / BC 5 is the LS of the data registered in the internal cache memory circuit 10.
When updating on U 3, MCM 2 must invalidate the registration data. That is, MPU 1 /
When BC 5 writes to address H “80000A0” of LSU 3, BI controller 27 in MCM 2
H registered in the PU built-in cache memory circuit 10
"80000A0" is invalidated.

As described above, in recent years, in order to improve the performance of the MPU, the capacity of the built-in cache memory circuit 10 has been increased, and the built-in cache memory circuit 10 may be damaged, for example, a certain bit of data may be corrupted. The nature is getting higher.

Therefore, in the present invention, when the duplicated MPU 1 causes a comparison error, a test including the built-in cache memory circuit 10 is carried out, and a failure MPU is executed.
Try to identify 1.

The test method including the built-in cache memory circuit 10 will be described in detail with reference to the flow chart of FIG. When a comparison error occurs during the operation of comparing the address and data between the above-mentioned normal duplicated MPU 1, for example, the MPU (#) is instructed by the service processor (SVP) 4 shown in FIG. 0) Stop the MPU (# 1) 1 to operate the diagnostic program only with 1.

In this case, the address / data comparison circuit 26 shown in FIG. 4 is invalidated, and the switching circuit 25 of FIG. 1 separates the address and data on the MPU (# 1) 1 side, and then the separated MPU ( # 1) 1 is stopped, MPU (# 0)
Allow the diagnostic program to run for side 1. {Refer to processing step 100 in FIG. 3} If the diagnostic program results in an error, the failed MPU is MP
It can be determined as U (# 0) 1. {Refer to processing step 101 in FIG. 3} Next, in order to diagnose the internal cache memory circuit 10 of the MPU (# 0) 1, the diagnostic program of the present invention first
Comparison address register (Comp-Address) 20
Set the address of the main storage unit (LSU) 3 to. {Refer to processing step 102 in FIG. 3} The comparison address register (Comp-Address
s) When the read operation is performed with the address set in 20, if the data of the corresponding address is registered in the internal cache memory circuit 10, the data of the internal cache memory circuit 10 can be read, but if it is not registered. Reads the data at the corresponding address from the main memory (LSU) 3,
Although it is also registered in the cache memory circuit 10, at this time, the read data is stored in the comparison data register (Comp-Da).
ta) Set to 21.

At this point, when a compare start instruction is issued, the memory control circuit (MCM) 2 reads data from the main memory unit (LSU) 3 at the address set in the comparison address register (Comp-Address) 20. Is read out and set in the main memory data register (LSU-Data) 24, then the comparison data register (Comp-Da)
ta) 21 is compared with a comparison circuit (Compare) 22. The compare process is performed for all addresses of LSU 3.

When the contents of the cache memory circuit 10 and the contents of the main memory unit (LSU) 3 are compared, what is done for all the addresses of the main memory unit (LSU) 3 is the aforementioned internal cache memory circuit. 10 is a part of MPU 1
This is because the contents of the TAG cannot be referenced from the outside because they are integrated and built in one integrated circuit (one chip).

If an error is detected in the test of the cache memory circuit 10, the MPU (# 0) 1 is regarded as a failure. {Refer to the processing steps 103 to 107 in FIG. 3} Next, the address / data / control line is switched by the service processor (SVP) 4, and the MPU (# 1) 1 alone operates the same diagnostic program. (# 0) 1 is stopped. {Refer to processing step 108 of FIG. 3} By running the same diagnostic program as above,
The failed MPU can be identified as MPU (# 1) 1.

As described above, the multiprocessor diagnostic circuit of the present invention invalidates the address / data comparison circuit output from the duplicated multiprocessor (MPU) having the cache memory circuit, and either one of them is invalidated. , A comparison address register (Comp-Address) that stores the address that compares the data in the cache memory circuit built into the MPU with the data in the main memory (LSU), and the MPU.
Comparison data register (Comp-Dat) that stores read data
a) and the instruction from the MPU, read the LSU data at the address indicated by the comparison address register (Comp-Address) and set it in the main memory data register (LSU-Data).
By providing a means for comparing with the above comparison data register (Comp-Data), the data of the cache memory circuit built in the MPU and the data of the LSU are compared in each MPU to identify the failed MPU. There are features.

[0031]

As described above in detail, according to the diagnostic circuit of the multiprocessor of the present invention, a comparison error occurs when the same program is run in the duplicated multiprocessor (MPU). If it occurs, the address / data comparison circuit is invalidated, the address / data / control line is switched to only one MPU, and a diagnostic program for comparing the data between the MPU built-in cache and the LSU is run. , When a mismatch is detected,
Since the failed MPU can be specified for the MPU that has just traveled, the effect of reducing the repair cost can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing an embodiment of the present invention (part 2).

FIG. 4 is a diagram for explaining a diagnostic circuit of a conventional duplexed MPU.

[Explanation of symbols]

1 Multiprocessor {MPU (# 0), (# 1), MPU} 10 Internal cache memory circuit (internal cache) 2 Memory control circuit (MCM) 20 Comparison address register (Comp Address) 21 Comparison data register (Comp-Data) 22 Compare circuit (Compare) 24 Main memory data register (LSU-Data) 25 Switching circuit 26 Address,
Data comparison circuit 3 Main storage unit (LSU), local storage unit (L
SU) 4 Service processor (SVP) 5 Bus controller (BC) Access request Compare START instruction Diagnostic program 100 to 108 Processing steps

Claims (2)

[Claims] 1. A main memory circuit (3) in which a program and processing data are stored and which can be read and written, and the main memory circuit.
A multiprocessor (1) containing a cache memory circuit (10) having a copy of the data stored in (3) and a plurality of such multiprocessors (1) are connected, and the same program is run and output. A comparison circuit (26) for comparing the generated address / data, a main memory control unit (23) for controlling a main memory by a main memory access request () from the multiprocessor (1), and the multiprocessor (1 ) Writes data to the main memory circuit (3), the memory control circuit (2) has a function of invalidating a predetermined block of the internal cache memory circuit (10) of the multiprocessor (1). In the processor module including the above, a built-in cache memory circuit (1
0) and the comparison address register (20) that stores the address that compares the data in the main memory circuit (3), and the comparison data register that stores the read data of the multiprocessor (1)
(21) and the instruction from the multiprocessor (1) read the data in the main memory circuit (3) at the address indicated by the comparison address register (20) and store it in the main memory data register.
The memory control circuit (2) has a comparison circuit (22) that is set to (24) and compares with the contents of the comparison data register (21), and the built-in cache memory circuit () of the multiprocessor (1) ( 1
0) and the main memory circuit (3) for data comparison,
A multi-processor diagnostic circuit characterized by detecting a failure of the multi-processor (1) by carrying out in (22). 2. In the processor module, a comparison circuit (26) for comparing addresses and data output from a plurality of multiplexed multiprocessors (1) is invalidated so that the addresses and data are transferred to one of the multiprocessors. Processor (1)
By providing a switching means (25) that operates only by one multiprocessor (1) by switching to one of the addresses and data, a predetermined diagnostic program () is run on one of the switched multiprocessors (1). A diagnostic circuit for a multiprocessor, characterized by determining a faulty multiprocessor (1).