JPH0936863A - Redundancy system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continue the processing without re-processing up to a fault occurrence point of time on the occurrence of a fault of a main storage device in the redundancy system. SOLUTION: On the detection of abnormality in a 1st main storage device 12, a bus interface circuit 1A of a 1st central processing unit reports the occurrence of the abnormality to a 1st standby system main storage access circuit 1B. The 1st standby system main storage access circuit 1B gives a read request to a 2nd main storage device 22. Then substitute data are acquired and they are returned to a 1st microprocessor 19 together with a normal response and the normal response is reported by using the substitute data through a 1st standby system main storage substitute interrupt request line 1C. The program receiving the interrupt request executes the processing up to a good step to leave off and selects a 2nd sub system through changeover for the further processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system provided with a plurality of data processing devices serving as an operating system or a standby system, and can be applied to, for example, a control configuration in an electronic exchange.

[0002]

2. Description of the Related Art Nowadays when telephones have become commonplace, system downs in electronic exchanges must be avoided as much as possible, and redundant systems are adopted as the main components of electronic exchanges. For example, a redundant system is adopted for the central control module that controls the electronic exchange.

FIG. 2 shows a conventional system of a redundant system adopted in such a central control module, that is, a duplicated computer system.

The device configurations of the first subsystem 10 and the second subsystem 20 are the same. When the power is turned on, one becomes the active system and the other becomes the standby system. The active central processing unit 11 or 21 can read and write each device of the active system, and uses the inter-subsystem connection devices 13 and 23 and the inter-subsystem connection line 30 to store the main storage device 22 or 12 in the standby system. You can read and write. In the active system, if any hardware failure occurs at the time of initial setting and process execution, the subsystem 20 or 10 of the standby system is switched to and the process is restarted. The central processing unit 21 of the standby system
Or 11 is stopped.

As an initial setting after the power is turned on, an instruction word and data for executing a process in the computer system are provided by the central processing unit 11 or 21 to the bus 15 in the subsystem.
Or 25 to read from the input / output device 14 or 24 and write to the main storage device 12 or 22. When writing to the main storage device 12 or 22 of the operating system by the central processing unit 11 or 21, the inter-subsystem connection devices 13 and 23
And the inter-subsystem connection line 30 transfers data to the standby system subsystem internal bus 25 or 15 at an address different from that of the operating system main storage device 12 or 22, and also to the standby system main storage device 22 or 12 at all. Write the same command word and data.

After completion of the initial setting, the central processing unit 11 or 2
The instruction word stored in the active main storage device 12 or 22 is read by 1 and the process is executed. The data stored in the active main storage device 12 or 22 is read and written as necessary. When writing to the active main memory 12 or 22, the contents of the active main memory 12 or 22 and the standby main memory 22 or 12 are always kept in the same state as described above.

Further, since it is sometimes necessary to complete one or more series of processes within a certain time, checkpoints are provided at points where these processes are well separated, and execution is completed for each checkpoint. Results in main memory 1
Process execution progress data storage unit 18 or 28 in 2 and 22
The process is executed while being stored in.

The main storage device 12 or 22 is a storage element circuit 1
6 or 26 and the storage data failure detection circuit 17 or 27, the storage data failure detection circuit 17 or 27 is stored in the storage element circuit 16 or 26 when reading or writing to the main storage device 12 or 22. If the data is tested and an abnormality is detected, an abnormal response is returned to the central processing unit 11 or 21.

When the first subsystem is the active system, after the central processing unit 11 receives the abnormal response, the first subsystem 1
Since it becomes impossible to continue the process at 0, the first subsystem 10 and the second subsystem 20 are switched to continue the process. As a result, the second subsystem 20 becomes the active system and the first subsystem 10 becomes the standby system. At this time, the initial setting data is not transferred from the input / output device 24 to the main storage device 22, and the process execution progress data storage unit 18
Further, by executing the process after the completion of execution stored in 28 as a subsequent process, it is possible to resume the process takeover.

In addition, the data for which the abnormality is detected is an instruction word,
As an alternative to that, an example of the processing in the case where the same data in the standby main memory is assumed to be used will be described with reference to FIG.

(B) The address where the same data is stored in the standby main memory is calculated.

(B) The alternative data is read from the main memory of the standby system, the instruction word is analyzed, and when the parameter of the instruction word has address information, the parameter is converted,
Copy to another area of the main storage of the operating system.

(C) The address of the instruction word to be executed next is found in the main memory of the operation system based on the address of the detected data and the information obtained from the instruction word analysis of (ii).

(D) By executing the instruction word copied to another area of the main memory of the operating system, and then executing the instruction word at the address calculated in (c), the processing after the occurrence of the abnormality is continued. To do.

[0015]

In the conventional redundant system, when an error occurs in the data transfer to the main memory between check points, the processing from the check point immediately before the error to the time of the error occurrence is invalidated, Since the active system and the standby system are switched, there is a problem that the processing from the checkpoint immediately before the occurrence of the abnormality to the time of the abnormality is wasted.

Assuming that the same data in the standby main memory is used as a substitute for the data for which an abnormality has been detected, if the data for which an abnormality has been detected is an instruction word, it can be used for instruction word analysis or address calculation. Since it takes time, it was difficult to complete the treatment within a fixed time.

[0017]

According to the present invention, there is provided a main storage device having a read data abnormality detection unit, a main storage input / output unit for accessing the main storage device, and a data processing unit having a processing execution unit. In a redundant system having a plurality of data processing devices equipped with one of the data processing devices as an active system and another data processing device as a standby system, each of the data processing devices has its own active system. It is characterized by comprising the following means that function in each case.

That is, (A) an abnormal response suppressing unit that suppresses notifying the main memory input / output unit of the abnormal response when the abnormal detecting unit detects an abnormality, and (B) this exception processing state. When the process shifts to, the alternative data of the read data relating to the abnormality is taken out from the main memory of one of the data processing devices of the standby system, and a normal response is returned to the main memory input / output means together with the alternative data. A data fetching unit and (C) an exception process notifying unit for notifying the process executing unit of having returned a normal response together with the alternative data.

[0019]

[Operation] When the abnormality detection unit detects an abnormality, it is equipped with an abnormal response suppression unit that suppresses notifying the main memory input / output unit of the abnormal response, thereby switching between the active system and the standby system. Temporarily suppress. In addition, by the alternative data extracting unit that extracts the alternative data of the read data relating to the abnormality from the main storage device of any one of the data processing devices of the standby system and returns a normal response to the main storage input / output unit together with the alternative data. After performing the processing using the alternative data in the same manner as normal, and performing the processing up to the point where the processing is separated by the exception processing notification section that notifies the processing execution section that a normal response is returned with the alternative data ,
Switch to the standby system.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a redundant system according to the present invention is applied to a redundant computer system will be described in detail below with reference to the drawings.

(Structure of Embodiment) FIG. 1 is a block diagram showing the entire structure of this embodiment, in which the same or corresponding portions as those of FIG. 2 according to the prior art are designated by the same reference numerals.

In FIG. 1, the duplicated computer system of this embodiment is also similar to the conventional system and each subsystem 1
Central processing units 11 and 21, main storage devices 12 and 22, input / output devices 14 and 24, intra-subsystem buses 15 and 25, and inter-subsystem connection device 1
3 and 23 and an inter-subsystem connection line 30 that connects the two subsystems 10 and 20. Main storage device 11 and 2
Since the configuration other than 1 functions in the same manner as the conventional one, the description thereof will be omitted.

The central processing unit 11 or 21 in this embodiment differs from the conventional one in that it has a microprocessor 19 or 29, a central processing unit bus interface circuit 1A or 2A, and a standby main memory access circuit 1B or 2B.
The main memory substitute interrupt request line 1C or 2C is provided. Central processing unit bus interface circuit 1A or 2
A is the main memory 12 or 22 to the microprocessor 1
The standby main memory access circuit 1B or 2B suppresses an abnormal response to 9 or 29.
The substitute data is acquired from the step 2, and the substitute data is returned to the operational microprocessor 19 or 29 together with the normal response. Further, the main memory substitute interrupt request line 1C or 2C is
The microprocessor 19 or 29 is notified that a normal response has been returned together with the substitute data.

The microprocessor 19 or 29 in the operating system central processing unit 11 or 21 issues a read request to the operating system main storage device 12 or 22 together with the address of the instruction word or the data handled in the processing thereof in the subsystem bus 15 or 25.
To transfer. Upon receiving the read request, the main storage device 12 or 22 extracts the data from the storage element circuit 16 or 26 by using the address, and then transfers the read data to the storage data failure detection circuit 17 or 27.

When data is written in the main storage devices 12 and 22, redundant bits are added to the write data for each fixed unit according to a fixed rule in advance. In the failure detection circuit, when the data in the main storage device 12 or 22 is read, the relationship between the data and the redundant bit is
Test if it follows the rules for writing. If the test result is normal, the subsystem bus 15 or 25
The data is sent back to the central processing unit 11 or 21 together with the normal response via.

(Operation of Embodiment) In the above system,
An operation when a failure of the main storage device occurs when the first subsystem is the active system will be described. When an abnormality is detected in the normality test in the main memory unit 12 of the operating system, the main memory unit 12 does not return the read data but returns only an abnormal response to the central processing unit bus interface circuit 1A in the central processing unit 11. . The central processing unit bus interface 1A that has received the abnormality response does not directly notify the microprocessor 19 of this, but notifies the standby main memory access circuit 1B that an abnormality has occurred in the main memory 12.

In the standby system main memory access circuit 1B, the address of the standby system main memory device 22 storing the same data is calculated based on the access address of the active system main memory device 12, and the central processing unit bus interface circuit is calculated. A read request is issued to the main storage device 22 of the operating system via 1A. The main memory 22 of the standby system, which has received the request via the intra-subsystem bus 15, the inter-subsystem connection devices 13 and 23, the inter-subsystem connection line 30, and the inter-subsystem bus 25 of the standby system, is of the normal operation system. Main memory 12
Similarly to the processing performed in step 1, data is extracted from the storage element circuit 26, a normality test is performed by the failure detection circuit 27, and then the read data is returned to the central processing unit 11 of the operating system together with a normal response.

The central processing unit bus interface circuit 1A of the operating system, which has received the normal data from the main memory 22 of the standby system, sends the data to the microprocessor 19 together with a normal response as the received data for the access to the main memory 12 of the operating system. return. As a result, the program running on the microprocessor 19 advances the processing in the same manner as in the normal case by using the alternative data without performing processing such as instruction word analysis.

At the same time, the standby main memory access circuit 1B instructs the microprocessor 19 to wait for the main memory 22 of the standby system.
The fact that a normal response has been made using the received data from is notified by the standby system main memory alternate interrupt request line 1C in the first subsystem 10.

In the program, after receiving the interrupt request and performing the processing up to the next checkpoint, the processing execution progress status is stored in the processing execution data storage units 18 and 28 as takeover data, and the first subsystem 10 and The switching of the second subsystem 20 is performed. In the second subsystem 20, which is in the operating state after switching, the subsequent processing is performed by referring to the first processing execution progress data storage unit 18 or 28.

(Effects of the Embodiment) According to the above embodiment, the first subsystem 10 and the second subsystem 10 are processed after the processing is performed up to the point where the division is good by using the alternative data in the main storage device 22 of the standby system. Since the subsystem 20 is switched, the processing can be resumed without performing the reprocessing until the failure occurs.

(Other Embodiment) In the above embodiment, the standby main memory access circuit 1B in the central processing unit 11 in the active system calculates the address of the alternative data in the main memory 22 of the standby system and the alternative data. However, the main memory 12 of the operating system requests the alternative data to the main memory 22 of the standby system, and the main memory 22 of the standby system calculates the address of the alternative data. Alternatively, the alternative data may be output.

The present invention can also be applied to a computer system of triple or more.

Further, the present invention can be applied to a system using a DMA controller or the like as main memory input / output means as long as the system involves access to the main memory device.

[0035]

As described above, when a failure occurs in the main memory of the operating system, an abnormal response is suppressed, and the main memory data of the standby system is used as a substitute for the data in which the failure occurs to return a normal response together with the substitute data. By performing a series of processing to notify that alternative data has been used and switching between the active system and the standby system at a good break, it is possible to resume processing without reprocessing up to the point of failure Becomes As a result, it is possible to shorten the operating state temporary interruption time, which is the switching time between the active system and the standby system, and improve the immediate processability of the system.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a redundant system according to the present invention.

FIG. 2 is a configuration diagram of a conventional redundant system.

FIG. 3 is an explanatory diagram showing an example of using alternative data in a conventional redundant system.

[Explanation of symbols]

 10 First Subsystem 20 Second Subsystem 11,21 Central Processing Unit 12,22 Main Storage Device 17,27 Storage Data Failure Detection Circuit 19,29 Microprocessor 1A, 2A Central Processing Unit Bus Interface Circuit 1B, 2B Standby Main memory access circuit 1C, 2C standby main memory alternate interrupt request line

Claims (2)

[Claims] 1. A plurality of data processing devices comprising: a main memory device having a read data abnormality detection unit; a main memory input / output unit for accessing the main memory device; and a data processing unit having a process execution unit. A redundant system in which any one of the data processing devices serves as an active system and another data processing device serves as a standby system, each of the data processing devices functions when it is an active system. When an abnormal state is detected by a section, an abnormal response suppression section that suppresses notifying the main memory input / output means of the abnormal response, and any one of the above-mentioned data of the standby system when shifting to this exception processing state An alternative data extracting unit that extracts alternative data of read data relating to an abnormality from the main memory of the processing device and returns a normal response to the main memory input / output means together with the alternative data. A redundant system comprising: an exception processing notification unit that notifies the processing execution unit that a normal response has been returned together with the alternative data. 2. The redundant system according to claim 1, wherein the data processing means is a central processing unit, and the processing execution unit and the main memory input / output means are both microprocessors.