JP2002007220A - Multiple memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable system which connects 3 or more memories to a memory controller and decides by majority by multiplying memory controllers and allowing the memory controllers to mutually confirm their operations, and to shorten a data copy time after memory exchange by using multiplied memory control parts. SOLUTION: Operation modes can be set to memory interface parts 313 to 316, and 323 to 326 of a memory controller; when a memory controller of a common-use system 310 reads a memory, a memory controller of a standby system 320 fetches data in the data output timing of the memory and a majority decision circuit checks them; and an SVP 302 monitors whether or not the results of data checks of the common-use and standby systems agree each other. Further, an operation mode where data of memories 1, 2, and 3 which are fetched by the standby system are written to a memory 0 is provided to shorten the data copy time, after the replacement of the memory 0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed memory control device for storing the same data in three or more memories and maintaining the reliability by taking a majority decision of the read data. And the execution of a memory copy at the time of recovery from a memory failure.

[0002]

2. Description of the Related Art Generally, a memory system in which a memory is duplicated to protect data in a computer is employed.

FIG. 1 shows a configuration diagram of a conventional memory duplication system.

A system bus 101 is connected to a processor 100, a regular memory controller 110, and a standby memory controller 120.

The memory control device 110 includes a memory device 11
1 are connected to the memory control device 120, respectively.

The processor 100, the memory controller 110, and the memory controller 120 are instructed to switch between a normal system and a standby system, and to copy memory contents after replacing a failed memory device. The service processor 102 is connected.

At the time of writing to the memory, the memory controller 110
And the memory controller 120 receive the request and write the same data to both memory devices 111 and 121 to maintain consistency.

At the time of memory reading, only the service side memory control device 110 accepts a request and the memory device 111
, And outputs the data to the system bus 101.

If an error occurs in the data read from the service side, the service processor 102 detects the failure and switches the data transfer subject from the service type memory control device 110 to the standby type memory control device 120. After the switching is completed, the service processor 102 instructs the processor 100 to perform the memory access again, so that the operation of the system can be continued.

In addition, while the operation of the system is continued, the faulty working memory is restored, and the service processor 102 transfers the standby memory device 1 to the processor 100.
The system is restored by giving an instruction to copy the data stored in the storage device 21 to the restored working memory device 111.

Further, a system has been devised in which three or more memory devices are connected to one memory control device to store the same data, and a majority decision is made at the time of reading data to maintain data reliability.

FIG. 2 shows a system in which memory devices are multiplexed.

The processor 200 and the memory controller 210 are connected to a system bus 201.

The memory control device 210 includes the memory device 22
0, 221 and 222 are connected.

A service is provided to the processor 200 and the memory control device 210 to instruct the switching of the memory device to be input to the majority circuit or to copy the memory contents after replacing the failed memory device. The processor 202 is connected.

At the time of writing to the memory, the memory controller 210
Write the same data to the memory devices 220, 221, 222i to maintain consistency.

The memory devices 220 and 22 are also used for reading the memory.
Read data from the memory controller 122 and the memory controller 210
To the majority circuit.

The data obtained as a result of the majority decision is output to the system bus 201.

If the data read from the memory device 220 is different from the data from the memory devices 221 and 222, it recognizes that a failure has occurred in the memory device 220 and reports it to the service processor 202. The service processor 202 instructs the memory control device 210 to disconnect the memory device 220 from the input of the majority circuit.

Since the correct data obtained from the majority circuit is output to the system bus 201, the system can continue to operate.

The failed memory device 220 is restored while the operation of the system is continued, and the service processor 202 instructs the processor 200 to read / write the restored memory area.

At the time of memory reading, the read data of the memory device 220 is not input to the majority circuit, and at the time of memory writing, the same data as that of the memory devices 221 and 222 is written so that the data is copied and the system is restored.

[0023]

The duplicated memory control device is defined as a normal system and a standby system, and means for performing a write operation for both the normal system and the standby system during memory write and performing a read operation from the normal system during memory read. Generally, in this case, the read processing of the standby system is performed after a failure occurs in the service system and the system is switched.

Therefore, there is a problem that the reliability of the read circuit of the standby system cannot be ensured until a failure occurs in the service system.

In a system in which three or more memory devices are connected to one memory control device to store the same data, a majority decision is made at the time of reading data, and the memory control devices are duplicated in a system for maintaining the reliability of data. Since three or more memory devices are connected, there is a problem that the connection amount of the memory devices increases.

When a failure occurs in the memory device, the memory system is switched to the standby memory control device to restore the failed working memory, and the data stored in the standby memory is restored according to an instruction from the CPU. Was to be copied to a regular memory.

In this case, it is necessary to copy data by performing a read operation and a write operation on the entire area of the replaced memory device. During this copy time, the processing performance of the system is squeezed and the copy is terminated. Until that time, the system is operated with the memory system multiplicity reduced.

Therefore, it was necessary to shorten the copying time.

[0029]

SUMMARY OF THE INVENTION The present invention provides a memory control device having three or more memory interfaces, two or more memory control devices for performing a majority decision of data read from each memory in a normal system and a standby system. A multiplexed memory system is characterized in that a circuit for setting an operation mode is provided in a memory interface portion of the device, and the following four operation modes can be set.

Memory control mode The control lines of the memory are driven to read and write data.

Data receive mode The operation of the control line of the memory is monitored, and an operation of taking in data in accordance with the read / write timing of the memory is performed.

Pause mode The control line of the memory is not driven and the operation of taking in the read data is not performed. Copy back mode The control line of the memory is driven to write data.

Used in combination with the data receive mode described above.

[0034]

FIG. 3 shows an embodiment of the present invention.
3, the instruction processor 3 is connected to the system bus 301.
00 and the memory control devices 310 and 320 are connected.

The memory controller 310 is a normal system, and the memory controller 320 is a standby system.

The instruction processor 300 and the memory controllers 310 and 320 include a service processor 302.
Is connected.

The memory controller 310 includes a system bus interface 311 and a memory device interface 3
13, 314, 315, 316 and a majority decision circuit 312.

Similarly, the memory controller 320 has a system bus interface 321, memory device interfaces 323, 324, 325, 326 and a majority circuit 32.
2 is comprised.

The memory control device 310 includes the memory device 33
0, 331, 332, and 333 are connected.

The memory control device 320 is similarly connected to the memory devices 330, 331, 332, and 333.

The memory device interface unit sets four operation modes from the service processor 302: a memory control mode, a data receive mode, a sleep mode, and a copy back mode.

In the memory control mode, control lines of the memory are driven to read / write data in the memory device.

In the data receive mode, the drive of the control line of the memory device is monitored, and data is fetched in accordance with the data output timing of the memory.

In the sleep mode, the data control line is not driven and the read data of the memory device is not taken in. The output data of the memory interface unit set in the sleep mode is excluded from the input data of the majority circuit and is not checked.

The copy back mode is the same in operation as the memory control mode, but only performs a write operation on the memory. The data to be written uses data output from the majority circuit.

The operation mode of the memory device interface of the memory controller is also set by the service processor 302.

Next, the structure of the memory control device will be described. FIG. 4 is a diagram showing the structure of the memory control device.

The memory controller 410 has a system bus interface 430, a majority circuit 440, and memory interfaces 450, 460, 470, and 480.
It is composed of

Memory interface controllers 450 and 46
Since 0, 470, and 480 have the same structure, only the memory interface control unit 450 will be described.

The memory interface controller 450 includes a read data register 453 for storing read data from the memory device 420, a write data register 452 for storing write data to the memory, and a memory stage controller A.
456, an operation mode register 451 for setting the operations of the memory stage control unit B457 and the memory interface control unit 450.

The operation mode register 451 can set a memory control mode, a data receive mode, a pause mode, and a copy back mode.

The value of the operation mode register is connected to the memory stage A controller 456 and the memory stage B controller 457.

The memory stage B controller 457 controls the memory control mode and the copy back mode among the operation modes. In this case, since the control line of the memory device 420 needs to be driven, a memory control output register 455 is provided.

The memory stage A control section controls the data receive mode among the operation modes.

In this case, since it is necessary to monitor the control signal of the memory device 420, the memory control input register 454
It has.

As input data to the write data register 452, data from the system bus interface unit 430 and data from the majority circuit 440 can be selected. The selection is made by the value of the operation mode register 451. When the value of the operation mode register is the copy-back mode, data of the majority circuit 440 is selected, and otherwise, data of the system bus interface unit 430 is selected.

When the value of the operation mode register 451 is in the sleep mode, the memory stage A control unit 456 and the memory stage control unit B 457 do not operate, and the memory device 42
Do not drive the memory control lines and data lines to 0.

The majority circuit 440 receives data from the memory interface units 450, 460, 470, and 480 and takes a majority decision. The data obtained as a result of the majority decision is sent to the system bus control unit 430.

The operation mode register data from the memory interface units 450, 460, 470, and 480 are connected to the majority circuit 440, and the data from the memory interface unit is used as an input to the majority circuit according to the operation mode value. Or choose.

When the operation mode of the memory interface control unit is the sleep mode or the copy back mode, data from the memory interface unit is not used as an input to the majority circuit.

The system bus interface section 430 includes a control register 431 for receiving a memory request from the system bus 400, an address register 432 for receiving a memory address, a write data register 433 for receiving memory write data, and a read data from the memory for the system bus 400. And a system bus interface control unit 435 for controlling an interface with the system bus 400.

The read data register 433 takes in the data obtained from the majority circuit 440. Whether the data is output to the system bus 400 is determined by the operation mode register 451 input to the system bus interface control unit.
And the setting values of the operation mode registers of the memory interface units 460, 470, and 480.

When the data receive mode is set in the operation mode register of any one of the memory interface units, the system bus interface control unit 435 controls so as not to output data to the system bus 400.

Next, the operation of the memory device control unit for each mode will be described. FIG. 5 shows a case where all of the memory interface control units 530, 531, 532, and 533 are set to the memory control mode.

When a memory read request is issued from the system bus 501 to the memory control device 500, a request code and a memory address are stored in the system bus interface unit 510.

Memory interface units 530, 531,
532 and 533 drive control lines of the respectively connected memory devices to read data.

The read data is input to the majority circuit 520. At this time, the memory interface units 530, 531,
Since 532 and 533 are set to the memory control mode, all the read data are used as inputs to the majority circuit.

The data obtained by the majority circuit is sent to the system bus interface unit 510.

Memory interface units 530, 531,
Since 532 and 533 are set to the memory control mode, the read data is output to the system bus 501.

FIG. 6 shows a case where all of the memory interface controllers 630, 631, 632, and 633 of the memory controller 600 are set to the data receive mode, and all the memory interface units of the memory controller 650 are set to the memory control mode. Is shown.

When a memory read request is issued to the system bus 601, the memory controllers 600 and 650 receive the request, respectively, and
At 660, the request code and the memory address are stored. The memory control device 650 drives a memory control line to read data.

The memory interface unit 633 monitors the memory control line driven by the memory interface unit 683, and takes in data in accordance with the data output timing of the memory device 640.

The read data is input to majority circuit 620. At this time, the memory interface units 630, 631,
Since 632 and 633 are set to the data receive mode, all the read data are used as inputs to the majority circuit.

The data obtained by the majority circuit is sent to the system bus interface unit 610.

The memory interface units 630, 631,
Since 632 and 633 are set to the memory control mode, read data is not output to the system bus 601.

FIG. 7 shows a case where the memory interface control units 730, 731 and 732 of the memory control device 700 are set to the memory control mode and the memory interface control unit 733 is set to the sleep mode.

When a memory read request is issued to the system bus 701, the memory control device 700 stores a request code and a memory address in the system bus interface unit 710.

The memory interface units 730, 731,
732 drives a control line of the memory device to read data from the memory. Since the memory interface unit 733 is set to the sleep mode, neither the control line nor the data line is driven for the memory device 740. The data read from the memory is sent to the majority circuit 720. Since the memory interface control unit 733 is set to the sleep mode, it is not used as input data for majority in the majority circuit 720.

Memory interface control units 730 and 73
1,732 read data are used as majority decision input data.

FIG. 8 shows that the memory interface unit 830 of the memory control device 800 is set to the copy back mode,
The memory interface units 831, 832, and 833 are set to the data receive mode, the memory interface unit 860 of the memory controller 850 is set to the sleep mode, and the memory interface units 861, 862, and 863 are set to the memory control mode. Is shown.

When a memory read request is issued to the system bus 801, the memory controllers 800 and 850 store the request code and the memory address in the system bus interface.

The memory control device 850 reads data from the memory and outputs it to the system bus 801 by the operation described with reference to FIG.

Since the memory interface units 831, 833, and 833 of the memory control unit 800 are set to the data receive mode, they monitor the control lines of the memory device and read data.

The read data is sent to the majority decision circuit 820. The data obtained as a result of the majority decision is sent to the system bus interface unit 810, but does not output data to the system bus 801 because the memory interface units 831, 833 and 833 are set to the data receive mode.

Since the memory interface unit 830 is set to the copy back mode, the data obtained as a result of the majority decision from the system bus interface unit 810 is written to the memory device 840 by driving the memory control line.

FIG. 8 shows operation timings in the data receive mode and the copy back mode. In stage 02, the memory interface units 831, 832, and 833 store read data from the memory device and send the data to the majority circuit 820. The result of the majority decision in stage 03 is majority circuit 8
20. In stage 04, memory write data is stored in the memory interface unit 830, and in stage 05, data is written in the memory device 840.

Next, the operation of the configuration shown in FIG. 3 will be described.
FIG. 9 shows a case where no failure has occurred in the memory control device and the memory device.

The regular memory controller 910 sets the memory interface units 913, 914, 915, and 916 to the memory control mode.

The memory controller 920 of the standby system sets the memory interface units 923, 924, 925, and 926 to the data receive mode.

When a memory read request is issued from the instruction processor 900, both the memory control devices 910 and 920 store the request code and the memory address in the system bus interface units 910 and 921, and start the read control for the memory device.

Since the memory interface of the ordinary memory controller 910 is set to the memory control mode, the memory controller 910 drives the memory control lines to the memory devices 930, 931, 923 and 933 to read the memory data.
The data taken into the memory interface unit is sent to a majority decision circuit 912 and majority decision is performed. The data obtained as a result of the majority decision is transferred to the system bus interface unit 911.
Is output to the system bus 901 via the.

If a mismatch occurs as a result of the majority decision, the number of the memory device that did not match the request identification number is reported to the service processor 902.

Since the memory interface of the memory controller 920 of the standby system is set to the data receive mode, the memory devices 930, 931, 933 and 933 are set.
Monitor the state of the memory control line, and fetch data in accordance with the data output timing of the memory.

The data fetched by the memory interface unit is sent to a majority decision circuit 922 and majority decision is performed.
The data obtained as a result of the majority decision is sent to the system bus interface 921,
Since 3, 924, 925, and 926 are set to the data receive mode, no data is output to the system bus 901.

However, if a mismatch occurs as a result of the majority decision as in the case of the normal-use memory control device 910, the number of the memory device that does not match the request identification number is reported to the service processor 902.

When the memory processor 910 and 920 report a state in which the memory data mismatch has occurred with the same request identification number from the memory control units 910 and 920,
The numbers of the memory devices are compared, and if the numbers of the memory devices match, the service processor 902 requests replacement of the memory device.

Until the replacement of the memory device is completed, the operation mode of the corresponding memory interface unit is set to the sleep mode, so that the operation of the system is continued without inputting the data of the faulty memory device to the majority circuit. .

When a failure report is received from only one of the memory controllers 910 and 920 to the service processor 902, it is determined that a failure has occurred in the memory controller.

If the memory controller determined to have failed is the service system 910, the operation mode of the memory interface unit of the standby system 920 is set to the memory control mode, and the memory of the service system memory controller 910 is set. After setting the operation mode of the interface unit to the sleep mode, the memory controller 910 is requested to be replaced.

When the memory control device determined to have failed is the standby system 920, the operation mode of the memory interface unit is set to the sleep mode, and then the replacement of the memory control device 920 is requested.

As described above, at the time of memory reading, regardless of the service system and the standby system, the data check mechanism by the majority circuit is operated, and the operation of the memory control devices can be mutually confirmed by comparing the check results, thereby realizing high reliability. can do.

Next, a case where a memory write request is issued from instruction processor 900 will be described.

Both the memory control devices 910 and 920 receive the memory write request, store the request code, the memory address and the memory write data in the system bus interface units 910 and 921, and start the write control for the memory device.

Since the memory interface of the ordinary memory controller 910 is set to the memory control mode, the memory control lines are driven for the memory devices 930, 931, 932, and 933 to write data to the memory.

Since the memory interface of the memory controller 920 of the standby system is set to the data receive mode, the memory devices 930, 931, 933 and 933 are set.
Monitor the state of the memory control line, and fetch data in accordance with the data write timing of the memory.

The memory interface units 923, 924,
The data taken into 925 and 926 is a majority decision circuit 92
It is sent to 2 and checked.

[0107] When the data does not match as a result of the check, a memory device number that does not match the request type is reported to the service processor 902.

In this case, after determining that a failure has occurred in the service memory controller and instructing the instruction processor 900 to stop the memory request and disabling the system bus, the memory interface of the service memory controller 910 is disabled. The operation mode of the memory controller is set to the sleep mode, the operation mode of the memory interface of the memory controller 920 of the standby system is set to the memory control mode, and after switching between the normal system and the standby system, the replacement request of the memory controller 910 is issued. I do.

As described above, even during memory writing, the operation of the memory control device can be confirmed by checking the memory write data of the normal system by the majority circuit of the standby system, and high reliability can be realized.

Next, the copying operation of the memory data after replacing the memory device will be described. FIG. 10 shows a state where the memory device 1030 is replaced.

The operation mode of the memory interface unit 1013 of the ordinary memory control unit 1010 is set to the copy back mode while the operation mode of the memory interface unit 1013 of the standby memory control unit 1020 is set to the sleep mode.

The service processor 1002 instructs the instruction processor 1000 to read the memory exchange area.
The instruction processor 1000 issues a read request to a mounting area of the memory device 1030.

Since the memory interface units 1024, 1024, and 1026 of the standby memory controller 1020 are set to the data receive mode, the state of the memory control lines of the memory devices 1031, 1032, and 1033 is monitored, and the data of the memory is monitored. Data is taken in according to the output timing.

The data fetched by the memory interface unit is sent to the majority decision circuit 1022 and majority decision is performed. The data obtained as a result of the majority decision is sent to the system bus interface unit 1021,
Is not output to

The data obtained by the majority decision circuit 1022 is sent to the memory interface unit 1023.

Since the operation mode of the memory interface unit 1023 is set to the copy-back mode, data is written by driving the memory control line to the memory device 1030.

When the issuance of the read request to the mounting area of the memory device 1030 is completed, the memory data copy operation ends.

When the copying is completed, the operation mode of the memory interface unit 1013 is switched from the sleep mode to the memory control mode, and the operation mode of the memory interface unit 1023 is switched from the copy back mode to the data receive mode.

As described above, since the data copy after the memory device replacement is completed only by the memory read request from the instruction processor 1000, the memory copy time can be reduced.

Also, by using data obtained from the majority circuit as data to be copied to the memory, a highly reliable memory copy can be performed.

[0121]

As described above, according to the present invention, even in a memory system in which the same data is stored in three or more memory devices, the memory device control unit can be multiplexed without increasing the number of memory devices. High reliability can be realized by always operating the multiplexed memory device control units and checking each other's operations.

Further, the data copy process to the replaced memory device is executed only by the read request using the multiplexed memory device control unit, so that the data copy time can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a conventional multiplexed memory system.

FIG. 2 is a diagram showing a configuration of a multiplexed memory system using a conventional majority method.

FIG. 3 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration of a memory control device in the overall configuration of the embodiment shown in FIG. 3;

FIG. 5 is a diagram illustrating an operation when a memory interface unit is set to a memory control mode in the memory control device illustrated in FIG. 4;

FIG. 6 is a diagram showing an operation when a memory interface unit is set to a data receive mode in the memory control device shown in FIG. 4;

FIG. 7 is a diagram showing an operation when a memory interface unit is set to a sleep mode and a memory control mode in the memory control device shown in FIG. 4;

FIG. 8 is a diagram showing an operation when a memory interface unit is set to a data receive mode and a copy back mode in the memory control device shown in FIG. 4;

FIG. 9 is a diagram showing an operation in a state where no failure occurs in the entire configuration of the embodiment shown in FIG. 3;

FIG. 10 is a diagram showing an operation of data copying after replacement of the memory device 1030 in the entire configuration of the embodiment shown in FIG. 3;

[Explanation of symbols]

100, 200, 300, 900, 1000 ... instruction processor (IP), 101, 201, 301, 400, 5
01,601,701,801,901,1001 ... system bus, 102,202,302,902,100
2. Service processor (SVP), 110, 120,
210: memory control unit, 111, 121, 220, 22
1,222... Memory, 310, 320, 430, 50
0,600,650,700,800,850,91
0,920,1010,1020 ... memory control device, 3
30,331,332,333,430,540,64
0,740,840,841,930,931,93
2,933,1030,1031,1032,1033
... Memory devices, 311, 321, 430, 510, 61
0,660,710,810,911,921,101
1,1021 ... system bus interface unit, 31
2,322,440,520,620,670,72
0, 820, 912, 922, 1011, 1022 ... majority circuit, 313, 314, 315, 316, 317,
318,323,324,325,326,450,4
60,470,480,530,531,532,53
3,630,631,632,633,683,73
0,731,732,733,830,831,83
2,833,860,861,862,863,91
3,914,915,916,923,924,92
5,926,1013,1014,1015,101
6,318,1023,1024,1025,1026
... Memory interface unit, 431 ... Control register, 4
32 ... address register, 433 ... write data register (system bus interface), 434 ... read data register (system bus interface), 4
35 ... memory interface unit, 451 ... operation mode register, 452 ... write data register (memory interface unit), 453 ... read data register (memory interface unit), 454 ... memory control input register, 455 ... memory control output register, 456 ... Memory stage A controller, 457... Memory stage B controller.

Claims (4)

[Claims] 1. A memory control device comprising three or more memory interfaces, and two or more memory control devices for performing a majority decision of data read from each memory in a normal system and a standby system, wherein an operation mode is provided in a memory interface portion of the memory control device. A multiplexing memory system comprising a circuit for setting the following four operation modes: Memory control mode The control lines of the memory are driven to read and write data. Data receive mode Monitors the drive of the control line of the memory and performs the operation of taking in data in accordance with the read / write timing of the memory. Idle mode Does not drive the control lines of the memory and does not take in the read data. Copyback mode Drives the control lines of the memory and writes data. Used in combination with the data receive mode described above. 2. The reliability of the memory control device is maintained by always operating the normal-use and standby-system majority decision circuits in the memory control devices connected on the same system bus and mutually confirming operation. And a memory multiplexing system. 3. A memory multiplexing system, wherein the memory control device connected to the same system bus captures and monitors write data to a normal system memory in a standby system to maintain reliability. 4. A multiplexed memory system in which memory data copy after memory replacement can be executed only by a memory read instruction by combining memory control modes of a memory interface control portion of the memory control device.