JPH0523258U - Memory circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if an error is detected in the data storage memory of the computer, the memory circuit is switched to the standby system and the processing of the computer can be continued. [Structure] Main and slave data storage memories 3a and 3b and parity storage memories 6a and 6b are arranged. Parity checkers 12a and 12b for arranging the correctness of the information output from the data storage memories 3a and 3b and the parity storage memories 6a and 6b at the time of a read request are arranged. CP
When the identification result of the system connected to U1 is normal, the connection state is kept as it is, and when abnormal, the switching control circuit 15 and the selector 14 for switching the connection to another system are arranged. [Effect] Even when one of the data storage memories 3a and 3b has an abnormality, the connection to the CPU 1 can be alternately made by the switching control circuit 15, so that the processing can be continued without interruption.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory circuit that strongly requires the reliability of stored data and that requires continuity of processing even when a temporary error or a permanent failure occurs during memory storage.

[0002]

[Prior Art]

 FIG. 3 is a diagram showing a method of detecting a logic inversion error in a memory circuit according to a conventional parity check method. In the figure, 1 is a CPU for executing an operation, 2 is an information output bus for outputting data information such as an operation result, 3a is a data storage memory for storing the data information of the information output bus 2, and 4 is an information output bus 2. Parity generator 5 that generates parity data based on the data information is parity information output from the parity generator 4. Whether the parity generator 4 is odd or even parity is set in advance by the system. 6a is a parity storage memory for storing the parity information 5, 7 is an address bus for determining where to store the information in the data storage memory 3a and the parity storage memory 6a, 8 is a write signal from the CPU1, and 9 is the CPU1. Read signal 10a is an information input bus for inputting data information to the CPU 1 from the data storage memory 3a when the read signal 9 is generated, and 11a is parity information output from the parity storage memory 6a when the read signal 9 is generated. , 12a is a parity checker for identifying whether the data information is normal or abnormal based on the information input bus 10a and the parity information 11a, and 13a is an error signal for notifying the CPU 1 of the abnormality according to the result of the parity checker 12a.

Next, the operation will be described. FIG. 4 shows the timing of writing data information from the CPU 1 to the data storage memory 3a. FIG. 5 shows the timing of reading information from the data storage memory 3a.

First, a data information writing method will be described with reference to FIG. When the CPU 1 executes the calculation, the CPU 1 outputs the corresponding address information to the address bus 7 at the timing of t1 in order to store the calculation result in the data storage memory 3a. One write cycle is from t1 to t4. At t2, the write signal 8 is output, and at the same time, the data information is output to the information output bus 2. This information is also input to the parity generator 4 to generate the parity information 5. The data information of the information output bus 2 and the parity information 5 are stored in the data storage memory 3a and the parity storage memory 6a at the trailing end t3 of the write signal 8, respectively.

Next, a data information reading method will be described with reference to FIG. The CPU 1 reads data information from the data storage memory 3a prior to executing the operation. At t5, the corresponding address of the data storage memory 3a is output to the address bus 7. One read cycle is from t5 to t8. When the read signal 9 is output at t6, the corresponding data information is output from the data storage memory 3a and the parity storage memory 6a designated by the address bus 7 as the information input bus 10a and the parity information 11a. These two pieces of information are input to the parity checker 12a, and normality or abnormality is discriminated. This identification is performed at t7. When the error signal 13a is at H level, that is, when the error signal 13a is normal, the processing of the CPU 1 is continued. If the error signal 13a is L level, that is, if there is an abnormality, the abnormality information is transferred to the CPU 1 and the processing of the CPU 1 is stopped.

[0006]

[Problems to be solved by the device]

 The error detection method using the parity check method as described above has a problem in that even if one error occurs during reading of data information, the processing of the CPU 1 cannot be continued and must be stopped.

The present invention has been made in order to solve such a problem, and makes it possible to continue processing even when an error occurs in the data storage memory 3a and a parity abnormality is identified during data reading. The purpose is to

[0008]

[Means for Solving the Problems]

 In the storage circuit according to the present invention, two data storage memories for storing data information from the CPU 1 are arranged as a master system and a slave system, and when the write request by the write signal 8 from the CPU 1 requests the same data information at the same time. And the slave data storage memory, and at the same time, this data information is input to the parity generator 4 to generate the parity information 5, which is written in the master and slave parity storage memories. When a read request is issued by the read signal 9, the corresponding address data information and parity information are simultaneously read from the main system and slave system data storage memories and parity storage memories respectively, and each parity checker of both systems checks each error. , As a result, the system currently connected to CPU1 by the selector is abnormal Where indicated, the output switching request from the switching control circuit to the selector, is obtained by such a system to be transferred from or slave to slave and the CPU1 to the main system can be operated while switching alternately from the main system.

[0009]

[Action]

 As described above, two data storage memories for storing data information are configured as a master system and a slave system, and when the data information is read from the CPU 1, abnormal states of the master system and the slave system are identified by a parity checker. When an abnormality occurs in the system connected to the CPU1, the processing is interrupted by switching the data information output from the data storage memory of the opposite system to the CPU1 for operation thereafter. It works so that you can continue without.

[0010]

【Example】

 Example 1. FIG. 1 shows an embodiment of the present invention, and 1 to 13 are exactly the same as the above-mentioned conventional circuit. The data storage memory 3a functions as a main system.

Reference numeral 3b is a subordinate data storage memory, 6b is a subordinate parity storage memory, 10b is an information input bus for inputting data information from the data storage memory 3b to the CPU 1, and 12b is a subordinate parity checker. Reference numeral 13b is a slave error signal, 14 is a selector for selecting the information input bus 10a or 10b, 10c is an information input bus for transferring the information input bus 10a or 10b selected by the selector 14 to the CPU 1, and 15 is an error signal 13a. And a switching control circuit composed of a flip-flop for discriminating between 13b and 13b, and 16 a switching signal of the selector.

Next, the operation will be described. The timing of writing the data information from the CPU 1 to the data storage memories 3a and 3b is basically the same as in FIG. 4 of the conventional example. The difference is that the information output bus 2 is connected to the data storage memories 3a and 3b, and the same data information can be written simultaneously by the write signal 8. FIG. 2 shows the data information read timing of this consideration. This will be described below with reference to FIGS. 1 and 2.

In the figure, the selector 14 initially selects the information input bus 10a by the switching control circuit 15. The switching signal 16 of the flip-flop output of the switching control circuit 15 is initialized to the L level.

The CPU 1 reads the data information from the data storage memories 3a and 3b prior to executing the calculation. At t5, the corresponding addresses of the data storage memories 3a and 3b are output to the address bus 7. One read cycle is from t5 to t8, and this is repeated. When the read signal 9 is output as L active at t6, the corresponding data information is read from the data storage memories 3a and 3b and the parity storage memories 6a and 6b designated by the address bus 7 and the information input buses 10a and 10b and the parity information 11a. 11b is output. The information input bus 10a and the parity information 11a and the information input bus 10b and the parity information 11b are input to the parity checkers 12a and 12b, respectively, and the normality or the abnormality is discriminated. This identification is executed in the time width of each read signal 9 from t6 to t7 immediately after. When the error signal 13a from t5 to t9 is H level, that is, when it is normal, the data information of the information input bus 10a is output to the information input bus 10c via the selector 14. When the error signal 13a from t9 to t10 is L level, that is, when the data information of the information input bus 10a is abnormal, the switching signal 16 which is the flip-flop output of the switching control circuit 15 changes to H level by the error signal 13a, The selector 14 is switched. After that, the information input bus 10b is input to the CPU 1 as the information input bus 10c. In the figure, this state is shown from t9 to t11. In the cycle of the read signal 9 from t11 to t12, an error occurs in the information input bus 10b, the switching signal 16 changes to L level by the error signal 13b, and the information input bus 10a becomes the information input bus 10c. It will be input to CPU 1. In this way, the data check memories 3a and 3b are checked by the parity checkers 12a and 12b for errors in the master system and the slave system, respectively, which are monitored by the switching control circuit 15 and the selector 14 is controlled to control the master system. Even if an abnormality occurs in some of the addresses of the data storage memories 3a and 3b, the processing can be continued while switching to the other system in order and avoiding the abnormality.

In the above description, a method of using the present invention in a memory circuit that requires high reliability has been described. However, it is applied to a data register of an input / output circuit that requires similar reliability. Good.

[0016]

[Effect of the device]

 Since the present invention is configured as described above, even if an abnormality occurs in the data storage memories 3a and 3b, the processing of the CPU 1 can be continued without interruption.

[Brief description of drawings]

FIG. 1 is a memory circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of a memory circuit showing an embodiment of the present invention.

FIG. 3 is a diagram showing a conventional memory circuit.

FIG. 4 is a diagram showing an operation timing when writing data in a conventional memory circuit.

FIG. 5 is a diagram showing an operation timing when reading data from a conventional memory circuit.

[Explanation of symbols]

 1 CPU 3a Data storage memory 3b Data storage memory 4 Parity generator 6a Parity storage memory 6b Parity storage memory 7 Address bus 8 Write signal 9 Read signal 12a Parity checker 12b Parity checker 14 Selector 15 Switching control circuit 16 Switching signal

Claims (1)

[Scope of utility model registration request] 1. A CPU for executing an operation, two data storage memories for a main system and a sub system for simultaneously recording data information output from the CPU according to a write signal from the CPU, C
A parity generator that generates parity information based on data information from the PU, a master and slave two parity storage memories that store parity information output from the parity generator, and a master and a slave according to a read signal from the CPU. Data parity and parity information output from the data storage memory and the parity storage memory of the main system and the secondary system for checking the correctness of the data information.
Selects whether to connect to the PU, the parity check results of the main and secondary parity checkers are identified, and when an error occurs in the master, the selector is switched to the slave and an error occurs in the slave. At the time, it is composed of a switching control circuit for switching the selector to the main system, and when a read signal is generated from the CPU, the data information of the main system and the slave system data storage memory and the parity information of the parity storage memory are read at the same time, and both systems are read. Both are checked by the parity checker. If the system currently connected to the CPU is normal, the state of the selector is left as it is. When an error is detected, the error signal output from the parity checker of the currently connected system is switched and controlled. A memory circuit characterized by switching the selector to another system by distinguishing it by the circuit and operating the main system and the sub system alternately.