KR100538486B1 - Error detecting circuit for storing data in system memory - Google Patents

Abstract

The present invention relates to a defect detection circuit of a system memory, comprising: a write buffer for receiving and storing data and receiving a write control signal and storing the data in first and second memories; Physically connected in parallel, the same physical address can be simultaneously accessed by the same read / write control signal so that data can be simultaneously read or written, and the first and second memories receive and store data from the write buffer. ; When the microprocessor reads data from the first and second memories, it compares two data of the same physical address of the first and second memories, and outputs a mismatch signal when the two data do not match. A comparator for outputting a coincidence signal when? A read buffer for storing data output from any one of the first and second memories when the match signal is output from the comparator, and outputting the stored data by an enable signal output from the microprocessor; It is composed of a microprocessor that controls each unit and outputs an enable signal to the read buffer when a match signal is input from the comparator, so that normal data can be read from another redundant memory when an error is detected. Can be guaranteed.

Description

Error detecting circuit for storing data in system memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection circuit of a system memory. In particular, the present invention relates to a fault detection circuit of a system memory, and to detect a fault occurring in real time in real time so that a redundant memory can be used to detect a fault. The present invention relates to a defect detection circuit of a system memory capable of detecting a defect so as not to lead to an error.

In the field of railway signal control, embedded computer technology is used in fields requiring high reliability and safety, and representative examples are used for controlling electronic interlocking devices, automatic train control devices, and timed electronic crossings.

1 is a structure of a general memory that interfaces with a microprocessor in a system using a microprocessor.

The memory 2 is a device that receives and stores data from the microprocessor 1 or transmits data at the request of the microprocessor. The memory 2 includes an address bus, a data bus, and a control bus. To interface with the microprocessor (1).

2 shows a process of reading / writing data to a general memory.

In order to write 0xFFFF to 0x0000A2 from 0x0000A0 to 0x0000A4 in the memory map represented by 16 bits, 0x0000A4 signal is applied to the address bus from the microprocessor 1 in the structure of FIG. After the chip select signal and the read / write signal are set to write, if 0xFFFF is applied to the data bus, it is written to the memory 2.

In order to read data from the memory 2, 0x0000A2 is applied to the address bus and then the read signal is applied to the chip select signal and the read / write signal of the control bus. .

Such a conventional memory stores data in a plurality of areas in software in order to detect data corruption due to an electrical disturbance or timing mismatch in storing data or a hardware defect in the memory. The occurrence of defects was monitored by comparison or by using extra information such as parity.

This structure does not detect defects generated in a computer system using a microprocessor in real time, and places a large amount of load on the microprocessor for detection of software defects.

The present invention is to solve the above problems, it is an object of the present invention to provide a defect detection circuit of the system memory for detecting defects in real time at the time of manufacturing a commercial control board or control board using a microprocessor.

Another object of the present invention is to detect a defect occurring in the memory of the system in real time to prevent the malfunction of the system by using the memory in which there is undamaged data by corrupting the information of the memory does not lead to an error of the system data It is to provide a defect detection circuit of the system memory.

Another object of the present invention is to detect a defect caused by external noise or damage to a device when data is stored in the system memory in a control board using a microprocessor defect of the system memory to ensure the normal operation of the system memory It is to provide a detection circuit.

In order to achieve the above object, a system memory defect detection circuit according to the present invention comprises: a write buffer which receives data and stores data therein, and receives a write control signal and stores the data in first and second memories; Physically connected in parallel, the same physical address can be simultaneously accessed by the same read / write control signal so that data can be simultaneously read or written, and the first and second memories receive and store data from the write buffer. ; When the microprocessor reads data from the first and second memories, it compares two data of the same physical address of the first and second memories, and outputs a mismatch signal when the two data do not match. A comparator for outputting a coincidence signal when? A read buffer for storing data output from any one of the first and second memories when the match signal is output from the comparator, and outputting the stored data by an enable signal output from the microprocessor; And a microprocessor for controlling the respective units and outputting an enable signal to the read buffer when a match signal is input from the comparator.

Since the first and second memories are physically connected in parallel, the same physical address may be simultaneously accessed by the same read / write control signal, thereby simultaneously reading or writing data.

In addition, since data input to the comparator by read control signals from the first and second memories are hardware-synchronized and output from a memory having the same timing, the data is electrically connected to the data bus only when the data is matched. Will be loaded.

An embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a defect detection circuit of a system memory according to the present invention.

The defect detection circuit of the system memory according to the present invention includes: a write buffer 11 for receiving data and storing data therein, and receiving a write control signal and storing the data in the first and second memories 12 and 13; Physically connected in parallel, the same physical address can be simultaneously accessed by the same read / write control signal so that data can be simultaneously read or written, and the first and second input and store data from the write buffer 11. Two memories 12 and 13; When the microprocessor 10 reads data from the first and second memories 12 and 13, two data are compared by comparing two data of the same physical address of the first and second memories 12 and 13. A comparator 14 for outputting a mismatch signal when the data does not match and outputting a match signal when the two data match; When the coincidence signal is output from the comparator 14, the data stored in one of the first and second memories 12 and 13 is stored and the enable signal is output from the microprocessor 10. A read buffer 15 for outputting stored data; And a microprocessor 10 which controls the respective units and outputs an enable signal to the read buffer 15 when a match signal is input from the comparator 14.

In order to explain a process in which the memory defect detection circuit of the present invention configured as described above writes data into the first and second memories 12 and 13, the memory map will be described with reference to FIG. 4 and a timing chart. do.

The microprocessor 10 first specifies an address to store via the address bus 18 in order to store data in the first and second memories 12 and 13. For example, a "0x0000A4" signal is applied to the address bus 18 as shown in Fig. 5E to store data at the "0x0000A4" addresses of the first and second memories 12 and 13. .

When the "0x0000A4" signal is applied to the address bus 19, the "0x0000A4" addresses of the first and second memories 12 and 13 are designated as shown in the memory map of FIG.

After designating the addresses of the first and second memories 12 and 13 as " 0x0000A4 ", " buffer enable " to the write buffer 11 via the control bus 16 as shown in Fig. 5A. After outputting the signal as "1" to the write state, the microprocessor 10 applies the data "0xFFFF" to the data bus 17 to the write buffer 11 as shown in Fig. 5C. Save it.

After the data "0xFFFF" is stored in the write buffer 11, the chip select signal "0" is output to the first and second memories 12 and 13 as shown in FIG. With the second memories 12 and 13 enabled, the chip select signal " 0 " outputs " 0xFFFF " stored in the write buffer 11, as shown in Fig. 5D. The data " 0xFFFF " is output from (11), and " 0xFFFF " is stored in the first and second memories 12 and 13, respectively.

In the same manner, data is also stored in other addresses of the first and second memories 12 and 13, and the memory fault detection circuit according to the present invention is executed in the first and second memories 12 and 13 in such a state. The process of reading data will be described with reference to FIG. 4 and a timing chart of FIG.

The microprocessor 10 applies the " 0x0000A4 " signal to the address bus 18 as shown in Fig. 6F to address the first and second memories 12 and 13, and the control bus 16 By inputting the buffer enable signal to the read buffer 15 through the () to enable the read buffer 15 (see Fig. 6 (a)).

After designating the addresses of the first and second memories 12 and 13 as " 0x0000A4 ", the chip select signal is output as " 0 " By putting it in the enabled state, data transfer occurs between the comparator 14 and the memories 12 and 13. In other words, " 0xFFFF " stored at the addresses " 0x0000A4 " of the first and second memories 12 and 13 are output to the comparator 14 and compared (see Fig. 6C).

Since the first and second memories 12 and 13 are physically connected in parallel, the same physical address may be simultaneously accessed by the same read / write control signal, thereby simultaneously reading or writing data.

Therefore, since the " 0xFFFF " data input to the comparator 14 by read control signals from the first and second memories 12 and 13 are data synchronized in hardware and output from a memory having the same timing, When the data is matched with each other, the match signal ("1" signal, see Fig. 6 (e)) is output from the comparator 14 to the microprocessor 10 and the microprocessor 10 receives the match signal. Enables the read buffer 15 so that the " 0xFFFF " data output from the first and second memories 12 and 13 is loaded onto the data bus through the read buffer 15 (see Fig. 6 (d)). ).

If the data read and output at address "0x0000A4" of the first memory 12 and the data read and output at address "0x0000A4" of the second memory 13 are different from each other, the comparator 14 is shown in FIG. As shown in (e) of the figure, a defect detection signal ("0" signal) is output to the microprocessor 10.

Therefore, the microprocessor 10 is detected by notifying the microprocessor 10 of a defect in the data due to the deterioration of the stored data due to the electrical disturbance or the timing mismatch in the process of storing the data or the hardware defect of the memory. ) Can read data from other redundant memories and prevent data from corrupted memory leading to system failure.

As described above, according to the present invention, a write buffer, a comparator, two memories, and a read buffer are used to detect hardware defects due to external noise or data errors due to physical damage to the memory, thereby providing another redundancy in error detection. The normal operation of the system can be guaranteed by reading the normal data from the memory.

1 is a structure of a general memory for interfacing with a microprocessor in a system using a microprocessor,

2 is an explanatory diagram showing a process of reading / writing data into a general memory;

3 is a block diagram showing a configuration of a defect suppression circuit of a system memory according to the present invention according to the present invention;

4 is an explanatory diagram showing a process of reading / writing data into a memory in a defect detection circuit of a system memory according to the present invention;

5 is a timing diagram showing a process of writing data into a memory by a memory defect detection circuit according to the present invention;

6 is a timing diagram showing a process in which a memory defect detection circuit of the present invention reads normal data from a memory;

7 is a timing diagram illustrating a process in which a memory defect detection circuit according to the present invention detects an error while reading data from a memory and outputs an error detection signal.

<Description of Symbols for Main Parts of Drawings>

11: Write buffer 12: First memory 13: Second memory

14: Comparative 15: Read buffer 16: Control bus

17: Data bus 18: Address bus

Claims (3)

A write buffer 11 for receiving and storing data and receiving a write control signal and storing the data in the first and second memories 12 and 13; Physically connected in parallel, the same physical address can be simultaneously accessed by the same read / write control signal so that data can be simultaneously read or written, and the first and second input and store data from the write buffer 11. 2 memories 12 and 13; When the microprocessor 10 reads data from the first and second memories 12 and 13, two data are compared by comparing two data of the same physical address of the first and second memories 12 and 13. A comparator 14 outputting a mismatch signal when the data does not match and outputting a match signal when the two data match; When the coincidence signal is output from the comparator 14, the data stored in one of the first and second memories 12 and 13 is stored and the enable signal is output from the microprocessor 10. A read buffer 15 for outputting stored data; And a microprocessor (10) for controlling the respective parts and outputting an enable signal to the read buffer (15) when a match signal is input from the comparator (14). . delete delete