JPS6121546A - Error detecting system of common memory - Google Patents

Abstract

PURPOSE:To attain ease of failure retrieval even if the number of sets is increased by detecting the rising and falling of a memory request signal and obtaining a signal representing whether or not a predetermined time is satisfied to detect a fault at write. CONSTITUTION:A memory request signal is given to an input (a) and inputted to a rising differentiation detection section 9 and a falling differentation detection section 11. An output signal (b) of the detection section 9 becomes a start signal of a counter 10 and when it is inputted, an output (d) of the counter 10 goes to logical 1 for a write/read required minimum time Tmin. Further, the output (d) and an output (c) of the detection section 11 are inputted to an AND element 12, given to a latch circuit 13 as an output (e) and an output (f) of the circuit 13 becomes a fault device number code sample signal of a fault device number storage section 14. Further, this fault device number is displayed on a display device 15. Thus, a fault at the write is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to error detection of a common memory accessed by a plurality of devices via a common bus.

(Prior Art) Conventionally, a common memory that can be accessed by a plurality of devices via a common memory has generally been used in a configuration as shown in FIG. The common memory 1 is connected to the devices 6-1 to 6- via the common bus 2.
In order to access the common memory 1, each device sends a bus use request signal 4 to the bus control section 3, and the device that receives or accepts the bus use permission signal 5 can access the common memory 1.

The common bus 2 includes all signal lines necessary to access the common memory 1. (For example, near address, data, etc.) The devices 6-1 to 6-n are usually considered to be processors or DMA devices. is not limited to this, as long as it accesses the common memory. FIG. 3 shows an operation time chart when a certain device accesses the common memory 1. The memory request signal 3 in FIG. 3 is an activation signal for the common memory 1. When this signal rises, a control circuit (not shown) in the common memory 1 is activated, and while this signal is at logic 1, data is sent to the device. Writing or reading data from the device is performed, and the memory access end signal 4 from the common memory 1 is received as 0, thereby completing one memory cycle. Note that (1) and <2) in FIG. 3 are the bus use request signal and bus use permission signal, and indicate that a bus use request is made and bus use permission is granted before sending the memory request signal 3. ing.

The memory request signal 3 is also used as a valid signal for a necessary signal line to access the common memory 1 within the common bus 2, and when the memory request signal 3 becomes logic 0, that signal line also becomes invalid.

(Problem to be Solved by the Invention) In such a configuration, the time To when the memory request signal 3 is logic 1 is the time To when data is written or read from a memory element (not shown) in the common memory 1. Assuming that the minimum time is Tmjn, at least the following equation (1) must be satisfied in order to guarantee the data in the memory element.

To≧Tmjn ・・・・・・・・・(1) However, the fourth
As shown in the figure, a failure occurred in the device accessing common memory 1, and Tl<Trrlin (2) Memory request signal 3 was terminated at 11 hours according to the relationship shown in equation (2) below. Or, as shown in Figure 5,
A failure occurred in the bus control unit 3, the bus use permission signal 5 was interrupted, and the memory request signal 3 was terminated at T2 (Tmin......(3)) in 12 hours according to the relationship shown in equation (3) below. In either case, since the memory request signal 3 is smaller than Tm1n, there is no guarantee of the data written to the memory element at this time.

Furthermore, even in the case of reading, the memory cycle ends before the read data is guaranteed.

In such cases, as a means to check the validity of data, conventional methods include a parity check method that adds redundant bits to the data and checks it when reading out to detect errors, or ErrorCheck using a Hamming code system.
king and CorrecNon (hereinafter referred to as ECC
There is a Type 75 (abbreviated as ). However, in all of these methods, errors in data are detected at the time of reading, so failures during writing are not discovered until the address is read, making early detection of failures difficult.

Furthermore, due to the nature of the common memory in which multiple devices access the common memory 1, the device that wrote data to the same location on the memory is often different from the device that read it, and the time lapse also occurs. The problem is that it is difficult to search for a faulty device among multiple devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a common memory error detection method that detects an abnormal memory cycle that occurs when accessing a common memory and facilitates a search for a device that causes a failure.

(Another means to solve the problem) The main point of this invention is to provide a detection circuit on the common memory to detect when the memory access time is so short that the memory contents cannot be guaranteed, and to output this detection signal from the bus control unit. The present invention is provided with a faulty device number storage section for launching a bus use permission signal and a display device for displaying the contents of this storage section.

(Function) With the above configuration, the present invention detects the rise and fall of the memo IJ IJ quest signal to obtain a signal indicating whether or not a predetermined time has been met, and to eliminate the cause of data errors. It is possible to detect an abnormality in a memory cycle and to understand the access device at the time, thereby eliminating the above-mentioned problem.

(Embodiment) FIG. 1 is a block diagram showing an embodiment according to the present invention,
In the figure, the same numbers as those in FIG. 2 are the same.

In addition, an error detection section 7 and a bus control section 3 are stored in the common memory 1.
Error detection unit 7 outputs the common bus use device number code signal 8 which encodes the device number currently using the common bus 2, that is, 1 for device 6-1, 2 for device 6-2, 2 for device 6-n, and 2 for device 6-n. It is connected to the. When the number of common bus-using device number code signals 8 is m and the number of devices is n, there is a relationship as follows: 2m≧n (4).

FIG. 6 is a detailed block diagram of the error detection section 7.
A memory request signal is connected to the rising edge differential detection section 9 and the falling edge differential detection section 11 . The output of the rising differential detection section 9 is the start signal of the counter 10, and when this is input, the output d of the counter 10 between Tmln
becomes logic 1.

Furthermore, the output d is the output C of the falling edge differential detection section 11 and the AN
The signal is input to the D element 12 and becomes the output e, which is connected to the latch circuit 13, and the output f becomes the failed device number code sample signal of the failed device number storage section 14. Furthermore, the faulty device number is displayed on the display device 15.

FIG. 7 is a time chart showing the operation of the error detection section 7, and (a) to (g) in the diagram show timings with the same names as in FIG. Similar to Fig. 4, a failure occurred in the access source of input a, so that after T1 time (T1 (
Consider the case where the cycle is interrupted at Tm1n). The rising differential is output to the output and starts the counter 10. A logic 1 is output to the output d for a period Tm1n after the start signal is input. When the differential detection section 11 detects a falling edge while the output d is at logic 1, it is output to the output C and the AND element 12
The logical AND is performed. This output e is transferred to the latch circuit 13'
The latch circuit 13 holds the output f at logic 1 so as to enable the first error detection block which is the cause of the failure. Since the faulty device number storage unit 14 stores the device number that was accessing the common memory 1 when the output f was turned on, subsequent errors are ignored by the latch circuit 13 and are not stored, but the first error is rewritten. It is retained without being retained. Furthermore, the stored device number is displayed on the display device 15.

Note that FIG. 6 is just one embodiment of the present invention, and any device that can detect that the memory cycle when accessing the common memory has fallen below Tm1n, which is sufficient to guarantee data, may be used. It doesn't matter if it's something. Also,
In order to know the device number that has obtained the right to use the common bus when the above guarantee time is not met, the device 6-! ~6
-n individually connected bus use permission signals 5 may also be used.

The bus use permission signal 5 is a conventional signal line, and an encoder capable of encoding the bus use permission signal 5 to obtain a common bus use device number code signal is installed in the error detection section z shown in FIG. By providing this, the same effects as in the first embodiment can be achieved, and the number of signal lines between the error detection section 7 and the bus control section 3 can be reduced.

Furthermore, when an error is detected, the faulty device stored in the faulty device number storage unit 14 is notified of the detection of the error by an interrupt or the like, so that the device that is notified immediately recognizes the occurrence of the error and prevents the spread of the fault to other devices. It also has the effect of making it possible to take countermeasures such as stopping the operation in order to suppress the situation.

(Effects of the Invention) As explained above, the present invention provides a common memory with a circuit for detecting an abnormality in the memory cycle that later causes a data error and a storage circuit for storing the device number being accessed at this time. As a result, it is possible to detect failures during writing that could not be discovered using the conventional Yariti check method or ECC method.Furthermore, since the device from which the access is made can be known, it is easy to search for failures even when the number of devices increases. The effect is dog because it can be done.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram according to the present invention, Fig. 2 is a conventional system configuration diagram, Fig. 3 is a time chart diagram when the memory cycle normally ends in Fig. 2, and Figs. 4 and 5 are Fig. 2 is a time chart when a memory cycle terminates abnormally, Fig. 6 is a schematic block diagram of an error detection section according to the present invention, and Fig. 7 is a time chart of the error detection section shown in Fig. 6. . DESCRIPTION OF SYMBOLS 1... Common memory, 2... Common bus, 3... Bus control unit, 4... Bus use request signal, 5... Start signal, 7... Error detection unit, 8... Common bus usage device number code signal, 9... Start-up differential detection section,
1o...Counter, 11...Fall differential detection section, 1
2...AND element, 3...Latch circuit, 14...
- Faulty device number storage unit, 15... Display device patent applicant Oki Electric Industry Co., Ltd.
−−−−−−−−−−Fig. 6

Claims (1)

[Claims] In an error detection method for a common memory that is accessed by multiple devices via a common bus, it is detected that a memory request signal that instructs a request to write data to or read data from the common memory does not meet the guaranteed time. The device has a detecting means, a storage means for storing a device number that has obtained the right to use the common bus when the guaranteed time is not satisfied, and a display means, and the device includes a detecting means, a storage means for storing a device number that has obtained the right to use the common bus when the guaranteed time is not satisfied, and a display means. A common memory error detection method is characterized in that when it is detected that the common bus is not being used, the device that has obtained the right to use the common bus at that time can be recognized by display means.