JPS6310378A - Peripheral memory device - Google Patents

Abstract

PURPOSE:To prevent data that is not written correctly from being used imprudently by inverting and writing an error detection correction code when the fault occurs in a host device during a read action and inspecting that the error detection correction code is inverted and written at the time of reading. CONSTITUTION:If the fault occurs in the host device 10 during a read action, an inversion circuit 205 inverts the error detection correction code generated by an ECC generation circuit 204 and transmits it to a storage unit 211 when a signal line 253 is effective. Read errors are inspected without the inversion of the error detection correction code transmitted from the storage unit 211 in the first read inspection circuit 208, and with the inversion of the error detection correction code in the second read error inspection circuit 209. Thus, data that is not correctly written is prevented from being used imprudently due to the occurrence of the fault in the host device, and the place in which the fault occurs can be partitioned.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to failure processing in a peripheral storage device when a failure that makes program execution impossible occurs in a host device during a write operation.

(Prior art) Conventionally, when it is detected that a failure has occurred in the host device during a write operation, the Kawabe storage device in this building stores specific data, for example, all 0 data, in the remaining part of the field being written. , and then an error detection and correction code is added thereto, or the writing is immediately interrupted when a fault in the host device is detected.

(Problem to be solved by the invention) In this case, since a fault has occurred in the host device that makes it impossible to execute the program, it is necessary to re-enter the field that was not correctly populated, or Since it is impossible to output or store addresses, etc., the above-mentioned conventional peripheral storage devices have the following problems.

In the former case, even if the field to which the write was not performed correctly is subsequently read, no abnormality is reported, making it impossible to detect that the write was not performed correctly.

In the latter case, since reading errors are detected, it is possible to prevent incorrect data from being processed incorrectly, but it is not possible to distinguish between reading errors due to a failure in the host device during writing and reading errors due to failures in the recording medium, etc. There were drawbacks.

The purpose of the present invention is to prevent careless use of data that has not been written correctly due to a failure in a host device;
An object of the present invention is to provide a peripheral storage device that can isolate the location where a failure occurs.

(Means for Solving the Problems) In order to achieve all of the above objects, the peripheral storage device according to the present invention includes a failure detection means for detecting the occurrence of a failure in a host device, and a failure detection means that is added to data and written to a recording medium. error detection and correction code generation means for generating an error detection and correction code;
an inverting means for writing an error detection and correction code by inverting the output of the error detection and correction code generation means when a fault in the host device is detected by the fault detection means during data writing; A first reading error checking means for checking for reading errors using an error detection and correction code added to the data; and a second reading error checking means for checking for reading errors after inverting the error detection and correction code added to the data. and a reading error checking means.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing in block form one embodiment of a peripheral storage device according to the present invention.

The peripheral storage device 20 includes a failure detection circuit 2011, a higher-level device connection circuit 202, a data transfer control circuit 203, an l1Xoo generation circuit 204, an inversion circuit 205, a storage unit connection circuit 206, an instruction execution control circuit 207, and a first read error check circuit 3208. , a second read error check circuit 209, and a plurality of storage units 211...212.

In this embodiment, a positioning command is issued prior to a data write command, and the selection of a storage unit to which data is to be written, positioning to a cylinder, track selection, and record search are performed. Since this is not directly relevant, a detailed explanation will be omitted.

When the host device Ti 110 issues a V write command following the positioning command, the write command is transmitted to the command execution control circuit 207 through the signal line 251 and the host device connection circuit 202% signal line 265.

The command execution control circuit 207 issues a write command to the storage unit 211 selected by the preceding positioning command through the signal line 264, the storage unit connection circuit 206, and the signal line 271, and further issues the data transfer control circuit 203 through the signal line 261. instructs to perform write processing.

Write data sent from the host device 10 through the signal line 251 is sent to the host device connection circuit 202, signal line 254, data transfer control circuit 203, signal line 256, storage unit connection circuit 206, signal line 271, and then to the storage unit 21.
Written to 1. At this time, the write data transferred from the host device is sent from the data transfer control circuit 203 to the E00 generation circuit 204 through the signal line 257, and the BOO
A generation circuit 204 generates an error detection and correction code.

When all the data to be written is transferred from the host device 10, the error detection and correction code generated in the E00 generation circuit 204 is transferred to the signal line 258, the inversion circuit 205, the signal line 259, the storage unit connection circuit 206, and the signal line 271. The data is sent to the storage unit 211 through the host device 10, and is written following the write data sent from the host device 10.

If no fault in the host device 10 is detected during the write operation, the error detection and correction code is not inverted in the inversion circuit 205.

When a failure occurs in the host device 10 during a write operation, the host device 10 notifies the failure detection circuit 201 through the signal line 251, the host device connection circuit 202, and the signal line 252 that a failure has occurred in the host device. Furthermore, even when the occurrence of a fault is not notified from the host device 10, the fault detection port % 201 can detect a fault in the host device 1O from the operating status of the signal line 251 through the host device connection circuit 202 and the signal line 252. When the fault detection circuit 201 detects that a fault has occurred in the host device 10, it enables the signal line 253 and notifies the inverting circuit 205 of this fact. The inversion circuit 205 inverts the error detection and correction code generated by the EOO generation circuit 204 when the signal line 253 is valid, and transfers it to the storage unit 211 .

On the other hand, in the read V operation as well, the host device 1o issues a positioning command, followed by a read command, as in the case of the write command.

When the instruction execution control circuit w5207 receives a read instruction, the signal line 264. The storage unit selection circuit fN5206 issues a read 9 command to the storage unit 211 through the signal line 271, and further instructs the data transfer control circuit 203 to perform m@ processing through the signal line 261.

The data read from the storage unit 211 is transferred to the signal line 27.
11 storage unit selection circuit w1206, signal line 260. The data is transferred to the higher-level device IO through the data transfer control circuit 203, signal line 255, higher-level device connection circuit 202, and signal line 251.

Furthermore, the data and error detection and correction codes received from the storage unit 211 are passed through the entire signal line 260 to the first reading error checking circuit 208 and the second reading error checking circuit 209.
sent to. In the first reading error checking circuit 208, the error detection and correction code sent from the storage unit 211 is not completely inverted, and in the second reading error checking circuit 209, the error detection and correction code is completely inverted to detect reading errors. Perform inspection.

When the read operation is completed in step 211, the instruction execution control circuit 207 checks through signal lines 262 and 263 whether or not there is a read error.

If no reading error is detected in the first read error checking circuit 208, the instruction execution control circuit 207 indicates that the reading has been performed normally to the host device 10 through the signal line 265, the host device connection circuit 202, and the signal line 251. to notify you of this. If a reading error is detected in the first reading error checking circuit 208, the second reading error checking circuit 208
9, and if no read error is detected, the instruction execution control circuit 207 informs the host device 10 that the data was not written correctly because a failure occurred in the host device when writing the read data. Report.

When a read error is also detected in the second read error check circuit 209, the instruction execution control circuit 207 determines that if one of the above states does not occur even if error correction or read retry is attempted, the indulgence is not detected. Notify the higher-level device IO that it is possible.

(Effects of the Invention) As explained above, the present invention inverts the error detection and correction code when a failure occurs in the host device during a write operation and writes the error detection and correction code, and further inverts the error detection and correction code at the time of reading. By checking that the data has been written correctly, it is possible to prevent incorrectly written data from being used inadvertently without changing the data recording format, and also to prevent data that has been written incorrectly from being used accidentally. This has the effect of making it possible to easily distinguish it from a reading error.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing in block form one embodiment of a peripheral storage device according to the present invention. 10... Host device 20... Peripheral storage device 201
...Failure detection circuit 202...Upper device connection circuit 203...Data transfer control circuit 204...E00 generation circuit 205...Inversion circuit 206...Storage unit connection circuit 207...Instruction execution control circuit

Claims (1)

[Claims] a failure detection means for detecting the occurrence of a failure in the host device; an error detection and correction code generation means for generating an error detection and correction code that is added to the data and written on the recording medium;
an inverting means for writing an error detection and correction code by inverting the output of the error detection and correction code generation means when a fault in the host device is detected by the fault detection means during data writing; A first reading error checking means for checking for reading errors using an error detection and correction code added to the data; and a second reading error checking means for checking for reading errors after inverting the error detection and correction code added to the data. A peripheral storage device comprising: reading error checking means.