JPS6320643A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of read data by providing a second error detecting means, which detects whether error occurs or not when data is written in an read from the address from which read data is read, besides a read data error detecting means using an error detection code. CONSTITUTION:A first error detecting means 2 and a second error detecting means 3, are provided the first means 2 detects whether read data read from a designated address of a storage device 1 includes error or not in accordance with the error detection code, and the second means 3 detects whether error occurs when data is written in and read from the address from which read data is read. Besides error detection by the first conventional error detecting means 2, error detection is performed by the second error detecting means 3 as follows; check data different from read data is written in the same address as read data of the storage device and is immediately read out, and write data and read data are collated to check whether address error exists or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] One port, one path for error detection in a storage device, in addition to error detection means for read data using an error detection code.

By providing a second error detection means for detecting the presence or absence of an error that occurs when reading and writing data to an address after reading the read data.

We aimed to improve the reliability of read data.

[Industrial application field]

The present invention relates to an error detection circuit for a storage device.

When a computer system failure occurs, it is possible to detect the error near the failure point.
It is very important to take effective countermeasures, and high reliability is particularly desired for error detection in storage devices.

[Conventional technology]

The error detection circuit of a conventional storage device (see Figure 3) employs a parity check method or an error correcting fE code (FCC) method. The detection code generation unit 21 generates an error detection code (Balitinaenoch code or error correction code) corresponding to the write data, adds it to the write data, and writes it into the storage device 1.

Also, when reading data from the storage device 1.

The error detection section 22 detects the presence or absence of an error in the read data using an error detection code, and sends an error signal to the processing device 4 if an error is detected.

[Problem that the invention seeks to solve]

In the conventional example, there are problems in that errors cannot be detected unless the data is being read, and errors can only be detected when the error is a relatively small line.

For the former, for example, a cyclical diagnostic program (PADIA:
patrol diagnostic program
) to check all bits of storage 74
Some have established capitals, but it has been difficult to fully assess the reliability of the data.

(Means for Solving the Problems) The festival detection circuit according to the present invention, as shown in the principle diagram of FIG. and a first error detection means 2 for detecting an error.

A second error detection means 3 is provided for detecting the presence or absence of an error that occurs when data is written to and read from the read address.

[Effect]

In addition to error detection by the conventional first error detection means, the second error detection means also detects test data different from the read data at the same address after reading the read data in the storage device A. As soon as it is written, it is read and the written data at this time is compared with the read data.

It is configured to check whether there is an error in the address.

〔Example〕

FIG. 2 shows a configuration diagram of the embodiment.

The first error detection means 2 is composed of the same error detection code generation section 21 and error detection section 22 as in the conventional example,
The read data is checked for errors in the same manner as in the conventional example.

The second error detection means 3 is composed of a 9-inversion section 31, a write/read section 32, and a collation section 33, and generates inverted data of the read data used for error detection by the first error detection means 2. , read this immediately after writing to the same address.

By comparing the written data and the read data at this time, it is checked whether there is an error in the address.

The first error detection means 2 and the second error detection means 3 are
Each sends a detection signal when an error is detected, and O
The R circuit 5 takes the logical sum of the two and sends it to the processing device 4.

〔Effect of the invention〕

As explained above, in the error detection circuit according to the present invention,
In addition to performing error detection using conventional methods, the reliability of read data can be greatly improved by checking for errors in the address immediately after reading the read data.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a configuration diagram of the embodiment. FIG. 3 is an explanatory diagram of a conventional example. In the figure. l is a storage device. 2 is the first error detection means. 3 is a second error detection means. 4 is a processing device. 21 is an error code generation section, and 22 is an error detection section. 31 is an inverting section, and 32 is a writing/reading section. 33 represents a collation unit, and 5 represents an OR circuit.

Claims (2)

[Claims] (1) A first error detection means (2) that detects the presence or absence of an error in read data read from a specified address of the storage device (1) using an error detection code, and writes data to the address after said reading. An error detection circuit comprising: second error detection means (3) for detecting the presence or absence of an error that occurs during reading. (2) The error detection circuit according to claim (1), wherein the second error detection means (3) uses inverted data of the read data as data to be written.