JPH02287743A - Decision system for writing to defective memory - Google Patents
Decision system for writing to defective memoryInfo
- Publication number
- JPH02287743A JPH02287743A JP1109660A JP10966089A JPH02287743A JP H02287743 A JPH02287743 A JP H02287743A JP 1109660 A JP1109660 A JP 1109660A JP 10966089 A JP10966089 A JP 10966089A JP H02287743 A JPH02287743 A JP H02287743A
- Authority
- JP
- Japan
- Prior art keywords
- uncorrectable error
- address information
- detected
- processor
- storage means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002950 deficient Effects 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims abstract description 5
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003745 diagnosis Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は不良メモリへの書込み判定方式に関し、特に訂
正不能エラーを検出したときのアドレス情報を記憶して
おき、書込み命令を受けたときのアドレスと比較するこ
とによって不良(訂正不能エラーを生じた)メモリへの
書込みを判定し、プロセッサへ伝える不良メモリへの書
込み判定方式に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a write determination method for a defective memory, and in particular, it stores address information when an uncorrectable error is detected, and stores address information when a write command is received. The present invention relates to a method for determining writing to a defective memory (in which an uncorrectable error has occurred) by comparing the address with the address, and transmitting the information to a processor.
(従来の技術)
従来この種の不良メモリへの書込み判定方式は、記憶装
置が訂正不能エラーを検出するとプロセッサに報告し、
プロセッサは訂正不能エラーの報告を受けると記憶装置
より詳細情報を読出すなどしてソフトウェアにより判定
し、以後不良(訂正不能エラーを検出した)メモリへの
書込みや読出しを禁止していた。(Prior Art) Conventionally, in this type of write determination method for defective memory, when a storage device detects an uncorrectable error, it reports it to a processor;
When the processor receives a report of an uncorrectable error, it reads detailed information from the storage device, makes a determination using software, and thereafter prohibits writing to or reading from the defective memory (in which the uncorrectable error has been detected).
(発明が解決しようとする課題)
上述した従来の不良メモリへの書込み判定方式は、上述
のように、記憶装置が訂正不能エラーを検出するとプロ
セッサに報告し、プロセッサは訂正不能エラーの報告を
受(つると記憶装置より詳細情報を読み出すなどしてソ
フトウェアにより判定し以後不良メモリへの書込みを禁
止しているので、記憶装置やプロセッサの故障、ソフト
ウェアのバグにより訂正不能エラーを検出したことが判
定できない場合、不良(訂正不能エラーを生じる)メモ
リに対して書込みや読み込みを行っても認識できないと
いう欠点がある。本発明の目的は、上記従来技術の問題
点に鑑みて記憶装置やプロセッサの故障、ソフトウェア
のバグにより訂正不能エラーを検出したことが判定でき
ない場合でも、訂正不能エラーを生じたメモリを判定す
ることのできる判定方式を提供することにある。(Problems to be Solved by the Invention) In the conventional write determination method for a defective memory, as described above, when the storage device detects an uncorrectable error, it reports it to the processor, and the processor receives the report of the uncorrectable error. (The software determines this by reading out detailed information from the storage device and prohibits future writing to the defective memory, so it is determined that an uncorrectable error has been detected due to a failure in the storage device or processor, or a software bug.) If this is not possible, there is a drawback that writing or reading to a defective memory (which causes an uncorrectable error) cannot be recognized.In view of the above-mentioned problems of the prior art, it is an object of the present invention to prevent malfunctions in storage devices and processors. An object of the present invention is to provide a determination method that can determine a memory in which an uncorrectable error has occurred even when it cannot be determined that an uncorrectable error has been detected due to a software bug.
(課題を解決するための手段)
本発明は、上記の目的を達成するために次の手段構成を
有する。即ち、本発明の不良メモリへの書込み判定方式
は、訂正不能エラー検出機能を備えた記憶装置において
; 訂正不能エラーを検出すると訂正不能エラーを検出
したことを記憶する記憶手段と; そのときのアドレス
情報を記憶する記憶手段と; プロセッサからの書込み
命令を認識する認識手段と; 前記認識手段が書込み命
令を認識しかつ前記記憶手段が訂正不能エラーを検出し
たことを記憶しているときに限り、書込み命令のアドレ
ス情報と前記記憶手段のアドレス情報を比較する比較手
段と; 前記比較手段の結果をプロセッサへ伝達する伝
達手段と; を備えることを特徴とする不良(訂正不能
エラーを生じた)メモリへの書込み判定方式である。(Means for Solving the Problems) The present invention has the following means configuration to achieve the above object. That is, the write determination method for a defective memory of the present invention is provided in a storage device equipped with an uncorrectable error detection function; When an uncorrectable error is detected, a storage means for storing the fact that an uncorrectable error has been detected; and an address at that time. storage means for storing information; recognition means for recognizing a write command from the processor; only when the recognition means recognizes the write command and the storage means remembers that an uncorrectable error has been detected; A defective memory (in which an uncorrectable error has occurred), comprising: a comparison means for comparing address information of a write command and address information of the storage means; and a transmission means for transmitting the result of the comparison means to a processor. This is a writing judgment method.
(実 施 例)
次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例の構成を示すブロック図で
ある。メモリからの読出しデータに訂正不能エラーがあ
ること即ち不良メモリがあることを検出できるECC回
路1は、訂正不能エラーを検出すると訂正不能エラーを
検出したことを信号線11へ出力する。エラー記憶レジ
スタ2は信号線11より訂正不能エラーを検出した報告
を受けると、訂正不能エラーを受けたことを記憶すると
ともに内容を信号線12へ出力する。エラーアドレスレ
ジスタ3は信号線11より訂正不能エラーを検出した報
告を受けると、プロセッサからの命令のアドレス情報を
伝える信号線15よりそのときのアドレス情報を取込み
、訂正不能エラーを検出した命令のアドレス情報を記憶
するとともに、内容を信号線13へ出力する。書込み命
令認識回路6は、プロセッサの命令を伝える信号線16
より命令を取込み、書込み命令であるがどうか調べ結果
を信号線17へ出力する。比較回路4は信号線17より
書込み命令を認識したことの報告を受け、かつ、信号線
12よりエラー記憶レジスタ2が訂正不能エラーを記憶
しているときに限り、信号線15からのアドレス情報と
信号線13からの訂正不能エラーを検出した命令のアド
レス情報とを比較し、結果が一致しているときは信号線
14を通してプロセッサ5へ伝える。(Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The ECC circuit 1, which can detect that there is an uncorrectable error in the data read from the memory, that is, that there is a defective memory, outputs to the signal line 11, when an uncorrectable error is detected, the fact that an uncorrectable error has been detected. When the error storage register 2 receives a report from the signal line 11 that an uncorrectable error has been detected, it stores the fact that an uncorrectable error has been received and outputs the contents to the signal line 12. When the error address register 3 receives a report from the signal line 11 that an uncorrectable error has been detected, the error address register 3 reads the address information at that time from the signal line 15 that conveys the address information of the instruction from the processor, and stores the address of the instruction in which the uncorrectable error has been detected. It stores information and outputs the contents to the signal line 13. The write command recognition circuit 6 is connected to a signal line 16 that transmits processor commands.
It takes in the command, checks whether it is a write command, and outputs the result to the signal line 17. The comparator circuit 4 receives a report from the signal line 17 that a write command has been recognized, and only when the error storage register 2 stores an uncorrectable error from the signal line 12, compares the address information with the signal line 15. It compares the address information of the instruction in which the uncorrectable error is detected from the signal line 13, and if the results match, it is transmitted to the processor 5 through the signal line 14.
(発明の効果)
以上説明したように本発明は、記憶装置が訂正不能エラ
ーを検出するとそのときのアドレス情報と訂正不能エラ
ーを検出したことを記憶する記憶手段及びプロセッサか
らの書込み命令を認識する認識手段と認識手段が書込み
命令を認識しがっ記憶手段が訂正不能エラーを検出した
ことを記憶しているときに限り、書込み命令のアドレス
情報と記憶手段のアドレス情報を比較する比較手段と比
較手段の結果をプロセッサへ伝達する伝達手段とを備え
ることにより、記憶装置やプロセッサの故障、ソフトウ
ェアのバグにより訂正不能エラーを検出したことが判定
できない場合においても、訂正不能エラーを生じたメモ
リに対して書込みを行ったときにそのことが判定される
ので不良(訂正不能エラーを生じる)メモリを使い続け
ることが無く、装置の信頼性が向上するという効果があ
る。(Effects of the Invention) As explained above, when the storage device detects an uncorrectable error, the storage device recognizes the address information at that time and the storage means for storing the detection of the uncorrectable error, and a write command from the processor. The recognition means and the comparison means compare the address information of the write command and the address information of the storage means only when the recognition means recognizes the write command and the storage means remembers that an uncorrectable error has been detected. By providing a transmission means for transmitting the results of the means to the processor, even if it cannot be determined that an uncorrectable error has been detected due to a failure of the storage device or processor or a software bug, the memory in which the uncorrectable error has occurred can be handled. Since this is determined when writing is performed, there is no need to continue using a defective memory (which causes an uncorrectable error), and the reliability of the device is improved.
また初期診断により全てのメモリの確認を行っておけば
、プロセッサが誤って不良メモリに対して書込みを行っ
た場合、記憶装置が判定しプロセッサに伝えるので、プ
ロセッサは別のメモリに再書込みができ、書込みデータ
を失わないという効果がある。In addition, if all memory is checked during initial diagnosis, if the processor accidentally writes to bad memory, the storage device will determine this and notify the processor, allowing the processor to rewrite to another memory. This has the effect of not losing written data.
第1図は本発明の一実施例である記憶装置のブロック図
である。
1・・・・・・ECC回路、 2・・・・・・エラー記
憶レジス夕、 3・・・・・・エラーアドレスレジスフ
、4・・・・・・比較回路、 5・・・・プロセッサ、
6・・・・・・書込み命令認識回路、 11〜1号線
。FIG. 1 is a block diagram of a storage device that is an embodiment of the present invention. 1...ECC circuit, 2...Error storage register, 3...Error address register, 4...Comparison circuit, 5...Processor ,
6...Write command recognition circuit, lines 11-1.
Claims (1)
正不能エラーを検出すると訂正不能エラーを検出したこ
とを記憶する記憶手段と;そのときのアドレス情報を記
憶する記憶手段と;プロセッサからの書込み命令を認識
する認識手段と;前記認識手段が書込み命令を認識しか
つ前記記憶手段が訂正不能エラーを検出したことを記憶
しているときに限り、書込み命令のアドレス情報と前記
記憶手段のアドレス情報を比較する比較手段と;前記比
較手段の結果をプロセッサへ伝達する伝達手段と;を備
えることを特徴とする不良メモリへの書込み判定方式。In a storage device equipped with an uncorrectable error detection function; when an uncorrectable error is detected, a storage means for storing the fact that an uncorrectable error has been detected; a storage means for storing address information at that time; and a storage means for storing address information at that time; recognition means for recognizing; only when the recognition means recognizes the write command and the storage means stores that an uncorrectable error has been detected, compares the address information of the write command with the address information of the storage means; A method for determining whether to write to a defective memory, comprising: a comparison means for determining the result of the comparison means; and a transmission means for transmitting the result of the comparison means to a processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1109660A JPH02287743A (en) | 1989-04-28 | 1989-04-28 | Decision system for writing to defective memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1109660A JPH02287743A (en) | 1989-04-28 | 1989-04-28 | Decision system for writing to defective memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02287743A true JPH02287743A (en) | 1990-11-27 |
Family
ID=14515926
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1109660A Pending JPH02287743A (en) | 1989-04-28 | 1989-04-28 | Decision system for writing to defective memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02287743A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090282305A1 (en) * | 2008-05-09 | 2009-11-12 | A-Data Technology Co., Ltd. | Storage system with data recovery function and method thereof |
-
1989
- 1989-04-28 JP JP1109660A patent/JPH02287743A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090282305A1 (en) * | 2008-05-09 | 2009-11-12 | A-Data Technology Co., Ltd. | Storage system with data recovery function and method thereof |
US8418030B2 (en) * | 2008-05-09 | 2013-04-09 | A-Data Technology Co., Ltd. | Storage system with data recovery function and method thereof |
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