JPS62212750A - Memory check system - Google Patents

Abstract

PURPOSE:To decide whether the write or read data on a memory causes an error by using a deciding means to discriminate the error information and suppressing the reading action to the memory when an uncorrectable error occurs according to the result of discrimination of said error information. CONSTITUTION:A deciding circuit 5 reports a 1-bit error of a write mode to the read data receiver side via a signal line 19 by the error section information on a signal line 18 read out of an error information memory part 4 and the read control signal received via a signal line 14 in case the error section information shows a 1-bit error. At the same time, the read data given from a memory 1 are also transmitted by a memory control circuit 2 via a signal line 16 and then checked at its receiver side. Thus the 1-bit error is detected and corrected. Then the circuit 5 reports a plural-bit error to the receiver side of the read data when the error section information shows a plural-bit error. Thus it is possible to discriminate easily the trouble of the data obtained immediately before its writing from that of the memory read data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory check method, and in particular, it checks data immediately before writing, stores the error information, and uses the stored error information when reading. Regarding the reference memory check method.

[Conventional technology]

Conventional memory devices have been equipped with a data system check circuit only for data read from the memory, but this has not been able to accurately identify faults. As a countermeasure against this problem, as described in Japanese Patent Publication No. 60-46457, the data is checked even immediately before being written into the memory, and if an error occurs, the address at that time is stored. When an error is detected during data checking during reading, the storage address is referred to using the error address, and if there is a matching address, it is determined that there is an error in the data being written, and if there is no matching, it is determined that the memory is faulty. However, since an error in the write data of the memory is propagated to the read data, when an error is detected in the write data, it means that an error also exists in the read data. When a multiple bit error is detected in write data, if the read address matches the stored write address when reading, there is no need to perform a read operation to the memory, and it is immediately considered a multiple bit error. You can report errors. Also, when writing occurs again to the same address, if the write data is not detected by the check circuit, it is necessary to cancel the memory address.
This was not taken into consideration.

[Problem that the invention seeks to solve]

In the conventional technology, the data immediately before being written into the memory and the read data are checked, and when an error in the read data is detected, it is determined whether the cause of the error is during writing. However, even without checking the read data, if an error is stored in the write data at the same address, it is possible to determine the read data. Also, if writing is performed to the same address in memory many times and the data is different each time, the written data check circuit will detect an error and store the error information, but if the next written data to the same address is If it does not occur, it is necessary to cancel the error information of the previous written data.

An object of the present invention is to provide a method for optimally determining whether an error is caused by writing data or reading data from a memory.

[Means for solving problems]

The above purpose is to provide a check circuit that checks written data during writing, and to store error classification information in addition to the error address when an error is detected, and to prevent writing to the same address as the stored error address. This is achieved by canceling the stored error information when no error is detected in the write data, and storing new error information when an error is detected.

[Effect]

Data error detection is performed at the time of damage, and error classification information is stored. What is error classification information here?

This is a single bit error or multiple bit errors.

This error classification information is stored for each write regardless of whether or not an error is detected. Next, when reading from the memory, the error classification information is referred to at that address, the error classification is identified, and if it is a 1-bit error, the error is reported to the data receiving side. If the error is a multi-bit error that cannot be automatically corrected, the error will be reported immediately, but the read operation to the memory will be canceled or prohibited. This makes it possible to report an error to the data receiving side earlier than the result of checking the read data, and on the memory side, wasteful read operations can be suppressed to prevent error propagation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of this embodiment. memory 1
When writing data to the memory 1, the memory control circuit 2 that receives the write request signal 10 sends a control signal &IX to drive the memory 1.
(RAS, CAS, WE, etc.) 11 writes write data to the address specified by the signal line 12 via the signal line 13. The check circuit 3 checks the write data based on the data bits and check pits of the write data on the signal line 13, and outputs error classification information (one bit error or multiple bit error) through the signal line 15. Although not shown in the figure, there is also a check circuit on the receiving side of the read data via the signal line 16, which detects and corrects 1-bit errors and detects multiple bit errors, and detects errors in the write data on the signal line 13. remains as signal m
Since the error is propagated to the read data on the memory 1, the check circuit 3 only performs error detection immediately before writing to the memory 1.

The error information storage section 4 is addressed by the address itself on the signal line 12, and the error classification information on the signal line 15 outputted from the check circuit 3 is controlled to be written into the error information storage section 4 via the signal line 14. Write and memorize signals. That is, regardless of whether or not the check circuit 3 detects an error in the write data, error classification information is written into the storage unit 4 for the corresponding address.

FIG. 2 shows the format of error classification information stored in the error information storage section 4. As shown in FIG. Initial letter jl! The error classification information is OO as in case 1 shown in Fig. 2, and when the check circuit 3 does not detect an error, it is OO in case 1.
is stored, and when an error is detected, error classification information of case 2 or case 3 is stored. When writing to the memory 1, the check circuit 3 detects an error in the write data on the signal line 13, and the conditions for writing the error classification information to the error information storage section 4 are as shown in FIG. Check circuit 3 regardless of the presence or absence of error detection.
The error classification information, which is the output signal of , is written as is using the address on the signal line 12 and the write control signal of the error information storage section 4 via the signal line 14.

When reading from the memory 1, when the read request signal 10 and the address on the signal line 12 are received, the read control signal via the signal line 14 and the address on the signal line 12 are transmitted to the error information storage unit 4, and the corresponding Read address error information. This means that by referring to the error information storage section 4 using the address on the signal line 12, error classification information whose read address matches the stored error address is read out. The determination circuit 5 uses the error classification information on the signal line 18 read from the error information storage unit 4 and the read control signal via the signal line 14 to
When the error classification information indicates a 1-bit error, the 1-bit error during writing is reported to the read data receiving side via the signal line 19. The memory control circuit 2 also sends read data from the memory via the signal line 16.

The data receiving side checks the read data and detects and corrects 1-bit errors. Further, when the error classification information indicates a multi-bit error, the determination circuit 5 reports the multi-bit error during writing to the read data receiving side, and also informs the memory control circuit via the signal line 17 that there is a multi-bit error. 2 and cancel or prevent the read operation from being executed, it is possible to suppress wasteful read operations to the memory 1 and prevent error propagation.

Although not shown in FIG. 1, a check circuit has conventionally been provided for the read data on the signal line 16, and based on the check result of this read data and the error report signal from the judgment circuit 5 to the signal line 19. It is possible to easily determine whether it is a data error immediately before writing to the memory 1 or a data error reading from the memory 1. Furthermore, since the report signal of a 1-bit error or multiple-bit error during writing, which is reported from the determination circuit 5 via the signal line 19, is considerably earlier than the error determination obtained from the check result of the read data from the memory 1, the memory read data On the receiving side, it is possible to perform various types of error processing for the error.

〔Effect of the invention〕

According to the present invention, in a memory device adopting the ECC method, data immediately before being written to the memory is checked,
Since error classification information is stored, it is possible to easily distinguish faults between data immediately before being written to the memory and data read from the memory. Further, when reading data, the error information is not determined based on the check result of the read data while it is stored in the error information storage unit, but is determined based on the stored error information, so that the error report can be made more quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing error classification information, and FIG. 3 is a diagram showing conditions for writing error classification information into an error information storage section. DESCRIPTION OF SYMBOLS 1... Memory, 2... Memory control circuit, 3... Check circuit, 4... Error information storage part, 5... Judgment circuit, 10-19... Signal line. Special l concave d error yōdai ku tsu 1N seal lj: ,, lkigo earn (L ra ku s 7 h 〒() also 2 phantom

Claims (1)

[Claims] 1. In a memory that adopts the ECC method, there is a check circuit that checks written information when writing to the memory, and error information results obtained from the check circuit in response to a write request to the memory are sequentially stored and referenced by a read request to the memory. and a determining means for identifying the error information stored in the error information storage means when reading from the memory, and when an error that cannot be corrected based on the identification result of the error information, the reading operation to the memory is performed. A memory check method characterized by suppressing.