JPH01283654A - Error detecting device - Google Patents

Abstract

PURPOSE:To appropriately know the replacement time of a storage element by holding a generation address of a 1-bit error and 1-bit error generating bit instructing data in a generation address buffer of plural 1-bit errors and a 1-bit error generating bit instructing data buffer. CONSTITUTION:In an error address buffer 23, a 1-bit error is detected and corrected by an error check code checking circuit 20, plural write data which have been sent out are held, and a 1-bit error generating bit instructing data buffer holds plural 1-bit error generating bit instructing data for instructing a generating bit of a 1-bit error which has been generated. Also, a data fault value buffer holds a data fault value for showing whether the 1-bit error which has been generated has caused a fault by '0' or has caused a fault by '1'. Moreover, an output selecting circuit 22 selects the contents of an error address buffer 23, the contents of the 1-bit error instructing data buffer and the contents of the data fault value buffer. In such a way, the replacement time of a storage element can be known.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an error detection device for a storage device using an error check code.

[Conventional technology]

In this type of conventional error correction method, an error check code (ECC) is used to determine whether or not there is an error in the information read from the storage device, and if the error is a 1-bit error, it is corrected. and is configured to report one-bit errors to the central processing unit. When the central processing unit receives this report, it performs processing such as checking the position of the 1-bit error. If the error was a 2-bit error, the error was not corrected, but the error was reported to the central processing unit and the system was brought down.

[Problem to be solved by the invention]

In this way, in the conventional error correction method, when a 1-bit error occurs, the read information is corrected and processing continues.
The central processing unit has to perform processing such as checking the position of occurrence each time such a one-bit error occurs, resulting in a problem that the processing capacity of the central processing unit is reduced.

In addition, in a state where a 1-bit error exists in the storage device,
2, the probability of occurrence of a hit error also increases, and there is therefore a risk of system failure. In this case, in the conventional method, 1
Since there is no means to analyze a memory element in which a short error has occurred, there are problems in that it is difficult to isolate and replace a defective memory element, and it is difficult to know when to replace the defective memory element.

Therefore, an object of the present invention is to sequentially store a 1-bit error address and 1-bit error occurrence bit instruction data in a plurality of buffers, and read out a plurality of error addresses, 1-bit error occurrence bit instruction data, and data failure values as necessary. As a result, “0” in the memory element where 1-bit errors occur frequently
It is an object of the present invention to provide an error detection device that makes it possible to distinguish between a "fixed failure" and a "1" fixed failure, and to know when to replace it.

[Means to solve the problem]

The error detection device of the present invention includes a memory element into which write data is written, an error check code generation circuit that generates and attaches an error check code to the written data when writing to the memory element. An information processing device comprising: an error check code check circuit that checks an error check code added to write data written to the storage device when reading the memory, and corrects a 1-bit error when it is detected; An error address buffer that holds multiple pieces of address information of write data that has been detected and corrected by the error check code check circuit and sent out, and a 1-bit error occurrence bit that indicates the bit where the 1-bit error occurred. A 1-bit error occurrence bit instruction data buffer that holds multiple pieces of instruction data, and a data failure value buffer that holds a data failure value that indicates whether the 1-bit error that occurred occurred at “0°” or “1”. Then, the correction information of the write data detected and corrected by the error check code circuit is sent, and when reading the error address and error pit position, the contents of the error address buffer and the contents of the 1-bit error instruction data buffer are , and an output selection circuit that selects and outputs the contents of the data failure value buffer.

Therefore, when the error detection device according to the present invention is used, the error address buffer holds a plurality of pieces of write data that have been detected and corrected by the error check code check circuit and sent out, and the error address buffer is configured to hold a plurality of pieces of write data that have been sent out after the error check code check circuit detects and corrects them. The data buffer holds a plurality of 1-bit error occurrence bit instruction data indicating the occurrence bit of the 1-bit error that has occurred. And the data failure value buffer is
It holds a data failure value indicating whether the generated 1-bit error is "0" or "1". Furthermore, the output selection circuit selects the contents of the error address buffer and 1
Select the contents of the bit error indication data buffer and the contents of the data failure value buffer. This makes it possible to know the address of the storage device where 1-bit errors occur frequently, the data bit position where 1-bit errors occur frequently, and the data failure value where 1-bit errors occur frequently.

〔Example〕

The present invention will be described in detail with reference to the embodiments above.

FIG. 1 shows the error detection device of this embodiment.

In the figure, a memory element 11 is connected to a central processing unit (not shown) via an address bus 12 and a data bus 13. The error check code (ECC) generation circuit 15 is
It is connected to a data bus 13 , an error check code (ECC) check circuit 16 , and further connected to a storage element 11 via a storage element input/output data bus 18 . Error check code (ECC) check circuit 2
0 is connected to the timing generation circuit 21, the output selection circuit 22, and the error buffer 23.

Next, the operation will be explained.

When a memory write request is received from a central processing unit (not shown),
ECC generation circuit 15 generates an ECC bit for write data on data bus 13.

Then, write data is written to the memory element 11 via the memory element input/output data bus 18.

When a memory read request is received from a central processing unit (not shown),
The ECC check circuit 20 performs an FCC check on read data read from the storage element 11. Then, when a 1-bit error is detected, it is corrected.
No data correction is performed when a 2-bit error is detected. Then, the ECC correction data 25 is outputted to the data bus 13 via the output selection circuit 22, and sent to the central processing unit (not shown).

Here, when a memory read request is received from a central processing unit (not shown) and a 1-bit error occurs, a 1-bit error detection signal 28 is sent to the timing generation circuit 21. Upon receiving this, the timing generation circuit 21 increments the error buffer number and notifies the error buffer 23 of the error buffer number using the error buffer number instruction signal 30. Furthermore, an error buffer write Hals 31 is sent to this error buffer 23, and a storage element switching address 32 when a 1-bit error occurs, 1-bit error occurrence bit instruction data 33, and a bit failure is “0” or “1”
A data failure value 34 indicating "is stored."

Furthermore, upon receiving an error buffer read instruction 36 from a central processing unit (not shown) via the address bus 12, the timing generation circuit 21 receives an error storage element number 36 in the error buffer 23 indicated by the error buffer number instruction signal 30. , a 1-bit error occurrence bit designation data buffer output 39 , and a data failure value buffer output 40 are sequentially sent to a central processing unit (not shown) by operating the output selection circuit 22 . At this time, the error buffer number indication signal 30 is incremented.

In this way, the central processing unit (not shown) can know the appropriate time to replace the storage element 11 by knowing the error storage element number, data error position, and data failure value stored in the error buffer 23. .

〔Effect of the invention〕

As described above, the error detection device of the present invention stores the 1-bit error occurrence address and 1-bit error occurrence bit instruction data in a plurality of 1-bit error occurrence address buffers and 1-bit error occurrence bit instruction data buffer. As a result, it is possible to know (1) the address when 1-bit errors occur frequently, (2) the data bit position where 1-bit errors occur frequently, and (3) the data failure value where 1-bit errors occur frequently. This has the effect of allowing you to appropriately know when to replace the element.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an error detection device according to the present invention. 11... Memory element, 15... ECC generation circuit, 20... ECC check circuit, 22...
- Output selection circuit, 23...Error buffer. Applicant NEC Corporation NEC Engineering Co., Ltd. Agent Patent attorney Umeo Yamauchi

Claims (1)

[Scope of Claims] A memory element into which write data is written, an error check code generating circuit that generates and attaches an error check code to the write data when writing to the memory element, and an error check code generation circuit that generates and attaches an error check code to the write data when writing to the memory element; and an error check code check circuit that checks an error check code added to the write data written in a storage element and corrects a 1-bit error when it is detected, the error check comprising: The code check circuit detects and corrects 1-bit errors and stores an error address buffer that holds multiple pieces of address information for the sent write data, and 1-bit error occurrence bit instruction data that indicates the bit where the 1-bit error occurred. The data buffer holds multiple 1-bit error occurrence bits and indicates whether the 1-bit error that occurred is "0" and a failure has occurred, or "1".
a data failure value buffer that holds a data failure value indicating whether a failure has occurred; and correction information of the write data detected and corrected by the error check code check circuit, and when reading the error address and error bit position, An output selection circuit that selects the contents of the error address buffer, the contents of the 1-bit error indication data buffer, and the contents of the data failure value buffer based on the correction information of the write data. Detection device.