JPH01116746A - Information processor - Google Patents

Abstract

PURPOSE:To decide a storage element in which 1-bit error occurs frequently and to know its exchange time by reading plural error addresses and the data positions of the 1-bit error calculated from a syndrome out of error buffer if necessary. CONSTITUTION:The title device has an error position detecting circuit 70 to calculate a bit position where the 1-bit error occurs from the error syndrome outputted from an error buffer 60 and an output selecting circuit 80 to receive the error address held in the error buffer 60 and output data from the error position detecting circuit 70 and to output these data in accordance with a reading-out request from a central processing unit. An error detecting/correcting circuit 50 corrects the 1-bit error occurring in read-out data from a storage device 30, sends it to the output selecting circuit 80 and sends the error address and the error syndrome of the data in which the detected 1-bit error occurs to the error buffer 60. Thus, the storage element in which the 1-bit error occurs frequently can be decided and the exchange time of the storage element can be known.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to error detection in read data (read information) of a storage device using an error check code.

[Conventional technology]

In conventional information processing apparatuses of this kind, error detection of information read from a storage device uses an error check code (EC) to determine whether there is an error in information read from the storage device.
C), and if the error is a 1-bit error, it is corrected, and the fact that a 1-bit error has been detected is reported to the central processing unit.

Upon receiving this report, the central processing unit performs processing such as checking the bit position where the 1-bit error has occurred.

If the error that occurs in the read information is a 2-bit error, the error is not corrected and the central processing unit is notified that a 2-bit error has been detected, and the central processing unit receives this report and causes the system to go down. It was structured like this.

[Problem that the invention seeks to solve]

As mentioned above, in conventional information processing devices, even if a 1-bit error occurs, the read information from the storage device is corrected and processing continues, but each time a 1-bit error occurs in the read information, the central processing unit There is a problem in that the original processing capacity of the central processing unit is degraded due to processing such as checking the bit position of a bit error.

Furthermore, when a 1-bit error exists in a storage device, the probability of a 2-bit error occurring increases, leading to a system failure, but conventional information processing devices analyze the storage elements in the storage device where a 1-bit error has occurred. There is a problem in that it is difficult to replace the memory element because there is no means to do so, and it is not possible to determine the appropriate time to replace the memory element.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide an information processing device that can determine a storage element that frequently causes one-bit errors, and can know when to replace the storage element.

[Means for solving problems]

In order to achieve the above object, the present invention includes an error buffer that holds a plurality of error addresses and error syndromes of data when a 1-bit error occurring in data read from a storage device is detected, and a plurality of error syndromes that are output from the error buffer. An error position detection circuit that calculates the bit position where a 1-bit error has occurred from the error syndrome, and a request to read these data from the central processing unit after receiving the error address held in the error buffer and the output data from the error position detection circuit. It has an output selection circuit that outputs according to the
The error detection/correction circuit sends corrected read data that corrects a 1-bit error that occurred in the read data from the storage device to the output selection circuit, and also outputs the error address and error syndrome of the data in which the detected 1-bit error has occurred. This is characterized by sending the data to an error buffer.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of an information processing apparatus according to the present invention. In the figure, a storage device 30 and a central processing unit (not shown) are connected via an address bus 10 and a data bus 20.

When there is a write request from the central processing unit to the storage device 30, the FCC generation circuit 40 generates an ECC bit for the write data output on the data bus 20, and sends the ECC bit to the storage device input/output data path 100. Memory writing is performed to the memory element in the memory device 30.

On the other hand, when a read request is issued from the central processing unit to the storage device 30, the ECC check circuit 50 checks the error check code (FCC) of the read data, and detects a 1-bit error in the read data. If a 2-bit error is detected, the read data is corrected, and if a 2-bit error is detected, the read data is not corrected and the ECC corrected data 110 is sent to the data bus 2 via the output selection circuit 80.
0 and sent to the central processing unit.

In this embodiment, when a 1-bit error occurs during a read request to the storage device 30 of the central processing unit, the ECC check circuit 50 outputs a 1-bit error detection signal 112 to the timing generation circuit 90. Timing generation circuit 90
increments the error buffer number for the error buffer 60, notifies the error buffer number by the error buffer number instruction signal 114, sends the error buffer write pulse 116, and sets the storage element switching address 118 and ECC syndrome 120 is stored.

On the other hand, the central processing unit issues an error buffer read instruction 1 to the timing generation circuit 90 via the address bus lO.
30, timing generator circuit 90 outputs error buffer number designation signal 114 to error buffer 60. As a result, the error storage element number 140 indicated by the error buffer number indication signal 114 is outputted from the error buffer 60 to the output selection circuit 80, and the error syndrome 142 is outputted to the error detection circuit 70. The error detection circuit 70 calculates the error pit position from the input error syndrome, and outputs a data error position signal 150 indicating the error pit position to the output selection circuit 80.

Output selection circuit 80 sequentially sends error storage element number 140 and data error position signal 150 to the central processing unit connected via address bus 10 and data bus 20 while incrementing the error buffer number. As a result, the central processing unit can determine the error storage element number and data error position stored in the error buffer, and can know when to replace a storage element that frequently causes 1-bit errors.

〔Effect of the invention〕

As explained above, in the present invention, the address and syndrome of a 1-bit error are stored sequentially in an error buffer consisting of a plurality of buffers, and if necessary, the error address is stored from the error buffer and the 1-bit error is calculated from the syndrome. Since the structure is configured such that a plurality of data positions can be read out, it is possible to determine which storage element frequently causes 1-bit errors, and therefore it is possible to know when to replace it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. 10...Address bus, 20...Data bus, 30...Storage device, 40...ECC generation circuit, 50...ECC check circuit, 60...
・Error buffer, 70...Error position detection circuit, 80...Output selection circuit, 90...Timing generation circuit.

Claims (1)

[Scope of Claim] An information processing device comprising a central processing unit, a storage device, and an error detection/correction circuit for detecting and correcting a 1-bit error occurring in data read from the storage device, comprising: an error buffer that holds a plurality of error addresses and error syndromes of data at the time of detection; an error position detection circuit that calculates a bit position where a 1-bit error has occurred from the error syndrome output from the error buffer; and an output selection circuit that receives output data from the held error address and error position detection circuit and outputs these data in response to a read request from the central processing unit, and the error detection/correction circuit receives output data from the storage device. Sends the corrected read data that corrects the 1-bit error that occurred in the read data to the output selection circuit,
An information processing device characterized in that an error address and an error syndrome of data in which a detected 1-bit error has occurred are sent to the error buffer.