JPH02197942A - Main storage - Google Patents

Abstract

PURPOSE:To attain an access to the data in the same timing as a case where no error is detected by outputting the data corrected by a correction means via a switch means only when an error bit is included in a data bit part and transmitting a correctable error production signal via a report means. CONSTITUTION:When a read address 107 is received in a cycle T1, the data on a designated address of a memory module 3 is held by a read data register RDR 4 in a cycle T2. The data held by the ROR 4 is checked by an error check circuit ECC 5 in the cycle T2. When an error is detected at a data bit part, the data bit part is corrected by a correction circuit 6. Then the corrected data on a signal line 102 is selected by a multiplexer 7 and outputted to the read data 103 in a cycle T3. Thus an access is possible to the data in the same timing as a case where no error is detected at all when an error is detected only at a check bit part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory device, and more particularly to a main memory device capable of correcting erroneous bits using an error-correctable code.

[Conventional technology]

Conventionally, in this type of device, if an error is detected and corrected using an error-correctable code, the error is detected.

Due to the time delay in correction, the access time is extended by one cycle compared to when the error is not detected and the data read from the memory module can be used as is.

[Problem to be solved by the invention]

In conventional devices, this one-cycle delay also occurs when correcting errors in the check focus section of the error correction code, which is not used at all in devices that access the main memory. The disadvantage is that when an error occurs, the access time increases.

An object of the present invention is to provide a main memory device that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the present invention detects the occurrence of a correctable error in a main memory device that corrects error bits using an error correctable code consisting of a data bit part and a check bit part. , a first detection reporting means for reporting, a second detection reporting means for detecting and reporting that the error bit is included only in the check bit part, a means for correcting the error bit, and a means for correcting the corrected data. a switching means for switching uncorrected data, the switching means outputs data corrected by the correction means, and the first and second detection reporting means report main memory access results. It is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, ECG1 is a check bit generation circuit that generates a check bit portion of an error correctable code from write data 100. WDR2 is a write data register that holds an error correction code consisting of a data bit part (i.e. write data) and a check bit part, memory module 3 is a storage part that stores data (including the check bit part), and RDR4 is a register from memory module 3. This is a register that holds the read data (including the check bit part). ECC5 is a check circuit that checks data errors on RDR4. If an error is detected only in the data bit part, it turns on the signal line 104, and if an error is detected only in the check bit part, it turns on the data error signal line 10.
Turn on 6. Further, when the ECC 5 does not detect a data error (including the check bit part), it turns on the signal line 105. The correction circuit 6 is a correction circuit that corrects the read data of the RDR 4 according to the check result at the ECC 5, and the multiplexer 7 is a switching circuit that switches between the data of the RDR 4 and the error-corrected data output from the correction circuit 6. or,
The switching circuit 6 selects the corrected data 102 only when the signal line 104 is on, and selects the data 101 on the RDR 4 at other times.

Next, the read operation will be explained with reference to FIGS. 2 and 3.

When a read address is given at 107 in the T1 cycle, data at the specified address in the memory module 3 is held in the RDR4 in the T2 cycle. RDR4 data (including check bit part) is ECCed in T2 cycle.
5, and if there is no error in the data bit section (no error detected at all or error detected only in the check bit section), the multiplexer 7
Since the output of RDR4 remains selected, correct data is output to the read data line 103 after the T2 cycle, and the data error signal line 106 remains off. On the other hand, when an error is detected in the data bit part by the ECC 5, the error data bit part is corrected by the correction circuit 6, and the read data 103 is sent to the signal line 10 in the T3 cycle.
The corrected data on 2 is selected by multiplexer 7 and output. In addition, ECC5 has signal lines 104 and 1
Let 05 be a co-ion.

The device for accessing the main memory of the present invention may be configured to re-capture data only when the signal line 104 is on and the signal line 105 is off. Data can be accessed at the same timing and without a one-cycle delay as when no detection is detected.

〔Effect of the invention〕

As explained above, the present invention provides a means for detecting that an error bit is included in a data bit portion, a means for correcting the error bit, a means for switching between corrected data and uncorrected data, and a correctable error bit. occurrence reporting means, and only when an error bit is included in the data bit part, the corrected data by the correction means is outputted by the switching means, and the reporting means sends out a correctable error occurrence signal. Even if an error in the check bit portion of the correctable code is detected, data can be accessed at the same timing as when no error is detected (that is, without one cycle of access time delay).

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart when no error is detected in the data bit section, and Fig. 3 is a time chart when an error is detected in the data bit section. be. 1... ECG (check bit generation circuit) 2...
WDR (write data register) 3...Memory module 4...RDR<read data register) 5...EC
C (error check circuit) 6...Error correction circuit li! 8
7...Data switching circuit patent applicant: Ibaraki NEC Co., Ltd. Representative: Patent attorney: Sugano
Medium [1・,′-5・粂+tI-,1Ill hi-1L,) ゛(゛゛′

Claims (1)

[Claims] (1) A first detection report that detects and reports that a correctable error has occurred in a main memory device that corrects error bits using an error-correctable code consisting of a data bit section and a check bit section. means, second detection reporting means for detecting and reporting that the error bit is included only in the check bit portion, means for correcting the error bit, and switching means for switching between corrected data and uncorrected data. 2. A main memory device comprising: a main memory device, wherein data corrected by the correction means is outputted by the switching means, and main memory access results are reported by the first and second detection reporting means.