JP2503981B2 - Peripheral storage - Google Patents

Description

The present invention relates to a failure processing in a peripheral storage device when a failure in which a program cannot be executed occurs in a host device during a write operation.

(Prior Art) Conventionally, when this type of peripheral storage device detects that a failure has occurred in a higher-level device during a write operation, specific data, for example, all zero data, is written in the remaining portion of the field being written. Has been adopted, and then an error detection / correction code is added to this to perform writing, or the writing is interrupted immediately when a failure of the host device is detected.

(Problems to be solved by the invention) In this case, because a failure in which the program cannot be executed has occurred in the host device, rewriting of the field that was not correctly written, or its address, etc. Since it is impossible to output or store the above, the conventional peripheral storage device described above has the following problems.

In the former case, no error will be reported even if the field is read correctly afterwards and the error is not reported.
It was impossible to detect that writing was not performed correctly.

In the latter case, a read error is detected, so that it is possible to prevent incorrect data from being processed incorrectly, but it is not possible to distinguish between a read error due to a host device failure during writing and a read error due to a failure of a storage medium or the like. There was a flaw.

An object of the present invention is to prevent accidental use of data that has not been correctly written due to the occurrence of a failure in a host device,
An object of the present invention is to provide a peripheral recording device capable of isolating a location where a failure occurs.

(Means for Solving Problems) In order to achieve the above-mentioned object, a peripheral storage device according to the present invention has a failure detection means for detecting the occurrence of a failure of the above-mentioned device and a recording medium added to the data. An error detection / correction code generation means for generating an error detection / correction code to be written, and an error by inverting the output of the error detection / correction code generation means when a failure of the host device is detected by the failure detection means at the time of writing data. Inversion means for writing the detection and correction code, first read error checking means for checking the read error using the error detection and correction code added to the data at the time of reading the data from the recording medium, and additional read error checking means Second read error checking means for checking the read error after inverting the error detection and correction code, and the read error upon completion of the read operation of the recording medium. Whether or not the reading error is detected by the first reading error checking means, the upper device is notified that the reading is normally performed, and the reading error is detected by the first reading error checking means. In this case, if the reading error is not detected by the second read error checking means, the higher-level device is notified that the data has not been written correctly, and if the second reading error checking means detects the reading error, the reading is completed. It is configured to include an instruction execution control means for notifying the upper device that it is impossible.

(Examples) Next, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a block diagram of an embodiment of a peripheral memory device according to the present invention.

The peripheral storage device 20 includes a fault detection circuit 201, a host device connection circuit 202, a data transfer control circuit 203, an ECC generation circuit 204, an inversion circuit 205, a storage unit connection circuit 206, and an instruction execution control circuit.
207, a first read error check circuit 208, a second read error check circuit 209, and a plurality of storage units 211 ... 212.

In the present embodiment, the positioning command is issued prior to the data writing command to select the storage unit to be written, the cylinder positioning, the track selection, and the record retrieval. Since it is not directly related, its detailed description is omitted.

When a write command is issued from the host device 10 following the positioning command, the write command is transmitted to the command execution control circuit 207 through the signal line 251, the host device connection circuit 202, and the signal line 265. The instruction execution control circuit 207 issues a write command to the storage unit 211 selected by the preceding positioning command through the signal line 264, the storage unit connection circuit 206, and the signal line 271, and further through the signal line 261 the data transfer control circuit 203.
To write the data.

Write data sent from the host device 10 through the signal line 251 is written to the storage unit 211 through the host device connection circuit 202, the signal line 254, the data transfer control circuit 203, the signal line 256, the storage unit connection circuit 206, and the signal line 271. . At this time, the write data transferred from the host device at the same time is transferred from the data transfer control circuit 203 through the signal line 257 to the ECC generation circuit 204.
The error detection / correction code is generated in the ECC generation circuit 204.

When all the data to be written is transferred from the higher-level device 10, the error detection / correction code generated in the ECC generation circuit 204 is signal line 258, inversion circuit 205, signal line 259, storage unit connection circuit 206, signal line 271. Through memory unit 21
The write data sent to 1 and written from the higher-level device 10 is written subsequently.

If no failure of the host device 10 is detected during the write operation, the inversion circuit 205 does not invert the error detection / correction code.

When a failure of the host device 10 occurs during the write operation, the host device 10 uses the signal line 251, the host device connection circuit 202, and the signal line 252.
The failure detection circuit 201 is notified of the occurrence of a failure of the host device. In addition, even if the failure is not notified from the higher-level device 10, the failure detection circuit 201 is connected to the higher-level device connection circuit 2
02, the failure of the host device 10 can be detected from the operation status of the signal line 251 through the signal line 252. Fault detection circuit 201
Detects that a failure of the upper device 10 has occurred, the signal line
It makes 253 valid and notifies the inverting circuit 205 of this. The inversion circuit 205 inverts the error detection and correction code generated by the ECC generation circuit 204 when the signal line 253 is valid, and transfers it to the storage unit 211.

On the other hand, also in the read operation, the positioning command is issued from the upper level device 10 as in the case of the write command, and then the read command is issued.

When the instruction execution control circuit 207 receives the read command, it issues a read command to the memory unit 211 through the signal line 264, the memory unit selection circuit 206, and the signal line 271, and further the signal line 2
Through 61, the data transfer control circuit 203 is instructed to perform the reading process.

The data read from the memory unit 211 is the signal line 271,
Signal unit selection circuit 206, signal line 260, data transfer control circuit 203, signal line 255, host device connection circuit 202, signal line 251
Is transferred to the higher-level device 10.

The data read from the storage unit 211 and the error detection / correction code are sent to the first read error check circuit 208 and the second read error check circuit 209 through the signal line 260. In the first read inspection circuit 208, the memory unit 211
A read error is detected by inverting the error detection / correction code sent from the above, and inverting the error detection / correction code in the second read error check circuit 209.

When the read operation is completed in the memory unit 211, the instruction execution control circuit 207 checks for a read error through the signal lines 262 and 263.

If no read error is detected in the first read error check circuit 208, the instruction execution control circuit 207 outputs the signal line 26.
5, host device connection circuit 202, host device 1 through signal line 251
Notify 0 that the read was successful. When a read error is detected in the first read error check circuit 208, the state of the second read error check circuit 209 is checked,
If no reading error is detected, the instruction execution control circuit 20
It reports to the host device 10 that the data was not written correctly because a failure of the host device occurred when writing the data read in 7.

When the second read error check circuit 209 also detects a read error, the instruction execution control circuit 207 cannot read if the error correction or the read retry does not result in any of the above states. That the upper device
Notify 10

(Effects of the Invention) As described above, according to the present invention, the error detection and correction code is inverted for writing when a failure occurs in the host device during the writing operation, and the error detection and correction code is inverted during reading. By checking that the data has been written, it is possible to prevent inadvertent use of data that has not been written correctly without changing the recording format of the data. This has the effect of making it easy to distinguish from reading errors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a block diagram of an embodiment of a peripheral memory device according to the present invention. 10 ... High-order position, 20 ... Peripheral storage device 201 ... Fault detection circuit 202 ... High-order device connection circuit 203 ... Data transfer control circuit 204 ... ECC generation circuit 205 ... Inversion circuit 206 ... Memory unit connection circuit 207 ... Instruction execution control circuit 208 ... First read error check circuit 209 ... Second read error check circuit 211, 212 ... Storage unit

Claims (1)

(57) [Claims] 1. A failure detection means for detecting the occurrence of a failure of the device, an error detection / correction code generation means for generating an error detection / correction code added to data and written in a recording medium, and data Inversion means for inverting the output of the error detection and correction code generation means to write the error detection and correction code when the failure detection means detects a failure of the host device at the time of writing, and data when reading the data from the recording medium. First read error checking means for checking a read error using the error detection and correction code added to the second read error and second read error for checking the read error after inverting the error detection and correction code added to the data. The inspection means and the reading operation of the recording medium should be completed and the presence or absence of a reading error should be checked. The first reading error checking means must detect the reading error. If the reading error is detected in the first reading error checking means and the reading error is not detected in the second reading error checking means, the data is correctly written. And instruction execution control means for notifying the host device that it has not been jammed, and notifying the host device that reading is impossible if the second read error checking means also detects a read error. A peripheral storage device characterized by the above.