JPS61175743A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS61175743A
JPS61175743A JP60015895A JP1589585A JPS61175743A JP S61175743 A JPS61175743 A JP S61175743A JP 60015895 A JP60015895 A JP 60015895A JP 1589585 A JP1589585 A JP 1589585A JP S61175743 A JPS61175743 A JP S61175743A
Authority
JP
Japan
Prior art keywords
data
circuit
read
error
rewriting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60015895A
Other languages
Japanese (ja)
Inventor
Akira Kato
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP60015895A priority Critical patent/JPS61175743A/en
Publication of JPS61175743A publication Critical patent/JPS61175743A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid the reduction of access time when no error is detected by reading out data corrected when an error is detected after rewriting it by hardware and transmitting the correction data with no rewriting in case the read-out data is still erroneous.
CONSTITUTION: When a memory error detecting circuit 13 detects a correctable error, a signal CTBLER is set at 1 and transmitted to a read/write control circuit 16. Then a read data transmission inhibiting signal DSINH is set at 1 to inhibit the transmission of the read data of a read data transmitting circuit 15. At the same time, the read data MRD and the check data CKD are supplied to a correcting circuit 14. Then the obtained correction data CD is stored in a write data register 11. When the writing is through with the data CD, the reading is carried out again. The circuit 13 detects errors again. If an error is detected again, the circuit 16 performs no rewriting and gives a command to the circuit 15 to transmit the data CD.
COPYRIGHT: (C)1986,JPO&Japio
JP60015895A 1985-01-30 1985-01-30 Memory control system Pending JPS61175743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60015895A JPS61175743A (en) 1985-01-30 1985-01-30 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60015895A JPS61175743A (en) 1985-01-30 1985-01-30 Memory control system

Publications (1)

Publication Number Publication Date
JPS61175743A true JPS61175743A (en) 1986-08-07

Family

ID=11901516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60015895A Pending JPS61175743A (en) 1985-01-30 1985-01-30 Memory control system

Country Status (1)

Country Link
JP (1) JPS61175743A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6339061A (en) * 1986-08-04 1988-02-19 Fujitsu Ltd Processing system for memory error

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6339061A (en) * 1986-08-04 1988-02-19 Fujitsu Ltd Processing system for memory error

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