JPS6156537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error recovery system for logical devices. An instruction retry method is one of the error recovery methods for a central processing unit (hereinafter abbreviated as CPU).

If an error occurs in the CPU while executing a certain instruction, in order to retry the instruction,
All the information related to the instruction in the CPU needs to be returned to the state before the instruction was executed, reproduce the state before the instruction was executed, and then re-executed.Basically, the programmable registers in the CPU This is a reproduction of the state of the device, the memory state, and the internal state of other devices.

For instruction retry, a copy register is provided for the programmable register so that the value before execution of each instruction is always retained, and if an error occurs while executing a certain instruction, the information in the copy register is By returning to the programmable register described above, it is possible to return to the state immediately before the instruction was executed. Furthermore, an instruction retry disabled indicator is provided to indicate whether or not an instruction can be retried. The instruction retryability indicator is set or reset depending on whether the instruction is retryable or not, and if it is extremely difficult to reproduce the state before the instruction is executed, such as when memory is rewritten during instruction execution, the instruction cannot be retried. Make sure to set the indicator.

Conventionally, when an error occurs during the execution of a certain instruction in a CPU that has the above-mentioned instruction retry means,
Whether or not the instruction can be retried is determined based on the contents of the instruction retry not possible indicator, and if the instruction can be retried, the CPU error is recovered by retrying the instruction. If the error is a fixed failure, there is a drawback that recovery from the error cannot be expected by retrying the instruction. Additionally, since the device containing the error basically performs its own recovery process, the recovery cannot be completed completely.
There is also a drawback.

The purpose of the present invention is to completely solve the disadvantages of a multiprocessor system, such as a decrease in the possibility of recovery from fixed failures and a decrease in the reliability of recovery results.
An object of the present invention is to provide an error recovery system for logical devices that can recover from errors in a CPU.

The system of the present invention is an error recovery system for a logic device that includes a plurality of logic devices and a recovery control device that controls error recovery operations of these logic devices. means, an error notification means for notifying an error that occurs when processing is performed based on the information in the storage means, a means for stopping execution after notification of the error, and an instruction that causes an error to be stopped by the stopping means. a plurality of logical devices having a sending means for sending display information indicating whether or not the command can be re-executed; and the error notification means notifying the error and displaying information from the sending means indicating that the command can be re-executed. When an error occurs, an evacuation grenade is used to evacuate the information group from the storage means of the logical device, and the information group evacuated to the evacuation means is sent to the storage means of the logical device in which the error does not occur among the plurality of logical devices. and a recovery control device having a control means for instructing re-execution from the instruction that has occurred.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to the figure, the error recovery device of the present invention includes a CPU 10 that detects an error, a CPU 20 that performs error recovery processing, a recovery control device 30 that controls error recovery processing, and a system for reporting errors in the CPU 10 to the recovery control device 30. Error reporting connection line 1
20, a saving connection line 121 for saving information of the programmable register group 111 to 119 of the CPU 10, the programmable register group 211 to 219 of the CPU 20, the programmable register group 111 to 119 of the CPU 10;
Programmable register group 11 of CPU 10
A recovery interface 222 for restoring the information of 1 to 119 to the programmable register group 211 to 219 of the CPU 20, and an error detection circuit 130 in the CPU 10 (realized by a conventional parity check circuit, etc.) , CPU10
The CPU 20 includes a clock oscillation circuit 131 within the CPU 20, a clock oscillation circuit 231 within the CPU 20, and an instruction retry disabled indicator 132.

Now, when an error occurs in the CPU 10 and the error detection circuit 130 detects the error, the control line 1
23, the clock oscillation circuit 131 is stopped and the CPU 10 at the time of the error occurs.
The internal state of the control line 124 is frozen, and the control line 124
An error occurrence report is then sent to the recovery control device 30 via the interface control circuit 133.
The recovery control device 30 is normally processing another task such as input/output control, but when an error occurrence report is given from the CPU 10, the control unit 31 of the recovery control device 30 interrupts the task being processed and starts the recovery process. control is started. That is, the contents of the programmable registers 111 to 119 of the CPU 10 are read via the save interface 121.

The read operation of the registers within the CPU 10 is performed as follows. That is, the data bus 13
7 is a data bus with a width of 36 bits, and the value of the register specified by the selection register 136 among registers 111 to 119 is set.Since the external interface is 9 bits, data is stored in the selection register 136 from the outside. Each time a read command is issued based on the register number to be read, the data on the data bus 137 is sent to the interface four times from the upper 9 bits via the selection gate group 138, and the value of the data bus 137 is read. I can do it. During the process of reading the programmable registers 111 to 119 of the CPU 10, the clock of the CPU 10 is stopped, and the read process
Make sure that the internal state of the CPU 10 does not change.

In the circuit control device 30, at the time of occurrence of the error,
Whether or not the instruction being executed by the CPU 10 can be retried is determined based on the contents of the instruction retryability indicator 132. The instruction retry prohibition indicator 132 is reset to OFF at the start of execution of each instruction, and is set to ON to indicate that the instruction cannot be retried under conditions such as memory rewriting during instruction execution. When the instruction retry not possible indicator 132 is off, the instruction at the time of the error occurrence can be retried, so a signal from the recovery control device 30 instructs the CPU 10 to retry the instruction. If the retry of the instruction by the CPU 10 is unsuccessful, the CPU 20 is requested to perform recovery processing for the CPU 10 via the control line 234.

The CPU 20 that has received a recovery request for the error CPU 10 from the recovery control device 30 is processing this task independently of the CPU 10, and the task being processed is interrupted at a good point, and the CPU 20 receives a recovery request via the control line 234. Report to the control device 30. After that, the clock oscillation circuit 231 is stopped, and the CPU 2
The main business process at 0 is temporarily suspended. However, if the recovery control device 30 can recognize that the CPU 20 is not processing this business, the CPU 20
There is no need for a report from to the recovery control device 30.

Upon receiving the report, the recovery control device 30 transfers the information of the programmable registers 111 to 119 of the CPU 10 that was saved via the save interface 121 to the recovery interface 222.
Programmable register group 21 of CPU 20
1 to 219.

Register writing to the CPU 20 is performed as follows. That is, data bus 235 is a 36-bit wide data bus, and registers 211 to 2
Data is set in the register designated by the contents of the selection register 236 among the 19 registers. The selection register 236 and data register 239 can be set externally, but since the external interface is 9 bits, it is necessary to set the data register 239 four times using the selection gate group 240. is set in the selection register 236, and written into the data register 239 in four parts of 9 bits each, and then written to a desired register by issuing a write command.

Programmable register group 1 of CPU10
After the information Nos. 11 to 119 is set to the programmable registers 211 to 219 of the CPU 20, the recovery control device 30 sends the information via the control line 225.
By canceling the clock oscillation stop of the CPU 20, the CPU 20 is activated to start an instruction, and the processing that was interrupted by the CPU 10 due to the error is continued by the CPU 20, and the recovery processing of the CPU 10 is performed.

The present invention has the advantage that CPU recovery processing can be performed without creating various recovery processing programs and without reducing the credibility of the recovery processing.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention. In the figure, 10, 20... CPU, 30...
Recovery control circuit, 31...control unit, 111-11
9,211-219...Register group, 120,2
20...Error reporting interface, 121,
221... Evacuation interface, 122, 22
2...Recovery interface, 123, 124,
125, 223, 224, 225...control line, 1
30,230...Error detection circuit, 131,23
1...Clock oscillation circuit, 132, 232...Instruction retry impossible indicator, 133, 233...
...Interface control circuit, 124, 224...
Control line, 135, 235...Write data bus,
136, 236...Selection register, 137, 23
7... Read data bus, 138, 238... Selection control gate group, 139, 239... Data register, 140, 240... Selection control gate group.

Claims (1)

[Scope of Claims] 1. In a logic device error recovery system having a plurality of logic devices and a recovery control device that controls error recovery operations of these logic devices, the system stores information details for reading and executing instructions. a storage means, an error notification means for notifying an error that occurs when processing is performed based on the information group of the storage means, a means for stopping execution after notifying the error, and a means for stopping the execution of the error that is stopped by the stopping means. a plurality of logical devices having a transmitting means for transmitting display information indicating whether or not the command can be re-executed; and a plurality of logical devices having a transmitting means for transmitting display information indicating whether or not the command can be re-executed; When displaying, a saving means saves the information group from the storage means of the logical device, and the information group saved to the saving means is stored at a break point between the processing of the logical device in which an error does not occur among the plurality of logical devices. 1. An error recovery system for a logic device, comprising: a recovery control device having a control means for instructing a storage means of the logic device to re-execute an instruction in which a sending error has occurred.