JPS5932821B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a retry function in the event of a hardware malfunction.

In recent years, the scale of information processing equipment has progressed, and as a result, the probability of hardware malfunctions has increased.
A problem has arisen in that its reliability is reduced.

In order to solve this kind of problem, hardware malfunction detection circuits are installed everywhere to monitor hardware malfunctions, and to ensure that detected hardware malfunctions are temporary rather than fixed malfunctions. Even if the malfunction is fixed, it only occurs at a specific timing, and it is possible to predict that it will be executed normally if executed at a different timing. Saving by execution (retry) is done.

However, in the past, this retry was performed on an instruction-by-instruction basis, and the following method was used.

The first method is to provide a retryable/impossible indicator bit to determine whether the point at which a malfunction is detected is within a retryable range or an impossible range, and the If one of a plurality of pieces of information that must be updated by the instruction among the instruction address, instruction word, operand word, and other initial information is updated, it is registered in the retry possible/impossible indication bit.

When a hardware malfunction is detected, this bit is checked, and if it is not registered, a retry is performed, and if it is registered, a retry is not performed. The second method is to provide a save means (save register) that holds multiple pieces of initial information necessary for instruction execution, and save and hold the initial information in the save register before or during instruction execution to prevent malfunctions. In this case, the method is to restore all or only the necessary information held in the save register and retry the instruction from the beginning or in the middle of execution.

However, although the first method requires only a small amount of hardware for retrying, it has the disadvantage that the time range in which retrying is possible is narrow, and the second method requires updating with the instruction. Even if a malfunction occurs after updating one of the multiple pieces of information that must be updated, or if the malfunction occurs immediately before the update and the update cannot be suppressed and the update is performed with incorrect data, the information before the update will be updated. It has the advantage that it can be retried because it is held in the save register, and the retry range is wide, but it requires a large amount of hardware for retrying, and the control for retrying is very difficult. The drawback was that it was complicated.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional instruction-based retry technique. Therefore, an object of the present invention is to use a buffer memory controlled by a swap method. , by performing process-specific retries, without the need for special save registers.
It is an object of the present invention to provide a new information processing device that can have a wider range of retry than the conventional retry of each instruction by using a small amount of hardware and simple control.

The present invention includes a main memory section that stores instructions, data, and operating environment information, a buffer memory that transfers data between the main memory section and the main memory section by a swap method, and a buffer memory that transfers data between the main memory section and the main memory section by a swap method. one or more registers that store operating environment information stored in the register; a malfunction detection circuit that detects any malfunction when executing one process based on the operating environment information stored in the register; Process retry display means for displaying that retry is possible at the start of execution of the process, and for displaying that retry is not possible when data is written to the main storage device during execution of the process. When a malfunction is detected by the malfunction detection circuit, if the process retry display means indicates that retry is possible, at least all data stored in the buffer memory is invalidated, and the process is restarted. The process is retried from the beginning, and if no hardware malfunction is detected by the malfunction detection circuit, the operating environment information and data stored in the register are stored in the main memory at the end of the process. An information processing device is configured.

A program executed by the information processing device of the present invention is divided into a plurality of hardware-visible work units, that is, processes, and each process synchronizes or exchanges messages with other processes as necessary. , in principle, is processed independently from other processes.

Hardware visibility also means that each individual process has information blocks (e.g. general registers, base registers, instruction counters, program/hardware masks, etc.) that define the operating environment when they are executed on the central processing unit. timers, etc. (hereinafter referred to as process control blocks) are stored in the main memory, and when a process is given the central processing unit and is allowed to execute, the hardware writes to the process control block. The specified operating environment information, that is, the initial state is transferred to the central processing unit, the operating environment for starting the execution of the process is defined on the central processing unit, and then the execution is started and the execution is terminated or interrupted. When the central processing unit is handed over to another process, the operating environment at the time of termination or interruption, that is, the execution result, is returned to the process control block (main memory), so that the process is executed discontinuously in time. However, the execution results are controlled to ensure continuity. Further, the information processing apparatus of the present invention has a buffer memory device that is swap-controlled in accordance with processes.

When this buffer memory device receives an access request from the central processing unit, it checks whether the specified information is registered on the buffer memory, and if it is registered, the specified information is targeted only for the information on the buffer memory. Processing (reading, writing, etc.) is performed, and if the specified information is not registered in the buffer memory, the exact amount of data (called a program) containing the specified information is read (swapped in) from the main memory and transferred to the buffer memory. After registering the specified information in the buffer memory, the specified processing is performed only on the specified information on the buffer memory. That is, at this point, the information on the main memory is not updated at all. When registering a program read from the main memory in the buffer memory, if there is no free space in which to register the program and the program is replaced with previously registered and outdated information, the old information cannot be written to the buffer memory. If the block has been written to the main memory (swap out), if the block has not been written to the main memory, it is rewritten with a new block. As a result of this swapout to main memory,
The information on the main memory will be updated. Furthermore, when one process yields the central processing unit to another process,
In addition to returning the operating environment to the process control block of that process in main memory, it also checks and writes to all the programs in buffer memory related to that process to see if any writing was done during the execution of that process. Swap out the completed program to main memory. That is, by transferring the final result of execution up to that point to the process control program and process on the main memory, the initial state when the process is executed again is created on the main memory. By controlling as described above, when a central processing unit is assigned to a certain process and the central processing unit reads out the process control program for that process from main memory and starts execution, a swap-out occurs from the buffer memory to the main memory. Until then, the state on the main memory before the start of execution of the process, that is, the initial state is held.

As mentioned above, in an information processing device that has a buffer memory whose slip is controlled according to the process, it is possible to retry the process to determine whether it is possible or impossible to retry the process being executed. When the program related to the process being executed is swapped out from the buffer memory to the main memory and the initial state in the main memory is updated, the above-mentioned retryable/impossible indicator bit is set to indicate that retrying is not possible. register.

Thus, an information processing apparatus is provided which is characterized in that when a hardware malfunction is detected, this bit is checked and if the bit is not registered, the process is retried. Next, the structural action and effects will be explained in detail with reference to the drawings showing one embodiment of the present invention.

FIG. 1 is a diagram showing the configuration of a main memory in an information processing apparatus according to the present invention.

As mentioned earlier, programs executed by this information processing device are divided into independent processing units called processes, and multiple processes can be multiplexed in time by synchronizing and exchanging messages between multiple processes as necessary. It is processed.

All of these processes are given process names JnPn, and by indexing the J table and the P table using the process name JnPn, a process control block can be obtained as shown in FIG. This process control block has an area for writing all of the program visible registers and masks that the central processing unit has, and each area has an area for writing all the program visible registers and masks that the central processing unit has. It holds the values of each register and mask at the time when execution of the first instruction in the specified process starts. This information indicates the initial state of the process. When a central processing unit is given to one process and execution of that process is started, the contents of the control block described above are transferred to the corresponding register of the central processing unit, and execution starts from the first instruction specified by the instruction counter. When the execution of the process is started, or when the execution of the process is terminated or interrupted, after the execution of the last instruction is completed, the information in the central processing unit is returned to the process control block in the main memory.

Therefore, even if a process hands over the central processing unit to another process, the process control block ensures continuity of the process. FIG. 2 is a main part block diagram showing an embodiment of the information processing apparatus according to the present invention.

In the figure, operation register group 1 consists of program-visible registers (general-purpose registers, base registers, scientific operation registers, instruction counter, stack pointer, masks) and hardware necessary for executing instructions. Consists of a group of operational registers.

In addition, the arithmetic circuit group 2 performs address calculations necessary for executing instructions.
It consists of a group of arithmetic circuits that perform operations such as shift, addition and subtraction, multiplication and division, and executes instructions according to instructions from the instruction register 3. When information on the memory is required in the process of executing an instruction, the address on the main memory of the information is set in the address register 4, and when the information on the memory needs to be updated,
The address of the information is set in the address register 4, and the update information is set in the write data register 5, and a read/write access request is made to the memory system.

The memory system includes a directory 6, a buffer memory 7, a main memory address 8, a read data register 9, and a main memory 10.
The directory 16 holds addresses on the main memory of information blocks registered in the buffer memory and a rewriting display bit W indicating that the information has been updated on the buffer memory.

The malfunction detection circuits 11, 12, 13, 14, and 15 are arithmetic register group 1, arithmetic circuit group 2, instruction register 3, and
This circuit mainly detects malfunctions of the address register 4 and write data register 5 using a parity check method, and when malfunction detection is reported by these output signals or the malfunction detection signal 17 of a circuit other than the above. A malfunction holding circuit 16 consisting of a group of flip-flops holds the error.

Output line 18 of malfunction holding circuit 16 (malfunction holding circuit 1
This is the logical OR of all 6 flip-flops. First, the operation of the instruction execution system consisting of circuits 1, 2, 3, 4 and 5 will be explained.

When a central processing unit is given to a process and its execution starts, first the process control program for the process obtained as shown in Figure 1 is calculated based on the specified process name JnPn. Read to the specified register in register group 1.

A process name is given by one register in arithmetic register group 1, an address is calculated by arithmetic circuit group 2, the result is set in address register 4, and an access request for reading is sent to the memory system. When the reading in the memory system is completed, the read data is sequentially read out to the designated register of the operation register group 1 via the read data register 9. This operation is repeated until all process control blocks are read out. When all the process control blocks in the memory system have been read into the arithmetic register group 1, execution of the process is started.

First, an instruction address is read from the instruction counter register in the arithmetic register group 1, set in the address register 4 through the arithmetic circuit group 2, and an access request for reading the instruction is issued to the memory system. When an instruction word is read into the memory read data register 9, the instruction word is set in the instruction register 3. If memory access is required according to the instructions of the instruction word set in the instruction register 3, the address of the operand word is calculated by the arithmetic circuit group 2, and the result is stored in the register specified by the hardware of the arithmetic register group 1 (
If an operand word for an operation needs to be read from the memory system, it is also set in the address register 4, and an access request for reading is sent to the memory system. Send out. If an operand word for executing an instruction is required, it is read from the memory system, and when it is read from the register specified by the instruction in the operation register group 1, the operation specified by the instruction register 3 is executed by the operation circuit group 2. Execute. The execution result is stored again in the register specified by the instruction in the operation register group 1, or written to the address register 4 from the operand address register in the operation register group 1 via the write data register 5. It is sent as an access request for writing to the memory system along with the write address. When the execution of one instruction is completed in this way, the instruction counter register in the operation register group 1 is updated according to the word length of the instruction, and execution of the next instruction is started. While executing the instructions in the above-mentioned iterations, when the process terminates execution or yields the central processing unit to another process by interrupting, the main processor that is kept in the state before the process started execution is The relevant information in the operation register group 1 is transferred (written) to the process control block in memory.

Next, the operation of the memory system consisting of circuits 6, 7, 8, 9 and 10 will be explained.

First, when an access request for reading is received from the instruction execution system, the directory 6 is indexed based on the contents of the address register 4.

If a matching address exists as a result of the index, a program containing the relevant data is registered in the buffer memory corresponding to that directory, so the data is read from that program to the data register 9, and the process is terminated by the instruction execution system ( reply). If there is no matching address in the directory 6, the data is not registered on the buffer memory, and the program containing the data is read out from the main memory 10 to the buffer memory. At this time, the read address is set in the main memory address register 8 from the address register 4 and sent to the main memory. When the corresponding block is read from the main memory, it is registered in the corresponding entries of the buffer memory 7 and the directory 6 along with the contents of the address register 4, and the necessary data from the registered block is read into the read data register 9 and the instruction is executed. Notify the system of termination. Also, when an access request for writing is received from the instruction execution system, the directory 6 is indexed in the same way as a read request, and if there is no matching address, the corresponding program is read from the main memory, and the corresponding program is stored in the buffer memory 7 and directory 6. Register a program.

When the updated data is registered in the buffer memory 7, only the data on the buffer memory 7 is updated and the rewriting display bit W of the corresponding directory 6 is set to 1. As mentioned above, regardless of whether the access request from the instruction execution system is for reading or writing, if the corresponding data is not registered in the buffer memory 7, the program containing the corresponding data is read from the main memory 10 to the buffer memory 7. There is.

If there is an area on the buffer memory 7 for registering this newly read out program from the main memory 10, it is registered in that area, but if there is no area, it is replaced with a previously registered and outdated program. At this time, we check the rewritten bit W of entry 1 of directory 16 corresponding to the old program and if it is ``1'5, this means that the program has been rewritten while the buffer memory existed and is already different from the contents of main memory. The program must be transferred to the main memory.The write address is set from the directory 6 to the main memory address register 8, the write data is set from the buffer memory 7 to the write data register 9, and the program is transferred multiple times. The buffer memory control method described above is a so-called general swap method, but the buffer memory in the present invention must be under swap control.

That is, when a running process hands over the central processing unit to another process, it scans all entries in the directory 6 and transfers all the programs whose rewrite display bit W is set to 1 to the main memory in the same way as above. and rewrite display bit W
Set to O. In this way, the rewrite display bit W on the process control block and buffer memory is set to 1.
When all of the processes in the main memory have been transferred to the main memory, the processes in the main memory are in a consistent and final state.

Next, in order to explain the effects of the present invention, we will use 2 to 3 instruction types as examples, and first explain how the conventional retry technique for each instruction expands the retryable range using Figure 3. After that, FIG. 4 shows how the structure has been changed according to the present invention.

First, we will discuss a type in which a general-purpose register designated by an instruction word and data in main memory are operated on and the result is stored in the same general-purpose register. In FIGS. 3 and 4, when this instruction starts to be executed, the general-purpose register read address register 35 and the general-purpose register write address register 36 are set to the general-purpose register designation part after the instruction. One word of the general-purpose register specified by the general-purpose register read address register 35 is read into the register 30. Around this time, the data on the main memory specified by the address section of the instruction section is read into the register 31. When the two data are read together and set in the corresponding registers, the arithmetic circuit (performs four arithmetic operations, logical operations, etc.) executes the specified operation and sets the result in the register 33. do. Next, the operation result of the register 33 is written into one word of the general-purpose register 34 specified by the general-purpose register write register 36, and the execution of this instruction is completed. Also circuits 37, 38, 3
9, 40, 41 and 42 are registers 30 and 31, respectively.
, 33, 34, 35, and 36, and the results are reported to all the parts that perform fault processing. Conventionally, when the fault processing unit is notified of the detection of a fault, the 0R circuit 43 first performs a logical sum, and the display bit flip-flop 4
4 to 1, then stop the machine clock and initialize the central processing unit (excluding registers visible to the program) to interrupt execution of this instruction, and then execute again from fetching this instruction. I'll have to fix it. At this time, since there is a time delay of one machine cycle or more from the time a failure is detected until execution is interrupted, if a failure is detected in the register 33 and write address register 36 that are written to the general-purpose register, an interruption instruction from failure processing is issued. If this were to be relied on, incorrect contents would be written to the general-purpose register 34, making it impossible to retry. Therefore, NOR circuit 45 and AN
Due to the D circuit 46, the results of the fault detection circuits 39 and 42 are both normal, and the display bit flip-flop 4
When 4 is O, a write pulse 47 from the control section is input to the general-purpose register 34. In addition, if a fault is detected before register 33 as described above, general-purpose register 3
If the register 33 is normal but the write to the general-purpose register 34 is not executed correctly, that is, after the check point of the failure detection circuit 39, the general-purpose register 34 In the case of a failure in the path to the memory element itself or in the memory element constituting the general-purpose register 34, the failure will be detected when the corresponding word is read by the subsequent instruction. No data is left and retry is not possible, or retry must be unsuccessful.

However, according to the method of the present invention, since the initial value of the process is stored in the main memory, in the event of a failure, it is possible to retry without any problem by reloading the process unit from the main memory. There is no need to store the initial values in the central processing unit correctly at the time of detecting a failure, just by monitoring whether or not it has been done correctly.

Therefore, as shown in FIG.
The circuit 46 is unnecessary, and if the fault in the general-purpose register 34 itself is an intermittent fault, the retry will be successful. Second, consider an instruction that loads data from main memory into multiple words of a general-purpose register.

In this case, if an attempt is made to retry each instruction without providing any special circuit, retrying will not be possible after the first word is loaded. Therefore, the ability to retry loading one word at a time or the method of saving the words to be loaded in advance is taken. The former does not require much additional hardware, but requires very complex control when considering speeding up pipeline control, etc., and the latter is a general-purpose system where a save register is loaded, such as register 48 in Figure 3. The number of words in the register or (the number of words in the general-purpose register to be loaded - 1) is required, resulting in an increase in hardware. When the general-purpose register 34 is rewritten, the register 48 in FIG. This register is used to rewrite the corresponding word in the general-purpose register 34 via the register 33 and return it to its original state, and usually requires a plurality of words.

However, as described above, since the initial values of all processes are stored in the main memory, as shown in FIG. 4, the system of the present invention does not require any of the above-mentioned save registers. Third, considering a type of instruction that operates on data in main memory and stores the result in main memory, that is, a variable length instruction, the first main In order not to be unable to retry even after memory rewriting, it is necessary to have a save register, but it is generally very long (
For example, since there are many instructions that can handle data (256 bytes), a large amount of hardware is required for the save register, so complex control such as enabling retry at appropriate processing intervals is required. will be done.

In this case, as a matter of course, according to the method of the present invention, no hardware is required for any special processing other than detecting a fault.

FIG. 5 is a diagram illustrating the main part of the present invention.

From the figure, bit 19 indicates whether or not a process can be retried.
is set to O by the signal line 22 which becomes ``1'' immediately before starting to transfer the process control block to the arithmetic register group 1 at the start of execution of the process, and is set to O by the signal line 22 which becomes ``1'''' during the execution of the process. When registering a new program in entry 1 where the write display bit W of 6 is set to ``1'', when the old program is transferred to the main memory, the signal line 21 which becomes ``1'' and ``5'' sets the write display bit W to ``3'' to ``5''. Therefore, while retryable/unable indicator bit 19 is set to 'O', all information in main memory regarding the process that is about to start execution or is currently being executed (the process control program) is and all of the program) remain in the state they were in before execution started.

A hardware malfunction has now been detected within the information processing device.
When a malfunction is registered and held in the malfunction holding circuit 16, its output signal line 18 is ANDed with the output signal line of the retry possible/impossible display bit 19 in the AND circuit 20.

If the resulting output signal 23 becomes ``1'''', it indicates that the process can be retried regarding the malfunction, and the process retry control circuit is activated. As explained above, the present invention uses a buffer memory that performs process-based swap control, and is configured to enable execution while maintaining the process in main memory in the state up to the start of execution. This method has the effect of allowing a wide range of retrials to be performed using a relatively small amount of hardware and simple control.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a state in which a program executed by an information processing device according to the present invention is stored in the main storage device, and FIG. FIG. 3 is a diagram illustrating the configuration of an example of the prior art, and FIG. 4 is a configuration diagram of an embodiment of the present invention corresponding to FIG. FIG. 5 is a diagram showing essential parts of one embodiment. 1... Arithmetic register 2... Arithmetic circuit group, 3... Instruction register, 4... Address register, 5... Write data Register, 6...Directory, 7...Buffer memory, 8...Main memory address register,
9... Read data register, 10...
・Main memory 11, 12, 13, 14, 15...
Malfunction detection circuit, 16... Malfunction holding circuit, 1
9... Retry possible/impossible display bit, 20.
...AND circuit, 30...General-purpose register read data register (operand), 31...
・Register for read data from main memory (operand)
, 32...Arithmetic circuit, 33...Arithmetic result storage register and general-purpose register write data register, 34...General-purpose register, 35...
General-purpose register read address register, 36...
General-purpose register write address register, 45...
Save register, 37, 38, 39, 40, 41, 42
, 46...fault detection circuit, 43...N
OR circuit, 44...AND circuit.

Claims (1)

[Claims] 1 A main memory section that stores instructions, data, and operating environment information constituting a process; a buffer memory that transfers data to and from the main memory section using a swap method for each process; one or more registers that retrieve and store operating environment information stored in the storage unit from the main storage unit and that are updated as the process is executed;
1 based on the operating environment information stored in this register.
A malfunction detection circuit detects any malfunction when executing a process, and displays that a retry is possible at the start of execution of the process, and the initial data and operating environment information in the main memory are rewritten while the process is executed. a process retry display means for displaying that a retry is not possible when a malfunction is detected by the malfunction detection circuit;
If the process retry display means indicates that retry is possible, invalidate all data stored in the buffer memory and operating environment information set in the register, and re-execute the process from the beginning; When the malfunction detection circuit terminates or interrupts execution of a process without detecting a hardware malfunction, the operating environment information set in the register and the data on the buffer memory are finally stored in the main memory. An information processing device characterized by: