JPS61202254A - Memory device - Google Patents

Abstract

PURPOSE:To attain a diagnosis in both an error check circuit and a correction circuit by securing an exclusive AND between a syndrome registered previously and a produced syndrome. CONSTITUTION:A memory device is provided with a syndrome generating circuit 6, a syndrome register 24, an error check circuit 10, an AND gate 25, a comparator 26, a selector 22, a decoder 7 and a correction circuit 8. The circuit 6 produces a syndrome with read data and check bits. This syndrome is registered on a syndrome register 24. An AND gate 25 secures an AND between an uncorrectable error given from the circuit 10 and the syndrome given from the register 24. Then a comparator 26 obtains an exclusive AND between the output of the gate 25 and the syndrome produced by the circuit 6. Then the read data is corrected by the output of the exclusive AND through the circuit 8.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a storage device having a 5EC-DBD code,
In particular, it relates to diagnosis of read error check circuits and correction circuits.

(Prior Art) FIG. 2 is a block diagram showing an example of a storage device according to the prior art. In Figure 2, 1.5.9 are data registers, 2 is a check bit generation circuit, 3 is a check bit generation inhibit register, 4 is a memory matrix circuit, 6 is a syndrome generation circuit, 7 is a decoder, and 8 is a correction circuit. , 10 is an error check circuit.

In FIG. 2, when the one-bit error check circuit 10 and correction circuit 8 are diagnosed by a program, the operation is as follows. First, the check bit generation prohibition register 3 is set to @1'' so that all check bits become @0'' when writing data. For example, the 8-bit data on signal line 12 is @10000000''
It is written to the memory matrix circuit 4 as .

Assuming that check bit generation follows the 8EC-DED code shown in FIG. 3, the check bit on signal line 14 is @
However, since the contents of the check bit generation prohibition register 3 are @1#, all check bits on the signal line 14 are @0''. Next, read the data and check bits from the memory matrix circuit 4 onto the signal line 15! . At this time, the data is “1000oo
Since the check bit is “00000”, the syndrome on the signal line 17 is @11100”. Therefore, the error check circuit 10 detects a 1-bit error, and the decoder 7 detects the data bit D.
The bit error in O is decoded and corrected by the correction circuit 8.

Therefore, all bits of data on signal line 20 are "0".
It is #. Similarly, the write data on signal line 12 is @0
1000000", "00100ooo',...@
00000001'', the error check circuit 10 and correction circuit 8 can be corrected.

However, if the data read from the memory matrix circuit 4 onto the signal line 15 contains a 1-bit error,
An uncorrectable error will occur.

For example, when data bit D7 has a 1-bit error, when the error check circuit 10 and correction circuit 8 of data bit DO are diagnosed, read data on signal line 15 and check bit bar 10000001'' and @00000m are detected. Therefore, from FIG. 3, the syndrome on the signal line 17 is @10001'', and an uncorrectable error can be detected.

(Problems to be Solved by the Invention) When attempting to diagnose a read data error check circuit or a 1-bit error correction circuit of a storage device having an 8EC-DEC code using a diagnostic program, it is difficult to detect a 1-bit error in the read data. There is a drawback that a diagnostic test results in an error even though there is no failure in the error check circuit or the 1-bit error correction circuit.

An object of the present invention is to register syndromes of 1-bit errors that occur during normal diagnosis other than diagnosis of error check circuits and 1-bit error correction circuits, and to register syndromes that cannot be corrected when diagnosing error check circuits and 1-bit error correction circuits. If it is an error, calculate the exclusive OR of the uncorrectable error syndrome and the registered syndrome, and send this exclusive OR signal to the error check circuit and
To provide a storage device which solves the above-mentioned drawbacks by using a bit error correction circuit syndrome and is configured so that even if a 1-bit error occurs in data, the error check circuit and 1-bit error correction circuit can be diagnosed. It is in.

(Means for Solving the Problems) A storage device according to the present invention includes a syndrome generation circuit, a syndrome register, an error check circuit, an AND gate, a comparison circuit, a selector, a decoder, and a correction circuit. , executes write/read operations in response to write/read instructions from an external arithmetic processing unit, and 8EC-D
The configuration is such that when a 1-bit error occurs in read data having an ED code, a diagnostic test of the read data can be performed on the error check circuit and the correction circuit.

The syndrome generation circuit is for generating a syndrome using read data and check bits.

The syndrome register is for registering the syndrome generated by the syndrome generation circuit.

The error check circuit is for checking read data based on syndromes from the syndrome generation circuit.

The AND gate is for performing a logical product between the uncorrectable error from the error check circuit and the syndrome from the syndrome register.

The comparison circuit is for comparing the output of the AND gate and the syndrome from the syndrome generation circuit and calculating exclusive OR.

The selector is for selecting the output of the comparison circuit or the syndrome output from the syndrome generation circuit.

The decoder is for decoding the signal selected by the selector.

The correction circuit is for correcting read data using the output signal of the decoder.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. In Fig. 1, 1°5.9 are data registers, 2 is a check bit generation circuit, 3 is a check bit generation prohibition register, 4 is a memory matrix circuit, 6 is a syndrome generation circuit, 7 is a decoder, and 8 is a correction circuit. , 10I is an error check circuit, 22 is a selector, 24 is a syndrome register, 25 is an AND gate, and 26 is a comparison circuit.

This embodiment will be described in detail below with reference to FIG. 1 and FIG. 3 showing the 8EC-DED code.0 Prior to diagnosis of the read data error check circuit 10' and the 1-bit error correction circuit 8. , perform write/read operations. In this diagnostic operation, for example, if there is a 1-bit error in data D7 among the 8 bits shown in FIG. 3, a syndrome @01101'' is registered in the syndrome register 24.

Next, the error check circuit 10' and the correction circuit 8 are diagnosed. First, set check bit generation prohibition register 3 to 1.
11 so that all check bits on signal line 14 become @0# when writing data. For example, the 8-bit data on signal line 12 is @100000.
00'' and is written to the memory matrix circuit 4.

Next, the data and check pits sent from the memory matrix circuit 4 to the signal line 15 are not read out. At this time,
If there is a 1-bit error in data D7, the data will be ``10''.
000001” and the check pit is “ooooo
' becomes.

Therefore, the syndrome on signal line 17 is "10001"
and the error check circuit 10 via the selector 22
' and generates an uncorrectable error signal on signal line 30. When the uncorrectable error signal on the signal line 3o is '1'', the signal from the syndrome register 24 on the signal line 31 is
The syndrome thus sent out is input to the comparison circuit via the AND gate 25, and the exclusive OR of this syndrome and the syndrome on the signal line 17 is determined.

That is, the syndrome on the signal line 31 is
1”, and the syndrome on signal line 17 is “1000”.
1", the syndrome output from the comparator circuit 26 onto the signal line 33 is ``11100''. The syndrome on the signal line is selected by the selector 22 and input to the error check circuit 10' and decoder 7. The error check circuit 10' detects a 1-bit error,
signal! Generates a 1-bit error signal on 21. Also,
The decoder 7 decodes the 1-bit error in the data Do, the correction circuit 8 corrects the data on the signal line 16, and the signal $2
The data above 0 is “ooooooo.

O".Other data bits can be diagnosed in the same way.

Here, in the above embodiment, when the data D7 is registered in the syndrome register 24 and the data on the signal line 12 is written as @00000001' when diagnosing the error check circuit 10' and the correction circuit 8, the signal Since the syndrome on the line 17 is "01101", the uncorrectable error signal also becomes "0", and the syndrome on the signal line 33 also remains unchanged at "01101". Also, signal line 1
Similarly, even when the data on signal line 17 is other than "@ooooooooi" and a 1-bit error does not occur in data D7, the syndrome on signal line 17 and the syndrome on signal line 33 remain the same.

(Effects of the Invention) As described above, the present invention provides a memory device having a 5BC-DED code and capable of diagnosing an error check circuit and a correction circuit for read data. Even if a 1-bit error occurs during testing, the error check circuit and correction circuit can be diagnosed by using exclusive logic between the syndrome registered in advance and the syndrome that has occurred. It has the effect of improving the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. FIG. 2 is a block diagram showing an example of a storage device according to the prior art. I! FIG. 3 is an explanatory diagram showing the 8EC-DED code used in the storage device. 1.5.9...Data register 2...Check bit generation circuit 3...Check bit generation prohibition register 4...Memory matrix circuit 6...Syndrome generation circuit 7...Decoder 8... Correction circuit 10.1
0'...Error check circuit 22...Selector

Claims (1)

[Claims] a syndrome generation circuit for generating a syndrome from read data and a check bit; a syndrome register for registering the syndrome generated from the syndrome generation circuit; and a syndrome generation circuit for detecting a read data error from the syndrome from the syndrome generation circuit. an error check circuit for checking, an AND gate for taking an AND between the uncorrectable error from the error check circuit and the syndrome from the syndrome register, and an output of the AND gate and the syndrome generation circuit. a comparison circuit for comparing with the syndrome from the above and calculating an exclusive OR; a selector for selecting an output of the comparison circuit or the syndrome output from the syndrome generation circuit; and a selector for selecting the syndrome output from the syndrome generation circuit. a decoder for decoding the signal selected by the decoder, and a correction circuit for correcting the read data using the output signal of the decoder,
When a write/read operation is executed in response to a write/read command from an external arithmetic processing unit, and a 1-bit error has occurred in the read data having the SEC-DED code, the diagnostic test of the read data is performed on the error check. A storage device characterized in that it is configured to be able to perform the correction on a circuit and the correction circuit.