JPH0117181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer failure detection method for preventing computer malfunctions and uncontrolled states, and is intended to promptly detect abnormalities in control signals.

Conventionally, electronic computers (hereinafter referred to as computers) are
A control device, ie, a bus master, such as a central processing unit (hereinafter referred to as CPU), and peripheral devices such as memory and input/output interfaces are connected by a bus line, which is an information transmission path.

For example, a microcomputer with multiple bus masters, as shown in Figure 1,
The first to Nth bus masters 1a to 1n, the decoder 2a of the memory 2, and the decoder 3a of the input/output interface 3 are connected to the address bus 4a, data bus 4b, and control bus 4 of the bus line 4.
For example, when the bus master 1a reads data from the memory 2, the bus master 1
A first control signal Sa of logic 1 (hereinafter referred to as "1") is generated at the bus master 1a, and an address signal is sent from the bus master 1a to the decoder 2a of the memory 2 via the address bus 4a, as shown in FIG. 2a. A.D.
Further, as shown in FIG.
(hereinafter referred to as “0”) read control signal RCm
is output and the data at the specified address in memory 2 is
Reading of the DT is commanded, and as shown in FIG.
A second control signal, that is, a response signal XK of "0" is output from the bus master 1a via the response line xm and the control bus 4c, and the response signal XK
During the output period, data DT at a predetermined address read from the memory 2 is taken into the bus master 1a via the data bus 4b. Note that when another bus master, for example, the bus master 1n, reads out the data DT in the memory 2, the first control signal Sa is generated in the bus master 1n, and the data DT in the memory 2 is read out by the bus master through the same operation as described above. 1n.

Next, for example, when the bus master 1a writes data DT to the memory 2, the first control signal is sent to the bus master 1a while the memory 2 is being accessed by the bus master 1a, similarly to when reading the data DT from the memory 2. As the signal Sa occurs, as shown in Figure 3a, the bus master 1a
An address signal AD is output from the bus master 1a to the decoder 2a via the address bus 4a, and as shown in FIG. A control signal is output to instruct writing of data DT to a predetermined address in the memory 2, and as shown in FIG. During the data input/output enabled period of 2, a response signal XK is output from the decoder 2a to the bus master 1a via the response line xm and the control bus 4c, and during the output period of the response signal XK, the data output from the bus master 1a is
DT is written to a predetermined address in the memory via the decoder 2a. Note that data is stored in memory 2 by another bus master, for example, bus master 1n.
When writing DT, the first control signal Sa is generated in the bus master 1n, and the data DT output from the bus master 1n is
is written to memory 2.

Further, for example, when reading the data DT of the interface 3 to the bus master 1a, the first control signal Sa is generated to the bus master 1a while the interface 3 is accessed by the bus master 1a via the bus line 4. With,
As shown in FIG. 4a, the address signal AD is output from the bus master 1a to the decoder 3a via the address bus 4a, and furthermore, as shown in FIG.
c, decoder 3a via read control line ri
A read control signal RCi of “0” is output to instruct the interface 3 to read data DT at a predetermined address, and as shown in FIG. As shown in Figure d, during the input/output enabled period of the interface 3, a response signal XK is output from the decoder 3a to the bus master 1a via the response line xi and the control bus 4c, and during the output period of the response signal XK, the interface Data DT at a predetermined address read from the ace 3 is taken into the bus master 1a. Note that when another bus master, for example, the bus master 1n, reads the data DT of the interface 3, the first control signal Sa is generated in the bus master 1n, and the same operation as described above causes the bus master 1n to read the data DT of the interface 3. data DT is imported.

For example, when the bus master 1a writes data DT to the interface 3, while the bus master 1a accesses the interface 3, the first control signal Sa is generated to the bus master 1a, and the first control signal Sa is generated as shown in FIG. As shown in FIG. 2, an address signal AD is output from the bus master 1a to the decoder 3a via the address bus 4a, and further, as shown in FIG. A write control signal WCi is output to the decoder 3a to instruct writing of data DT to a predetermined address of the interface 3, and as shown in FIG.
DT is output, and as shown in Figure d, a response signal XK is output from the decoder 3a to the bus master 1a via the response line xi and the control bus 4c during the input/output enabled period of the interface 3. During the output period of signal XK, data DT on data bus 1a is written to a predetermined address of interface 3 via decoder 3a.
Note that other bus masters such as bus master 1
Also when writing data to the interface 3 using n, the first control signal Sa is sent to the bus master 1n.
occurs, and the data DT output from the bus master 1n is written to the interface 3 by the same operation as described above.

That is, each bus master 1a to 1n stores data in the memory 2 and interface 3.
When reading and writing DT,
While each of the bus masters 1a to 1n accesses the memory 2 and the interface 3 via the bus line 4, each of the bus masters 1a to 1n
A first control signal Sa is generated for each of the memory 2 and interface 3, and commands the memory 2 and interface 3 to read the data DT during the output period of the first control signal Sa, which is while the memory 2 and interface 3 are being accessed. When, each bus master 1a
Read control signals RCm and RCi are output from each of bus masters 1a to 1n along with address signals AD, and when commanding writing of data DT to memory 2 and interface 3, each bus master 1a
Write control signals WCm, WCi are output from each of ~1n along with address signal AD, and data from memory 2 and interface 3 is controlled by read control signals RCm, RCi, which are third control signals, and write control signals WCm, WCi, respectively. DT output and input are commanded, and memory 2 and interface 3 each receive data DT.
During the data input/output enabled period in which input and output are possible, the second
A response signal XK, which is a control signal, is output, and data DT is read and written during the output period of the response signal XK. Note that the same applies to reception of interrupt vectors.

By the way, the first control signal Sa, each control signal RCm,
Since the operation timing of each bus master 1a to 1n, memory 2, and interface 3 is controlled by RCi, WCm, WCi and response signal XK, each control device
When RCm, RCi, WCm, and WCi are not output to the memory 2 or interface 3 and the response signal XK is not output to the bus masters 1a to 1n, or during a non-output period when the first control signal Sa is not output. , each control signal RCm, RCi, WCm, WCi is output to the memory 2 or interface 3, and the response signal XK is output to the bus masters 1a to 1n, that is, the control signal via the bus line 4 If any abnormality occurs, normal operation will no longer be possible.

For example, when reading the data DT of the memory 2, if the circuit for the read control signal RCm provided on the bus line 4 fails and the read control signal RCm of "0" continues to be output to the memory 2 regardless of the control, The data DT of the memory 2 is output to the data bus 4b regardless of the accesses of the bus masters 1a to 1n, causing the computer to malfunction or run out of control.

Conversely, the circuit for the read control signal RCm mentioned above breaks down, the read control signal RCm is no longer output to the memory 2, and the read control line rm becomes "1".
response signal XK from memory 2.
is no longer output, and the bus masters 1a to 1n that have accessed the memory 2 are kept in a standby state waiting for the input of the response signal XK.

In addition, the circuit for response signal XK of bus line 4 has failed, and bus master 1a accessing memory 2
Even when the response signal XK is no longer output to bus masters 1a to 1n, the corresponding bus masters 1a to 1n are held in a standby state.

Therefore, if an abnormality occurs in the control signal due to a malfunction, the abnormality in the control signal is promptly detected and proper fault repair is carried out to prevent the occurrence of secondary failures such as malfunction or runaway due to the abnormality in the control signal. It is necessary to prevent this.

However, conventional microcomputers do not have means for detecting abnormalities in the control signals, and it is difficult to prevent secondary failures such as malfunctions and runaways due to abnormalities in the control signals.

The present invention has been made with the above-mentioned points in mind, and the problem arises when a control device such as a central processing unit accesses a peripheral device such as a memory or an input/output interface via a bus line. a first control signal, a second control signal that is outputted in response from the peripheral device to the control device via the bus line during a data input/output enabled period of the peripheral device by access from the control device; a failure detection circuit to which a third control signal for data input/output command of the peripheral device is outputted to the peripheral device via the bus line; the failure detection circuit generates the first control signal; detecting a failure from the non-output of the second control signal or the third control signal during the period and the output of the second control signal or the third control signal during the non-occurrence period of the first control signal; This is a fault detection method for an electronic computer, characterized by outputting a fault detection signal.

Therefore, if some kind of failure occurs during the generation period of the first control signal, that is, when the peripheral device is accessed by the control device, the second control signal is no longer output to the control device, or the third control signal is not output to the peripheral device. If the first control signal is not output, a failure detection signal is output from the failure detection circuit, and similarly, some failure occurs during the non-occurrence period of the first control signal, that is, when the peripheral device is not accessed by the control device.
When the second control signal is output to the control device or the third control signal is output to the peripheral device, a failure detection signal is output from the failure detection circuit, and the failure detection circuit reliably and quickly detects an abnormality in the control signal due to the failure. Based on the failure detection signal, the failure location can be promptly repaired to prevent the occurrence of secondary failures such as malfunctions and runaways.
Reliability can be improved.

Next, a first embodiment of the computer failure detection method of the present invention will be described with reference to FIG. 6 and the following drawings.

In FIG. 6, Ia is a "0" read control signal sent to the decoder 2a via the control bus 4c and read control line rm in FIG.
The first input terminal to which RCm is input, Ib is the control bus 4c, the second input terminal to which the "0" write control signal WCm sent to the decoder 2a via the write control line wm is input, Ic is the control bus 4c, a third input terminal to which a read control signal RCi of "0" is input, which is sent to the decoder 3a via the read control line ri; Id is a control bus 4c, which is sent to the decoder 3a via the write control line wi; The fourth input terminal Ie to which the write control signal WCi of "0" is input is the response line xm, Ie from the decoders 2a and 3a, respectively.
a fifth input terminal to which a "0" response signal XK sent to each of the bus masters 1a to 1n via each of xi and the control bus 4c is input;
If is a sixth input terminal to which the first control signal Sa generated in each of the bus masters 1a to 1n is input.

A 4-input type NAND gate 5 is provided in the failure detection circuit 5 at the first to fourth input terminals Ia to Id.
Each input terminal of a is connected, and each control signal
When any one of RCm, RCi, WCm, and WCi is output to the memory 2 or the interface 3, a gate signal of "1" is output from the NAND gate 5a.

Further, the input terminal of the first inverter 5b provided in the failure detection circuit 5 is connected to the fifth input terminal Ie, and while the response signal XK is input to the fifth input terminal Ie, "1" is output from the first inverter 5b. An inverted signal is output.

Further, the trigger input terminal ta of the first flip-flop 5c provided in the failure detection circuit 5 is connected to the sixth input terminal If, the first control signal Sa is input to the sixth input terminal If, and the sixth signal input terminal If The first flip-flop 5c is triggered when the level of the flip-flop rises from "0" to "1", and the data input terminal of the first flip-flop 5c when triggered
The level of da is held and the second
It is output to inverter 5d.

Then, the gate signal of the NAND gate 5a, the inverted signal of the first inverter 5b, and the Q output terminal qa
Since the output signal of the first OR gate 5e is input to the 3-input type first OR gate 5e, and the output signal of the first OR gate 5e is input to the data input terminal da, each control signal RCm, RCi, WCm,
Any one of WCi continues to be output to the memory 2 or interface 3, and while the gate signal of the NAND gate 5a becomes "1", access to the memory 2 or interface 3 by any of the bus masters 1a to 1n causes , first control signal
When Sa is input to the sixth input terminal If, the level of the sixth input terminal If rises from "0" to "1" due to the input of the first control signal Sa, and the first flip-flop 5c is triggered.

By the way, when the first flip-flop 5c is triggered, the response signal XK is sent to the fifth input terminal Ie.
is not input, the inverted signal of the first inverter 5b is held at "0", and the output signal of the Q output terminal qa of the first flip-flop 5c is also held at "0".

Therefore, any of the bus masters 1a to 1n
When the first flip-flop 5c is triggered by access to the control signals RCm, RCi,
If either WCm or WCi is output to the memory 2 or the interface 3, a "1" gate signal from the NAND gate 5a causes the first OR gate 5e to output "1" to the data input terminal 5e of the first flip-flop 5c. A gate signal of `` is output, the gate signal is held in the first flip-flop 5c, and the output signal of the Q output terminal qa of the first flip-flop 5c becomes ``1''.

and the Q output terminal of the first flip-flop 5c.
When the output signal of qa becomes "1", a failure detection signal of "0" is output from the second inverter 5d to the first output terminal Oa.

Note that when the failure detection signal is not output, the level of the first output terminal Oa is held at "1" by the voltage of the power supply terminal Va via the first resistor 5f.

Furthermore, when the first flip-flop 5c is triggered by an access from any of the bus masters 1a to 1n, if the response signal XK continues to be output to the bus masters 1a to 1n due to some kind of failure, the first inverter 5b is inverted. Since the signal is held at "1", "1" is output from the first OR gate 5e to the data input terminal da of the first flip-flop 5c.
A gate signal of "0" is output from the second inverter 5d to the first output terminal Qa as described above.

Furthermore, the failure detection circuit 5 includes a NAND gate 5a.
a third inverter 5g to which a gate signal of
Inverted signal and fifth input terminal of the inverter 5g
A second three-input type OR gate 5h receives the response signal XK of Ie, and a second flip-flop 5i receives the gate signal of the OR gate 5h to the data input terminal db, and has a trigger input terminal tb and a Q output terminal qb. , a third inverter 5j provided between the Q output terminal qb of the flip-flop 5i and the first output terminal Oa, and the response signal XK of the fifth input terminal Ie are input to the clear terminal cl, and the sixth input terminal If a first control signal Sa is input to a trigger input terminal tc, and an output terminal is connected to a trigger input terminal tb and a second output terminal Ob of a second flip-flop 5i;
A resistor 5l connected to the power supply terminal Vb and a capacitor 5 to which the power supply voltage is applied via the resistor 5l.
A time constant circuit 5n of a multivibrator 5k consisting of m is provided.

When the memory 2 or the interface 3 is accessed by any of the bus masters 1a to 1n, each control signal is
RCm, RCi, WCm, and WCi are all memory 2
Alternatively, if the gate signal of the NAND gate 5a continues to be held at "0" without being output to the interface 3, the inverted signal of the third inverter 5g is held at "1".

On the other hand, the multivibrator 5k sends a response signal.
It is cleared by the input of XK, that is, the level of the fifth input terminal Ie falls from "1" to "0", and before any of the bus masters 1a to 1n accesses the memory 2 or the interface 3. In this case, the output signal of the output terminal of the multivibrator 5k is held at "1", and the "1" output signal of the output terminal is transferred to the second output terminal.
At this time, the "1" output signal via the second output terminal Ob is sent to each bus master 1a to 1n as a so-called ready signal (READY signal). , each bus master 1a-1n detects that the memory 2 and interface 3 are not being accessed.

By the way, each control signal RCm, RCi, WCm, WCi
If there is no abnormality in the response signal XK, one of the bus masters 1a to 1n, for example
When memory 2 or interface 3 starts to be accessed, as shown by the solid line in FIG. 7a,
The first control signal Sa is input to the sixth input terminal If from time ta, and the level of the sixth input terminal If becomes "0" at time ta.
It rises to “1” from

Then, the multivibrator 5 is triggered by the rise of the level of the sixth input terminal If from "0" to "1", and as shown by the solid line in FIG. 7b,
At time ta, the output signal of the output terminal of the multivibrator 5 is inverted from "1" to "0", the ready signal output from the second output terminal Ob is suddenly cut off, and the time constant is determined by the time constant circuit 5n. The output signal of the output terminal is “0” for a predetermined period T.
begins to be retained.

Further, as shown by the solid line in FIG. ”
, and an inverted signal of "0" is output from the third inverter 5g to the second OR gate 5h.

Furthermore, at time tc, the memory 2 or the interface 3 enters a state in which data DT can be input or output, and as shown by the solid line in FIG.
is output, and the level of the fifth input terminal Ie falls from "1" to "0" at time tc.

Then, as the level of the fifth input terminal Ie falls from "1" to "0", the multivibrator 5k is cleared before the predetermined period T elapses, and as shown by the solid line in Fig. 7b, the multivibrator 5k is output at time tc. terminal qc
The output signal of is inverted from "0" to "1", a ready signal is output from the second output terminal Ob, and the second flip-flop 5i is triggered.

However, during tc, the inverted signal of the third inverter 5g is held at "0" and the Q output terminal
Since the output signal of qb is held at “0”, the second
The gate signal of OR gate 5h becomes “0” and Q
The output signal of output terminal qb continues to be held at “0”,
The inverted signal of the fourth inverter 5j is held at "1".

On the other hand, at time tc, the first flip-flop 5c is not triggered, so the output signal of the Q output terminal qa is held at "0", and the inverted signal of the second inverter 5d is also held at "1".

Therefore, if there is no abnormality in each control signal RCm, RCi, WCm, WCi and response signal XK, no failure detection signal is output to the first output terminal Oa.

Next, if none of the control signals RCm, RCi, WCm, and WCi are output to the memory 2 or the interface 3 at time tb due to some kind of failure, the inverted signal of the third inverter 5g becomes "1" at time tc. Therefore, the gate signal of the second OR gate 5h becomes "1" and the response signal XK is no longer output from the memory 2 or the interface 3 to the bus masters 1a to 1n.

If the response signal XK is not output due to some kind of failure, the level of the fifth input terminal Ie will continue to be held at "1" even at time tc, as shown by the two-dot dashed line in Figure 7d, and the output of the multivibrator 5k. The output signal of the terminal is held at "0" from time ta until time td when a predetermined period T has elapsed, and as shown by the two-dot broken line in Figure b, the output signal of the output terminal changes from "0" to " 1”, and at td, the second flip-flop 5i is triggered and the second flip-flop 5i is triggered.
A ready signal is output from the output terminal Ob.

By the way, since the response signal XK is not output at the time tc, the bus masters 1a to 1n that accessed the memory 2 or the interface 3 are held in a standby state until the ready signal is output at the time td. As shown by the two-dot broken line, the period in which the level of the sixth input terminal If is held at "1" and the period in which the gate signal of the NAND gate 5a is "0" are extended.

Since the response signal XK is not output, the level of the fifth input terminal Ie is held at "1" during td, the gate signal of the second OR gate 5h becomes "1", and the level of the output terminal of the 22nd flip-flop 5i becomes "1" during td. The output signal is inverted from "0" to "1", the inverted signal of the fourth inverter 5j is inverted from "1" to "0", and a failure detection signal is output from the first output terminal Oa.

Note that even though any one of the control signals RCm, RCi, WCm, and WCi has been output to the memory 2 or the interface 3, due to some failure, the response signal of the memory 2 or the interface 3 is not sent to the bus masters 1a to 1n. Even if XK is no longer input, the first
A failure detection signal is output to the output terminal Oa, and a ready signal is output to the second output terminal Ob.

Therefore, any of the bus masters 1a to 1n
During the access period, each control signal RCm, RCi,
When neither WCm nor WCi is output to the memory 2 or interface 3, or when any of the control signals RCm, RCi, WCm, or WCi is output, the response signal XK is not output to the bus masters 1a to 1n. , a predetermined period T based on the time constant circuit 5n after the first control signal Sa is output.
After lapse of time, the output signal of the output terminal of the second flip-flop 5k is inverted from "0" to "1", the inverted signal of the fourth inverter 5j is inverted from "1" to "0", and the output signal of the first output terminal Oa is inverted from "1" to "0". A failure detection signal is output from the bus master 1a to 1, and a ready signal is output from the second output terminal Ob.
The standby state of n is released.

Note that the predetermined period T is set to a period that is sufficiently larger than the delay of the response signal XK with respect to the first control signal Sa, that is, the response period of the memory 2 and the interface 3.

That is, the first control signal Sa is not output from any of the bus masters 1a to 1n, and before the memory 2 or the interface 3 is accessed,
Due to some kind of failure, the output of each control signal RCm, RCi, WCm, WCi, which is the second control signal, to the memory 2 or the interface 3, and the output of the response signal XK, which is the third control signal, to the bus masters 1a to 1n.
If the output is being performed, the memory 2 or the interface 3 will begin to be accessed by any of the bus masters 1a to 1n, and the first control signal
When Sa starts to be output, a failure detection signal is output to the first output terminal Oa, and conversely, the memory 2 or the interface 3 is accessed by any of the bus masters 1a to 1n, and the first control signal Sa is output.
Due to some failure, each control signal RCm, RCi, WCm, WCi is output to memory 2 or interface control signal RCm, RCi,
When the response signal XK is not output to the bus masters 1a to 1n even though WCm and WCi are input to the memory 2 or the interface 3, a failure detection signal is output from the first output terminal Oa, and the second A ready signal is output from the output terminal Ob, and the bus masters 1a to 1n are released from the standby state, making it possible to accurately and quickly detect abnormalities in control signals due to failures, thereby preventing secondary failures such as erroneous control or runaway. In addition, the standby state of the bus masters 1a to 1n can be automatically canceled, and reliability can be improved.

Further, since the configuration of the failure detection circuit 5 is simple, it can be applied to small-sized computers such as microcomputers to obtain great effects.

Even when the failure detection circuit 5 fails, a plurality of failure detection circuits identical to the failure detection circuit 5 are provided so that an abnormality in the control signal can be detected and reliable failure detection can be performed. Of course, by maintaining the FAIL SAFE characteristic, more reliable failure detection can be performed.

Also, when the failure detection signal is output, the first
It is also possible to diagnose a failure location by separately providing a circuit that separately stores the levels of each of the fifth input terminals Ia to Ie.

Furthermore, since the fault detection circuit 5 reliably detects abnormalities in the control signals, it is possible to accurately detect abnormalities in the address signals AD and data DT of the address bus 4a and data bus 4b, respectively, when the control signals are normal. Detection is also easy.

[Brief explanation of drawings]

Figure 1 is a partial block diagram of an example of a conventional electronic computer, Figures 2 a to d, Figures 3 a to d, and Figure 4 a.
~d, Figures 5a~d are timing charts for explaining the operation of Figure 1, Figure 6 is a wiring diagram of essential parts of one embodiment of the computer fault detection method of the present invention, and Figure 7a. -d are timing charts for explaining the operation of FIG. 1a to 1n...Bus master, 2...Memory,
3... Input/output interface, 4... Bus line, 5... Failure detection circuit.

Claims (1)

[Claims] 1 A first control signal generated in the control device while a control device such as a central processing unit accesses a peripheral device such as a memory or an input/output interface via a bus line; a second control signal that is output in response from the peripheral device to the control device via the bus line during the data input/output enabled period; and a second control signal that is output from the control device to the peripheral device via the bus line. a failure detection circuit to which a third control signal for data input/output command is input;
The failure detection circuit causes non-output of the second control signal or the third control signal during the generation period of the first control signal, and non-output of the second control signal or the third control signal during the non-occurrence period of the first control signal. 1. A fault detection method for an electronic computer, comprising detecting a fault from an output and outputting a fault detection signal from the fault detection circuit.