KR20050036032A - Error detecting circuit for storing data in system memory - Google Patents

Abstract

The present invention can detect a defect generated in the memory in real time to take measures such as using a redundant memory when detecting the defect so that the system can detect the defect so that the information in the memory is damaged and do not lead to system data errors A fault detection circuit of a memory, comprising: a write buffer for receiving and storing data, and receiving a write control signal and storing the data in first and second memories; First and second memories for receiving data from the write buffer and storing the data; A comparator for reading data from the first and second memories, comparing the two data, and outputting a mismatch signal when the two data do not match; It is composed of a read buffer for storing the data output from the comparator and outputting the stored data by the enable signal to ensure the normal operation of the system by reading the normal data from another redundant memory when the error is detected.

Description

Error detecting circuit for storing data in system memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection circuit of a system memory. In particular, the present invention relates to a fault detection circuit of a system memory, and to detect a fault occurring in real time in real time so that a redundant memory can be used to detect a fault. The present invention relates to a defect detection circuit of a system memory capable of detecting a defect so as not to lead to an error.

In the field of railway signal control, embedded computer technology is used in fields requiring high reliability and safety, and representative examples are used for controlling electronic interlocking devices, automatic train control devices, and timed electronic crossings.

1 is a structure of a general memory that interfaces with a microprocessor in a system using a microprocessor.

The memory 2 is a device that receives and stores data from the microprocessor 1 or transmits data at the request of the microprocessor. The memory 2 includes an address bus, a data bus, and a control bus. To interface with the microprocessor (1).

2 shows a process of reading / writing data to a general memory.

In order to write 0xFFFF to 0x0000A2 from 0x0000A0 to 0x0000A4 in the memory map represented by 16 bits, 0x0000A4 signal is applied to the address bus from the microprocessor 1 in the structure of FIG. After the chip select signal and the read / write signal are set to write, if 0xFFFF is applied to the data bus, it is written to the memory 2.

In order to read data from the memory 2, 0x0000A2 is applied to the address bus and then the read signal is applied to the chip select signal and the read / write signal of the control bus. .

Such a conventional memory stores data in a plurality of areas in software in order to detect data corruption due to an electrical disturbance or timing mismatch in storing data or a hardware defect in the memory. The occurrence of defects was monitored by comparison or by using extra information such as parity.

This structure does not detect defects generated in a computer system using a microprocessor in real time, and places a large amount of load on the microprocessor for detection of software defects.

The present invention is to solve the above problems, it is an object of the present invention to provide a defect detection circuit of the system memory for detecting defects in real time at the time of manufacturing a commercial control board or control board using a microprocessor.

Another object of the present invention is to detect a defect occurring in the memory of the system in real time to prevent the malfunction of the system by using the memory in which there is undamaged data by corrupting the information of the memory does not lead to an error of the system data It is to provide a defect detection circuit of the system memory.

Another object of the present invention is to detect a defect caused by external noise or damage to a device when data is stored in the system memory in a control board using a microprocessor defect of the system memory to ensure the normal operation of the system memory It is to provide a detection circuit.

In order to achieve the above object, a system memory defect detection circuit according to the present invention comprises: a write buffer which receives data and stores data therein, and receives a write control signal and stores the data in first and second memories; First and second memories for receiving data from the write buffer and storing the data; A comparator for reading data from the first and second memories, comparing the two data, and outputting a mismatch signal when the two data do not match; And a read buffer for storing data output from the comparator and outputting the stored data by an enable signal.

Since the first and second memories are physically connected in parallel, the same physical address may be simultaneously accessed by the same read / write control signal, thereby simultaneously reading or writing data.

In addition, since data input to the comparator by read control signals from the first and second memories are hardware-synchronized and output from a memory having the same timing, the data is electrically connected to the data bus only when the data is matched. Will be loaded.

An embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a defect detection circuit of a system memory according to the present invention.

The defect detection circuit of the system memory according to the present invention includes: a write buffer 11 for receiving data and storing data therein, and receiving a write control signal and storing the data in the first and second memories 12 and 13; First and second memories 12 and 13 for receiving and storing data from the write buffer 11; A comparator (14) for reading data from the first and second memories (12, 13) and comparing the two data and outputting a mismatch signal when the two data do not match; And a read buffer 15 for storing data output from the comparator 14 and outputting the stored data by an enable signal.

In order to explain a process in which the memory defect detection circuit according to the present invention configured as described above writes data to the memories 12 and 13, a memory map and a timing chart will be described with reference to FIG.

The microprocessor 10 first specifies an address to store via the address bus 18 in order to store data in the memories 12 and 13. For example, a "0x0000A4" signal is applied to the address bus 18 as shown in Fig. 5E to store data at the "0x0000A4" address of the memory 12,13.

When the "0x0000A4" signal is applied to the address bus 19, the "0x0000A4" address of the memory 12, 13 is designated as shown in the memory map of FIG.

After designating the addresses of the memories 12 and 13 as " 0x0000A4 ", the " Buffer Enable " signal is transmitted to the write buffer 11 via the control bus 16 as shown in Fig. 5A. After outputting to the write state, the microprocessor 10 applies data " 0xFFFF " to the data bus 17 and stores it in the write buffer 11 as shown in FIG.

After storing the data "0xFFFF" in the write buffer 11, as shown in Fig. 5B, the chip select signal "0" is output to the memories 12 and 13, and the memory 12 and 13 are checked. In the enable state, the chip select signal " 0 " outputs " 0xFFFF " stored in the write buffer 11 so that data " 0xFFFF " is output from the write buffer 11 as shown in FIG. "0xFFFF" is stored in the memories 12 and 13.

In the same manner, data is stored at other addresses of the memory 12 and 13, and the memory defect detection circuit according to the present invention reads data from the memory 12 and 13 while the data is stored. It demonstrates with reference to FIG. 4 and timing chart FIG.

The microprocessor 10 applies the " 0x0000A4 " signal to the address bus 18 as shown in Fig. 6E to address the memories 12 and 13, and reads the read buffer through the control bus 16. The buffer enable signal is input to (15) to put the read buffer 15 in the enabled state (see (a) of FIG. 6).

After designating the addresses of the memories 12 and 13 as " 0x0000A4 ", as shown in Fig. 6B, the chip select signals are output as " 0 " to the memories 12 and 13 and placed in the enabled state. Data transfer occurs between the comparator 14 and the memories 12 and 13. In other words, " 0xFFFF " stored at the address " 0x0000A4 " in the memories 12 and 13 is output to the comparison section 14 for comparison (see FIG. 6 (c)).

Since the first and second memories 12 and 13 are physically connected in parallel, the same physical address may be simultaneously accessed by the same read / write control signal, thereby simultaneously reading or writing data.

Therefore, since the " 0xFFFF " data input to the comparator 14 by read control signals from the first and second memories 12 and 13 are data synchronized in hardware and output from a memory having the same timing, In comparison, the data is loaded on the data bus through the data read buffer 15 only when the data match (see (d) of FIG. 6).

If the data read and output at address "0x0000A4" of the first memory 12 and the data read and output at address "0x0000A4" of the second memory 13 are different from each other, the comparator 14 is shown in FIG. As shown in (e), the defect detection signal is output to the microprocessor 10.

Therefore, the microprocessor 10 is detected by notifying the microprocessor 10 of a defect in the data due to the deterioration of the stored data due to the electrical disturbance or the timing mismatch in the process of storing the data or the hardware defect of the memory. ) Can read data from other redundant memories and prevent data from corrupted memory leading to system failure.

As described above, according to the present invention, a write buffer, a comparator, two memories, and a read buffer are used to detect hardware defects due to external noise or data errors due to physical damage to the memory, thereby providing another redundancy in error detection. The normal operation of the system can be guaranteed by reading the normal data from the memory.

1 is a structure of a general memory for interfacing with a microprocessor in a system using a microprocessor,

2 is an explanatory diagram showing a process of reading / writing data into a general memory;

3 is a block diagram showing a configuration of a defect suppression circuit of a system memory according to the present invention according to the present invention;

4 is an explanatory diagram showing a process of reading / writing data into a memory in a defect detection circuit of a system memory according to the present invention;

5 is a timing diagram showing a process of writing data into a memory by a memory defect detection circuit according to the present invention;

6 is a timing diagram showing a process in which a memory defect detection circuit of the present invention reads normal data from a memory;

7 is a timing diagram illustrating a process in which a memory defect detection circuit according to the present invention detects an error while reading data from a memory and outputs an error detection signal.

<Description of Symbols for Main Parts of Drawings>

11: Write buffer 12: First memory 13: Second memory

14: Comparative 15: Read buffer 16: Control bus

17: Data bus 18: Address bus

Claims (3)

A write buffer 11 for receiving and storing data and receiving a write control signal and storing the data in the first and second memories 12 and 13; First and second memories 12 and 13 for receiving and storing data from the write buffer 11; A comparator 14 which reads data from the first and second memories 12 and 13 and compares the two data and outputs a mismatch signal when the two data do not match; And a read buffer (15) for storing data output from the comparing unit (14) and outputting the stored data by an enable signal. The memory device of claim 1, wherein the first and second memories 12 and 13 are physically connected in parallel to simultaneously access the same physical address by the same read / write control signal, thereby simultaneously reading or writing data. Fault detection circuit of the system memory, characterized in that. The data inputted to the data bus (17) according to claim 1, wherein data input from the first and second memories (12, 13) to the comparator (14) is synchronized in hardware so that only if the data coincide with each other. And a defect detection circuit of the system memory.