JPS61134857A - Multilexing memory device - Google Patents

Abstract

PURPOSE:To attain a test and a maintenance efficiently by commanding externally a specific block with the priority and commanding the normal operation and test operation so as to attain the ease of memory test in a block. CONSTITUTION:The memory is duplicated by the 0-th block 10 and the 1st block 11, a data including a parity bit is read from the 0-th block 10 at read and a similar data is read from the 1st block. Error detection circuits 12, 13 detect the parity error of the read data. The read/write of the content of a flip-flop in a priority circuit 14 and an operation mode circuit 15 is attained from an external device such as a service processor 16, the priority circuit 14 has information representing whether the 0-th block 10 or the 1st block 11 is selected with priority and the operation mode circuit 15 commands the mode of normal operation or test operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage data control method by multiplexing cache memory, etc. in an information processing device, and improves access efficiency and eases maintenance/testing. This invention relates to a multiplexed storage device.

[Conventional technology and problems]

FIG. 4 shows an example of a conventional duplex storage device.

The memory is duplicated by the 0th block 20 and the 1st block 21, and write data WD having the same contents is supplied to both blocks.

To read the stored data, flip-flop 2
6 is selected by the selector 22. That is, the read data is set in the register 23 with one of the blocks 20 or 21 being valid according to the selection of the selector 22. If the error detection circuit 24 detects that there is an error in this read data, the state of the flip-flop 26 is inverted via the exclusive OR circuit 25. As a result, the selector 22 is switched and reading from the other block is performed by retrying. After that, every time the same error occurs,
Blocks 20, 21 are alternately switched to ensure that the correct data is read.

According to the above-mentioned conventional method, the blocks are switched every time an error occurs, which is inconvenient, for example, when testing a device in which performance evaluation is performed for each block.

Another problem is that it is difficult to detect defective memory elements during fault investigation. Furthermore, if an error occurs during normal operation, it is necessary to retry after block switching, and the retry time is wasted.

[Means for Solving the Problems] The present invention aims to solve the above problems, and makes it possible to give priority instructions to a specific block from the outside, and also makes it possible to give instructions for two normal operations and test operations. When in test mode, which instructs the operation, even if an error is detected during reading, the system does not switch to another block.
This allows for efficient testing and maintenance.

Furthermore, it is possible to shorten the retry time when an error occurs in the second normal operation mode. That is.

A multiplexed storage device of the present invention includes a plurality of blocks of memory for storing information, and writes and reads the same contents to and from the memories of the plurality of blocks. The data read from each of the plurality of blocks is based on a plurality of error detection circuits that each check, a priority signal that gives a priority selection order for each block, and an operation mode signal that indicates normal operation or test operation. a select circuit for selecting one block of memory; when the operation mode signal indicates normal operation, the select circuit selects a correct one from among the plurality of blocks of memory based on the priority signal and the check result by the error detection circuit; When one block of read data is selected and the operation mode signal indicates test operation,
The present invention is characterized in that it is configured to select read data from the highest priority block designated by the priority signal, regardless of whether the check result by the error detection circuit is good or bad. An embodiment will be described below with reference to one drawing.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an example of the error detection circuit shown in FIG. 1, and FIG. 3 is an example of the selector shown in FIG. 1.

In the example shown in FIG. 1, the memory is duplicated by the 0th block lO and the first block 11. Similar to the prior art, the write data WD is.

Both blocks are supplied with the same content. During reading, data BKORD (0 to 4.P) including parity pits is read from the 0th block 10, and similar data BKIRD (0 to 4.P) is read from the first block 11.

The error detection circuits 12.13 are so-called parity checkers. For example, as shown in FIG.

The error detection circuit 12 is composed of a simple exclusive OR circuit, and the error detection circuit 12 detects the read data B from the 0th block 10.
When the parity of KORD (0 to 4.P) is normal,
The output signal BKO is set to "1", and if there is a parity error, the output signal BKO is set to "0". Similarly, the error detection circuit 13 also sets the signal BK1 to "1" when the data read from the first block 11 is normal. , if there is a parity error), the BKI is set to "0".Of course, error detection other than parity may be performed in implementing the present invention.

The priority circuit 14 is composed of two flip-flops, for example,
Should the 0th block 10 be selected preferentially?

It holds information as to whether the first block 11 is selected preferentially. When giving priority to the 0th block 10, the priority signal PO is set to "1", and when giving priority to the first block 11, the priority signal P1 is set to "1".

The operation mode circuit 15 is also composed of, for example, a flip-flop, i! ! l Indicates the mode of normal operation or test operation. When in test mode, output signal TEST ON
-h<"1" and 2, in the normal mode, the output signal TEST OFF becomes "1".

The contents of the flip-flops of the priority circuit 14 and the operation mode circuit 15 can be read/written from an external device such as a service processor (SVP) 16, for example.

The selector 17 is a circuit that selects either the read data BWORD (0 to 4.P) from the O-th block 10 or the read data BKIRD (0 to 4.P) from the first block 11. for example.

It is constructed as shown in FIG. In fig.

AI to A6 represent AND circuits, and 01 represents an OR circuit.

The register 18 is an output register in which read data RD selected by the selector 17 is stored.

Next, the operation of the two embodiments will be explained. In the following description of the operation, it is assumed that the priority circuit 14 instructs to preferentially select the O-th block 10. At this time, the priority signal PO is "1".

The signal P1 is 0''.The operating principle is the same when the first block 11 takes priority.

(i) In normal operating mode.

In the normal operation mode, the output signal TEST ON of the operation mode circuit 15 is "0", and the output signal TF!
ST OFF is 1". Therefore, the outputs of the AND circuits A1 and A2 shown in FIG. be done.

Then, the read data BIWOR of the O-th block 10
If there is no parity error in D, the signal BKO becomes 1", so the read data BKORD is sent to the AND circuit A3.
and output via OR circuit 01. On the other hand, if there is an error in the read data of the 0th block 10 and the read data of the 1st block 11 is normal, the read data BKIRD from the 1st block 11 is transferred to the AND circuit A.
4 and the OR circuit 01. Both plotters 1
If the read data from 0.11 are both errors, the output data from OR circuit 01 is.

It is fixed at “O”.

(11) In case of test operation mode.

In the case of the test operation mode, the output signal T[! of the operation mode circuit 15 is present. This is because ST OFF is “0”.

The outputs of the AND circuits A3 to A6 shown in FIG. 3 are inhibited. Assuming that the 0th block 10 is designated as a priority, since the signal PO is "1", the read data 13WORD from the 0th block 10 is passed through the AND circuit A1 regardless of the presence or absence of an error. , is always output. Note that if the first block 11 is designated as a priority, the read data BKIRD from the first block 11 is always outputted via the AND circuit A2.

In the above embodiment, the case where the blocks are duplicated has been described, but it is clear that the same structure can be applied to the case where three or more blocks are multiplexed.

〔Effect of the invention〕

As explained above, (1) according to the present invention, by specifying the priority and specifying the operation mode, in the case of the test operation mode, it is possible to read out fixed blocks, and (2) in the normal operation mode, it is possible to read the blocks in the specified priority order. Accordingly, it becomes possible to read normal data. Therefore, memory testing within the block becomes easy, and testing and maintenance can be performed efficiently. Furthermore, access retries during normal operation are no longer necessary, improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an example of the error detection circuit shown in FIG. 1, FIG. 3 is an example of the selector shown in FIG. 1, and FIG. 4 is a conventional duplex storage device. Here is an example. In the figure, 10 and 11 are blocks, 12 and 13 are error detection circuits, 14 is a priority circuit, 15 is an operation mode circuit, 16 is a service processor, 17 is a selector, and 18 is a register. Patent applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) D Fang 2

Claims (1)

[Claims] A multiplexed storage device comprising a plurality of blocks of memory for storing information and writing and reading the same contents to and from the plurality of blocks of memory, a plurality of error detection circuits each checking read data from the plurality of blocks. , a selection circuit that selects data of one block from among the data read from each of the plurality of blocks based on a priority signal giving a priority selection order for each block and an operation mode signal indicating normal operation or test operation; When the operation mode signal indicates normal operation, the selection circuit selects one correct block of read data from the plurality of blocks of memory based on the priority signal and the check result by the error detection circuit, and performs the operation. Multiplexing characterized in that when the mode signal indicates a test operation, read data from the highest priority block designated by the priority signal is selected regardless of whether the check result by the error detection circuit is good or bad. Storage device.