JPH01277951A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To improve the reliability of data transfer and to quickly cope with the occurrence of trouble by providing a trouble detecting means in each of plural control bus interface parts constituting a data transfer equipment and detecting trouble at the time of outputting data to a bus. CONSTITUTION:When the polarity of a control bus driving signal of a signal line 18 is made effective by a central processing unit 7, data of the unit 7 is outputted to a control bus 1. That is, when the control bus driving signal of the signal line 18 is effective, polarities of driving signals of the other signal lines 17 and 19 are made ineffective, and data of the unit 7 is outputted to the bus 1 through an interface part 8. Further, this data is inputted to a main storage device 2 and an input/output device 12, and simultaneously, input/output signals of interface parts and data to be outputted to the bus 1 are compared with each other by a comparing part. Comparison results are transmitted to a detecting part 11 and the unit 7 independently of contents of results to discriminate whether trouble occurs in interface parts or not; and when it is discriminated that trouble occurs, detecting parts 6, 11, and 16 are referred to determine which interface the trouble occurs in.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer device in which a plurality of bus masters exchange data via a control bus, and particularly relates to a data transfer device in which a plurality of bus masters exchange data via a control bus. This invention relates to an improvement in a fault detection method in an interface means for outputting.

[Conventional technology]

Conventional means for detecting failures in data transferred by a control bus include a device on the receiving side that performs a parity check on the transferred data, but a device on the driving side of the control bus does not perform any checking.

[Problem to be solved by the invention]

However, in the conventional technology as described above, whether or not the data on the driving device side of the control bus is accurate can be verified only on the receiving side of the data. In other words, incorrect.

Errors in the data are discovered only after the data is transferred and checked on the receiving side, resulting in a lack of reliability in the data transferred using the control hash.

Furthermore, since the error is discovered after the erroneous data has been transferred, there is also the inconvenience that the response to a failure is delayed.

[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a data transfer device that improves the reliability of data transfer to a control bus and can quickly respond to the occurrence of a failure. That is the purpose.

[Means for solving problems]

In the present invention, a plurality of bus masters are each connected to a control bus via an interface unit, and one of the bus masters is driven based on a control bus drive signal to transfer data to other bus masters. The data transfer device includes comparison means for comparing input data and output data of the corresponding interface unit when the corresponding control bus drive signal is input, and data storage means for storing the comparison results. . Each interface section is equipped with a separate failure detection means. Furthermore, it is provided with processing means for outputting a control bus drive signal, detecting the occurrence of a failure from the comparison result of the comparison means, and specifying the interface section in which the failure has occurred from data stored in the data storage means. This aims to achieve the above objective.

[For production]

According to this invention, a failure detection means is provided in each interface section between the control bus and the bus master, which are targets of failure detection.

Each failure detection means includes a comparison section that compares input data and output data of the corresponding interface section when the corresponding control bus drive signal is input, and a data storage section that stores the comparison result. There is.

The comparison results by the comparison section are stored in the data storage section and also input to the processing means.

The processing means detects the occurrence of a failure from the comparison result, and specifies the interface section in which the failure has occurred from the data stored in each data storage means.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In this figure, the control bus includes main memory 2. A central processing unit 7 and an input/output device 12 are connected via interface sections 3, 8, and 13, respectively, and data is transferred between them via a control bus 1.

Each of the main storage device 2, central processing unit 7, and input/output device 12 is provided with a failure detection circuit 4.9°14.

Of these, the failure detection circuit 4 will be explained. The failure detection circuit 4 is composed of a comparison section 5 and a detection section 6. The comparison unit 5 has a function of comparing the input value and the output value of the output buffer of the interface unit 3 when the polarity of the control bus drive signal input from the central processing unit 7 becomes valid. Furthermore, the detection section 6 stores the comparison results from the comparison section 5.

The above-mentioned control bus drive signal is transmitted to the main storage device 2. It is designed to be input to an interface section 3 and a comparison section 5. Further, the comparison result in the comparison section 5 is input to the central processing unit 7 via a signal line 20.

Similarly, the failure detection circuit 9 includes a comparison section 10 and a detection section 11.
It is composed of: A control bus drive signal that provides operation timing to the comparison section 10 is inputted to the interface section 8 and the comparison section 10 through a signal line 18, respectively.

Further, the comparison result in the comparison section 10 is input to the central processing unit 7 via a signal line 21.

Similarly, the failure detection circuit 14 includes a comparison section 15 and a detection section 1.
6. A control bus drive signal that provides operation timing to the comparison section 15 is inputted to the input/output device 12, the interface section 13, and the comparison section 15 through a signal line 19, respectively. Also,
The comparison result in the comparator 15 is input to the central processing unit 7 via a signal line 22.

Note that the basic operation of the failure detection circuit 9.14 is the same as that of the failure detection circuit 4.

Next, the overall operation of the above embodiment will be explained with reference to the flowchart of FIG.

Here, an example will be described in which the central processing unit 7 validates the polarity of the control bus drive signal on the signal line 18 and data from the central processing unit 7 is output to the control bus 1.

First, when the control bus drive signal on the signal line 18 becomes valid (see step SA in FIG. 2), the other signal lines 17.1
The polarity of the control bus drive signal 9 becomes invalid (step S
(see C).

Therefore, data from the central processing unit 7 is output to the control bus 1 via the interface section 8 (see step SC), and further input to the main storage device 2 and the input/output device 12 (step SC). reference).

At the same time, the data to be outputted that was outputted from the central processing unit 7 and inputted to the interface unit 8 and the data to be outputted that was outputted from the interface unit 8 and inputted to the control bus 1 are respectively The comparison is performed at the timing given by the control bus drive signal described above (see step SC).

Regardless of the content of the comparison result, the detection unit 1
1 and the central processing unit 7 (see step SC).

The above operations are also performed in the failure detection circuits 4 and 14, respectively, and the comparison result of the comparison section 5.15 is sent to the detection section 6.16.
and are transmitted to the central processing unit 7.

Next, in the central processing unit 7, based on the input comparison result, it is determined whether or not a failure has occurred in the interface part (see step SC).As a result, when it is determined that no failure has occurred Then, the normal data transfer operation continues (see step SC).

On the other hand, when a failure is detected, the detection unit 6.11
．． 16 are referred to in the central processing unit 7, it is determined which interface section is faulty (see step SI), and the program at the time of failure is executed (see step SC). That is, positive 6
Necessary processing for data on control bus 1 that is not 1 is performed.

〔Effect of the invention〕

As explained above, according to the present invention, failure detection means are provided in each control bus interface section, and failure detection is performed at the time of data output to the control bus, thereby improving the reliability of data transfer to the control bus. It is possible to provide an unprecedented and excellent data transfer device that can improve the performance of the device and quickly respond to the occurrence of a failure.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of a data transfer device according to the present invention, and FIG. 2 is a flowchart showing an example of the operation of the embodiment. 1... Control bus, 2... Main storage device, 3.8.13
...Interface section, 4,9.14...Failure detection circuit, 5,10.15...Comparison section, 6.11.16
. . . detection unit, 7 . . . central processing unit, 12 . . . input/output device. Patent applicant: Ibaraki NEC Co., Ltd.

Claims (1)

[Claims] (1) Multiple bus masters are each connected to the control bus via an interface section, and one of the bus masters is driven based on a control bus drive signal to transfer data to other bus masters. The data transfer device includes a comparison means for comparing input data and output data of the corresponding interface section when the corresponding control bus drive signal is input, and a data storage means for storing the comparison result, Each interface section is equipped with a failure detection means, which outputs the control bus drive signal, detects the occurrence of a failure from the comparison result of the comparison means, and detects the interface in which the failure has occurred based on the data stored in the data storage means. 1. A data transfer device comprising processing means having a function of specifying a part.