JPH04220745A - Bus error detecting circuit - Google Patents

Bus error detecting circuit

Info

Publication number
JPH04220745A
JPH04220745A JP2404735A JP40473590A JPH04220745A JP H04220745 A JPH04220745 A JP H04220745A JP 2404735 A JP2404735 A JP 2404735A JP 40473590 A JP40473590 A JP 40473590A JP H04220745 A JPH04220745 A JP H04220745A
Authority
JP
Japan
Prior art keywords
bus
data transmission
circuit
data
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2404735A
Other languages
Japanese (ja)
Inventor
Yoshiro Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI FIELD SERVICE
NEC Fielding Ltd
Original Assignee
NIPPON DENKI FIELD SERVICE
NEC Fielding Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI FIELD SERVICE, NEC Fielding Ltd filed Critical NIPPON DENKI FIELD SERVICE
Priority to JP2404735A priority Critical patent/JPH04220745A/en
Publication of JPH04220745A publication Critical patent/JPH04220745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a bus error due to transmission from a device without bus using right by checking for the bus using right as well as for a parity error and permitting data transmission to the bus only when both checks are satisfied.
CONSTITUTION: An AND circuit 12 outputting a selective signal 18 when both the result of a register 13 holding information 19 indicating the presence or absence of the bus using right transmitted from an input/output controller and the parity result of a parity check circuit 9 for the data transmitted from a data transmission circuit 8 are positive, is provided. A data signal 14 from the data transmission circuit 8 is temporarily held in a register 11, and the data signal is transmitted to a bus 1 only when the selective signal 18 permits the data transmission to a bus 1.
COPYRIGHT: (C)1992,JPO&Japio
JP2404735A 1990-12-21 1990-12-21 Bus error detecting circuit Pending JPH04220745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2404735A JPH04220745A (en) 1990-12-21 1990-12-21 Bus error detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2404735A JPH04220745A (en) 1990-12-21 1990-12-21 Bus error detecting circuit

Publications (1)

Publication Number Publication Date
JPH04220745A true JPH04220745A (en) 1992-08-11

Family

ID=18514392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2404735A Pending JPH04220745A (en) 1990-12-21 1990-12-21 Bus error detecting circuit

Country Status (1)

Country Link
JP (1) JPH04220745A (en)

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