SU1619280A1 - Device for monitoring master computer - Google Patents

Description

t

(21) 4440419/24

(22) 13.06.88

(46) 07.01.91. Bksh. f 1

(71) Ufa Aviation Institute. Sergo Ordzhonikidze

(72) Yu.P.Kil ev, A.P. Zhil Ev and A.F. Gimranov

(53) 681.3 (088.8)

(56) USSR Author's Certificate No. 1120339, .cl. G 06 F 11/28, 1983.

USSR author's certificate number 1522216, il. G 06 F 11/28, 1988.

(54) DEVICE FOR CONTROL OF MANAGEMENT COMPUTERS

(57) The invention relates to computing and can be used in automatic

computer-based controls for monitoring the execution of computer programs and restoring the computational process upon failure. The purpose of the invention is to reduce the time of fixation failure. The device contains fixed memory blocks, adder, comparison circuit, registers, OR-NOT elements, triggers, delay element, I-NB element, address decoder, transition instruction decoder, pulse drivers, OR element, inputs, device outputs. The device makes it possible to recognize the failure in the equipment of the controlled computer and to restore the computational process by fixing the fact of failure and re-executing the command at which the failure occurred. 6 Il.

a ss

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The invention relates to computing and can be used in computer-based automatic control systems for monitoring the execution of programs on a computer and restoring the computational process upon a crash.

The purpose of the invention is to reduce the time of fixation failure.

Figure 1 shows the functional diagram of the device; 2 is a time diagram of the operation of the device in the absence of a fault in the equipment of the controlled D) VM; FIG. 3 is the same when executing a transition command; figure 4 - the same, at the time of fixing failure; Fig. 5 is the same when exiting an interrupt and recovering. computational process; Fig. 6 shows the layout of information in the permanent memory blocks.

The device (Fig. 1) contains the first block 1 of the permanent memory, the second block 2 of the permanent memory, the adder 3, the comparison circuit 4, the second register, the histor 5, the first trigger 6, the elements -OR-NOT 7-10, the second trigger 11, the element OR NOT 12, the delay element 13, the element AND-NOT 14, the third trigger 15, the decoder 16 transition commands, the element OR-NOT 17, the decoder 18 addresses, the element OR-NOT 19, the first driver 20 pulses, the second pulse shaper 21, the element OR 22, the first register 23, the device information input-output 24 (data bus), the device address input 25 (address bus), control output

26 devices (interrupt signal line), first control input 27 of the device (input signal line), second 4th control input 28 of the device (command start signal line), third control input 29 of the device (initial installation signal line ). In the time diagram of the operation of the device in the absence of “failure of the equipment of the controlled computer (FIG. 2), the following information is indicated: SM — information on data bus 24, PA — information on address bus 25, DK11 1 — signal on the first output of the decoder 16, NC — command start signal on the signal line 28, INPUT - input information signal to the processor of the controlled computer on the 27 signature line, BPP 2 - information on the information output of block 2, C - information on the output of the adder 3; Zprg 1, Pr 2 - the write signal to registers 5 and 23 from the output of the element AND-NOT 14, Pr 1 - information at the output of register 5, Pep, signal interception on the signal line 26, Pr 2 - the contents of register 23, CPC - the operation code of the current command of the computer being monitored, the CS is the control circuit, ftt is the delay time of the delay element 13 (# is the signal level does not matter).

The time diagram of the operation of the device when executing a transition command (FIG. 3) is indicated: ID — information on the data bus 24, 1 HA — information on the address bus 25, DCT 1 — signal at the first output of the encoder 16, DCL 2 — signal at the second the output of the decoder 16, NC - a signal on the signal line 28, ENTER - a signal to enter information into the computer processor | on line 27 of the signal, BPP - information at the information output of block 2, C - information at the output of the adder 3, T 3 - signal at the direct output of the trigger 11, ZsRg 1, Pr 2 - recording signal into registers 5 and 23 from the output elements-4 and I-NOT 14, Pr 1 - information at the output of register 5, PREP - interruption signal on interrupt signal line 26, Pr 2 - contents of register 23, KOG1 - operation code, CS - checksum, b, t - the delay time of the delay element 13.

In the time diagram of the operation of the device when exiting the interrupt and restoring the computational process (Fig. 3), it is indicated:

g 5 0 5

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BD - information on data bus 24, ША - information on address bus 25, DKPZ - signal at third output of decoder 16, PC - command start signal on line 28 command start signal, ENTER - information input signal to computer processor on line 27, BPP 2 - information at the information output of block 2, C - information at the output of the adder 3, ZiRg 1, Pr 2 - the signal i write to registers 5 and 23 from the output of the AND-14 element, Pr 1 - information at the output of the register 5, Sat T1 - a reset signal of the trigger 6 at the output of the OR-NOT 10 element, PREP - an interrupt signal on the interrupt signal line 26, Cbl T2 - a signal l reset flip-flop 15 at the output of OR-NO element 17, T2 - signal at the inverse output of the flip-flop 15, Pr 2 - contents of the register 23, the CPC - opcode, COP - checksum, ut - delay time of the delay element 13.

In the layout of information in blocks 1 and 2 (Fig. 6), A, B are the relative addresses of the cells of block 1 and block 2, the CPC is the operation code, and the CC is the checksum.

The device operates as follows.

The work program of the controlled computer is entered in block 1, and the checksums in block 2. The addresses of blocks 1 and 2 are the same. The computational process is monitored during the reading of the next command code from block 1 by blocking the sum of the read command code and the contents of register 5 with the checksum extracted from block 2. The addresses of the cells of block 1 containing the operation codes (commands) and cells of block 2, containing the corresponding checksums match ().

If the compared amounts from the outputs of the adder 3 and block 2 are the same, then the corresponding sum | from the output of the adder 3 is written to register 5. If the compared amounts do not match, the interrupt signal is generated, then the computational process is restored.

Consider the execution of the i-th command in the absence of failures during the execution of the previous command (figure 2). The computer processor transmits on the bus 24 the block cell address of block 1, containing

The operation code of the rth command (), after setting this address on bus 25, the computer processor generates an ENTER signal, then a start signal transmitted via lines 27 and 28 respectively, indicating that the processor is ready to receive information from block 1. Signal The INPUT is fed to the read inputs of block 1, from which GOGC is read on bus 24, and block 2, from which the checksum KCj1 is read from the first information input of comparison circuit 4. At the same time, the second information input of the adder 3 receives the CPC from the bus 24, and the first information input of the adder 3 from the output of the register 5 enters the CS, from the previous comparison step (read from the CPC block 1).

At the output of the adder 3, an amount is formed that coincides with KC, j, which is fed to the second information input of the comparison circuit 4, at the output of which a level signal O is received, which enters the information input of trigger 6. The command start signal from line 28 appears with. some delay relative to the INPUT signal for the operation of block 1, adder 3 and comparison circuit 4. The command start signal goes to the third input of the OR-NOT 7 element, from the output of which the signal goes to the synchronous input of the trigger 6. On the front of this signal, the trigger 6 is set to the state / corresponding to the signal level at its information input, i.e. remains in the zero state. Then the same signal from the output of the element OR NOT 7 through the delay element 13 and the element AND NOT. 1 is fed to the inputs of register 23 and register 5. Register 5 is entered on this signal by the CS from the output of the adder 3 and the address of the CPC is entered in register 23. The delay element 13 delays the signal from the output of the element OR-NE 7 by the time Јt necessary for triggering trigger 6.

The decoder 16 is a three-bit permanent programmable storage device with an address field corresponding to the address field of block 1 and block 2. The three-digit cells of the decoder 16 are addressed to the addresses of the block 1 cells that store the transition operation codes, entered code 110 (the low-order bit of this code corresponds to the first output of the decoder 16, and the high-order bit to the third output of the decoder 16). In the cells of the decoder 16 to addresses that match the addresses of the cells of block 1, which store the first operation codes of linear

plots (at the addresses of the beginning of the linear sections of the program), codes 101 are entered. The code 011 is entered into the cell of the decoder 16 at the address coinciding with the address of the last command of the interrupt processing program (exit command from the interrupt command). The rest of the decoder cells 16 add codes 111.

Consider the execution of the j-th command

0 transition to the hc-th linear section of the program (fig.Z). When the address of the code of the transition operation (COPC) appears on bus 25, the first output of the decoder 16 receives the signal O, which is fed to the information input of the trigger 11. If the reading of K0nnj failed to be fixed, a write signal is generated in the register 5 and register 23 from the output element

0 AND-NOT 14, which simultaneously arrives at the input of the second pulse generator 21 pulses, generating pulse 1 on the front of the input signal. Trig-1 pulse 11 is set to the zero state at the front of the pulse from the pulse generator output 21, corresponding to the signal level at its information input . From the direct output of trigger 11 to the second

0 the input of the element OR NOT 9 enters the signal O. After entering the processor of the computer being checked into the processor / in register 5 is stored by the COP., In register 23 is the address of the CPC nj. After executing the jth command

5, the processor transition of the computer transmits on the bus 24 the address of the beginning of the m-th linear section (the CPC address) in case there was no failure during the execution of the j-th transition command. When appearing

0 KOP addresses on bus 25 on the second

The output of the decoder 16 is the signal O, which is fed to the first input of the element OR-NOT 9, the output of which is signal 1, which is fed through the element OR-NOT 8 to the zero input of register 5, and zeroes it. If the execution of the j-th transition command failed, as a result of which the processor controls

My computer will not go to the beginning of the linear section, then register 5 will not reset, and when I enter the information processor from the cell of block 1 at the address transmitted via bus 24 at this point, a failure will be detected.

When a CPU is entered into the computer processor, if the system fails to execute the jth transition command, a comparison is made in scheme 4

compare the output rate of the hister accumulator 5), etc.

КСМ 0 + КОПтс 3 (0 - from the output of re-, as in the considered case, in the absence of failures in the ai-register 23, which contains KOP4.

computer controlled device. With the appearance of the command start signal, the signal from the output of the OR-NOT 7 element through the OR-G 12 element sets the trigger 11 "to one state

Suppose that in the equipment of a controlled computer, when executing the i-th command, a failure occurred, which led to a distortion of the computational process, as a result of which the computer processor, instead of block 1, containing KOI fa, turned to a cell containing, for example, KOP After- | Occurrences on goin 24 KOIIg (Fig. 4) at the output of the adder 3 appear KSP KS j + COL n, and from block 2 it is read to the address set on bus 25 - KSr. At the output of the comparison circuit 4, if the information at its inputs mismatches, signal 1 appears and a trigger 6 is set on the front of the signal from the output of the element OR-IE 7, from the direct output of which via line 26 to the processor of the controlled computer , causing the interruption of the working program of the computer. At the same time, the signal O from the inverted output of the trigger L is fed to the second, swarm input element AND 14 and prohibits the passage through it of the signal 1 from the output of the delay element 13, thereby preventing the formation of the recording signal of the register 5 and the register 23. The level interruption signal 1 is also fed to the first input of the element OR-NOT 7, preventing the passage of signals from line 27 and the beginning of a command from line 28 through it.

In order to organize an interrupt in a controlled computer, the processor loads onto the stack first the contents of the processor command counter, then the word "computer processor." In the counter ko20

25

thirty

35

40

45

50

55

After the appearance of this address on bus 25 (FIG. 5), it is recognized by decoder 18, at the output of which an O signal appears, arriving at the first input of the element OR 22. When an ENTER signal appears on line 27, which arrives at the second input of the element OR 22, the O signal appears at its output - a read signal from register 23.

When the address of the interrupt-exit command (KOP8pr) appears on the bus 25, the third output of the decoder 16 causes an O signal to arrive at the first input of the OR-NOT element 19. The command start signal of the line 28 goes to the second input of the OR-19 element On the front of the signal from the output of the element OR NOT 19, the trigger 15 is set to one, since the level 1 interrupt signal arrives at its information input. At the inverse output of the trigger 15 at this moment the signal O appears, which is fed to the blocking input adder 3. In this case the second information input of the adder Z is blocked; its information output is transmitted from the first information input of the adder 3, i.e. register information 5.

On the front of the signal from the output of the OR-NOT 19 element, the first pulse shaper 20 generates a signal 1, which triggers the trigger 6 (the interrupt signal is removed) through the element OR-NOT 10. The computer processor is output from the interrupt and control occurs at the CPC address, 1, i.e. re-executes the i-command, during the execution of which the failure occurred. When the KOP J bus appears on the 24th bus, the output of the adder 3 remains the COP, 1, since the adder 3 is blocked by the second

the mand then loads the address of the start of the interrupt processing program, which consists of the command to send the CPC from register 23 to the stack to the place of the contents of the command counter and the command to exit from the interrupt:

MOV RG, +2 (SP) RTI (RG - register address 23).

In order to extract the contents of register 23, the computer processor over the bus 24 programmatically transmits the address

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After the appearance of this address on bus 25 (FIG. 5), it is recognized by decoder 18, at the output of which an O signal appears, arriving at the first input of the element OR 22. When an ENTER signal appears on line 27, which arrives at the second input of the element OR 22, the O signal appears at its output - a read signal from register 23.

When the address of the interrupt-exit command (KOP8pr) appears on the bus 25, the third output of the decoder 16 causes an O signal to arrive at the first input of the OR-NOT element 19. The command start signal of the line 28 goes to the second input of the OR-19 element On the front of the signal from the output of the element OR NOT 19, the trigger 15 is set to one, since the level 1 interrupt signal arrives at its information input. At the inverse output of the trigger 15 at this moment the signal O appears, which is fed to the blocking input adder 3. In this case the second information input of the adder Z is blocked; its information output is transmitted from the first information input of the adder 3, i.e. register information 5.

On the front of the signal from the output of the OR-NOT 19 element, the first pulse shaper 20 generates a signal 1, which triggers the trigger 6 (the interrupt signal is removed) through the element OR-NOT 10. The computer processor is output from the interrupt and control occurs at the CPC address, 1, i.e. re-executes the i-command, during the execution of which the failure occurred. When the KOP J bus appears on the 24th bus, the output of the adder 3 remains the COP, 1, since the adder 3 is blocked by the second

916

the information input from block 2 is read by the address given on bus 25 - KS. In this case, at the output of the comparison circuit 4, the signal O and the trigger 6 are not set to one, then a write signal is generated in the register 5 (entered by KCj from the output of the adder 3) and in register 23 (the CPC address | is entered). On the front of the write signal of registers 5 and 23, the second pulse shaper 21 generates a level 1 pulse, which triggers trigger 15 through the W-NOT-17 element, and the blocking signal of the adder 3 is picked up.

If the address on the bus 24 does not result in the address of the next CPC and the address of any data, then in this case a zero code will be read from block 2 and comparing this zero code with the information from the output of the adder 3 will also be recorded a failure.

Thus, the proposed device makes it possible to recognize the failure in the equipment of the controlled computer and to restore the computational process by fixing the fact of failure and re-executing the command, during the execution of which the failure occurred.

Claims (1)

Invention Formula A device for controlling a control computer that contains two blocks of permanent memory, an adder, a comparison circuit, two registers, three triggers, a delay element, a decoder for the transition commands, an address decoder, two pulse drivers, an OR element, and the information inputs for the transition command decoder, the address decoder and the first register, the address inputs of the first and second blocks of permanent memory are connected to the address input of the device for connecting to the address of the controlled computer, the outputs of the first block of permanent memory and the first Registers, first information input of the adder are connected to the information output apparatus vhodu- podklyueni computer controlled to the data bus, the information output of the adder is connected to the data input of the second register, whose output is connected to second data input of an adder, a direct output of the first flip-flop ten Q280 is the interrupt output for connecting to the control bus of the monitored computer, the input of the device for connecting to the control bus of the monitored computer is connected to the first input of the OR element, the second input of which is connected to the output of the address decoder, the output of the OR sub jQ key to the read input of the first register, the first the output of the transition instruction decoder is connected to the information input of the second trigger; the output of the comparison circuit is connected to the information input of the first trigger, characterized in that, in order to reduce the time tim fixing SRB, it is further introduced seven elements NOR, NAND, 20 wherein the first information input of the comparison circuit is connected to the output of the second block of the permanent memory, and the second information input of the comparison circuit is connected to the outputs of the adder, the pack5 equaling the inputs of the first and second blocks of permanent memory, the first input of the first element OR is NOT connected to the input of the input of the device for connection to the control bus controlled 30 computer, to the input of the initial command of the device for connecting to the control bus of the controlled computer are connected the second input of the first element OR NOT and the first input of the second element OR NOT, the output of which is connected to the synchronization of the third trigger and the input of the first pulse shaper, the output of which is connected with the first input of the third element OR NOT, the second input 4 "of the third element OR NOT and the first inputs of the fourth, fifth and sixth elements OR are NOT connected to the input of the initial installation of the device, the direct output of the first trigger is connected 5 informational inputs of the third the trigger and the third input of the first element OR NOT, the inverse output of the first trigger is connected to the first input of the NAND element, the output of the first element OR NOT is connected to the input of the delay element, the second input of the fifth element. ment OR NOT, to the sync input of the first trigger, the zero input of which is connected to the output of the third element g OR NOT, the output of the first element OR NOT is connected to the single input of the second trigger, the direct output of which is connected to the first input of the seventh element OR NOT whose output connect5 SHI S SHA15 prerge lush PK18 FIG. 2 Fig4 J ICM "Oh Cvs "five 6