SU1267424A1 - Device for checking microprocessor program units - Google Patents

Abstract

The invention relates to computing, in particular, to test logic block devices. The aim of the invention is to increase the speed. The device contains a clock pulse generator 1, a divider 2 frequencies, a selector-multiplexer 3, a reference block 4, a test block 5, a memory block 6 of the control program, the first comparison block 7, the second comparison block 8, the selector 9 signals by duration, the display control unit 10, the display unit 11, the program progress control unit 12, the subprogram address register 13, the mode setting unit 14, two selector-multiplexer 15.16, the OR element 17.4 Il. (L with

Description

1 The invention relates to computing, in particular, to test logic block devices. The aim of the invention is to increase speed. Figure 1 shows the block diagram of the device; on league. 2 - a variant of the selector 9 for positive signals; in fig. 3 - a variant of building the program control unit 12; in fig. 4 is a variant of the display control unit 10. The device contains a clock pulse generator 1, a frequency divider 2, a selector-multiplexer 3, a reference block 4, a test block 5, a memory block 6 of the control program 1 1, the first block 7 and the second 8 comparison blocks, the selector 9 of signals according to the frequency range 10 control unit: display unit, display unit 11, program progress control block 12, subprogram register 13 addresses, block 14 for. Dani regime s, selectors-multiplexes 15 and 16, element SH-17, output Synchronization. The selector 9 of the signals in duration (Fig. 2) contains the input 18 of the Glitter, the diode 19, the resistor 20, the capacitor 21, the threshold element 22, the output 23. The program progress control unit 12 (Fig. 3) contains the output 24 of the interrupt 25 input signal 25 errors, address input 26 of the block to be tested, address input 27 of the reference block, input 28 and 29 of the start of the operation of the mode setting block 5, switch 30, element I 31, d encoder 32, triggers 33 - 35, indicator 36 of the first error, indicator 3 second error, 38 expiration indicator. The display control unit 10 (FIG. 4) contains elements AND 39, 40 of element OR 41. Pulse generator 1, frequency divider 2 and selector multiplexer 3 provide clocking of the reference and test blocks at low-high frequencies. The selector-multiplexer 3 is controlled by the operation mode setting unit 14. The reference and verifiable blocks 4, 5 are software devices such as a processor or microprocessor. The inputs and outputs of blocks 4 and 5 have the following purpose: tact input 4: output signals connected to the output of the selector-multiplexer 3; input of the first data line, connected with the output of the block 14 setting the operation modes (in this device it is used to receive bits of the initial address of the program from block 14, in real data processing devices it is used to receive data from subscribers); the input of the second data line connected to the output of the register 13 of the address of the subroutine (in data processing devices it is used to receive data from random access memory); the input of instruction bits connected to block 6 of the memory of the control program; interrupt input connected to block 12; the output of the trunk, which includes groups of information outputs, pulsed and potential signals, connected to multiplexer selectors 15 and 16; output of the address line connected to the program control unit 12 of the program progress with the multiplexer selector-. Block 6 of the memory of the control program is designed to store the program number 1 of the control. To read the contents of a particular cell of block 6, the address of the cell is sent from block 4 to its input. The comparison unit 7, together with the SHS 1 7 element, performs the function of the comparison scheme of the same output signals of the blocks 4.5. which is a common signal when a pair of sig.par is not compared. In addition, the result of one-by-one addition is output from block 7 to display block 11. Comparison unit 8 compares the current address of the control program with the synchronization address specified on the mode setting unit 14 and outputs a comparison signal to the display control unit 10. The selector 9 of signals, by duration, allows only those signals to exit, the dx1 of which exceeds the specified one. With short-duration signals, the capacitor 21 does not have time to charge to a level sufficient to trigger the threshold element 22. The diode 19 provides an accelerated discharge of the capacitor 21 after the end of the signal. The display unit 11 displays the error address, as well as the result of a stepwise addition of one3 output signals 4 and 5, to the error address or the specified synchronization address. The program control unit 42 responds to the error signal from the selector 9 and the fixed program addresses: the address of the error routine and the final address of the program. A possible construction of block 12 is shown in FIG. 3. When an error signal is received at input 25, trigger 33 is triggered via element 31. From output trigger 33, the signal goes to the first error indicator to indicate that the tested block 5 does not work, element 31 (output 24) is also given an interrupt signal for blocks 4 and 5, on which the interrupt program is started. If there is no signal at input 29 from block 14, then an error signal does not pass through the E 31 element, which makes it possible to analyze the testing of sections of the control program after an error. The decoder 32 identifies the address of the error subroutine and the address of the end of the control program by the contents of the address mains 26 or 27 (depending on the state of input 28, which controls the selection of the switching direction). When an error subroutine address is detected, the signal from decoder 32 turns on trigger 34, the output of which is indicated by a second error indicator. When an end-of-program address is detected from the decoder 32, a trigger 35 is turned on, which causes the validity indicator 38 to indicate the validity of the block being tested. Unit 10, depending on the operating mode specified on unit 14, UOOMWells an information input signal to the display unit 11 or on a signal not compared with unit 8. Subprogram address register 13. stores the starting address of the current subroutine. The operation mode block 14 is a set of toggle switches defining the operation mode of the device. The outputs of block 14 have the following functional purposes: the first output associated with the inputs of blocks 4 and 5 is for setting the initial address of the control program; a second output connected to the input of the selector-multiplex 3, is designed to enable clocking of blocks 4 and 5 at high and low frequency; the third output 24 connected to the input of the program control unit 12 is for setting the monitoring mode; the fourth and fifth outputs associated with the selectors 15 and 16, respectively, set the switching direction codes; sixth, the output is intended to set the address-. Sa synchronization to the input of block 8; the seventh output sets the block 10 display mode. The selectors-multiplexers 15 and 16 switch the group of output signals of the checked and reference blocks, respectively, into block 7 of sequential addition. The device works as follows. The principle of control of the tested block is based on comparing its output signals with the output signals of the reference block in the process of simultaneous processing by both blocks of the control program. A control program is a set of subroutines, each of which checks the correct execution of a certain group of commands (operations). The correctness of the result is verified by comparing the actual result with the predefined (reference) result. When comparing the results, the next subroutine is executed; in case of non-comparison, the transition is made to the Error subroutine. At the beginning of the subroutine, the starting address of the subroutine is sent to register 13, after which a group of checked instructions is executed and the correctness of the result is checked. Then, one of the operational registers of the monitored processor is sent the program address of the block of commands for checking the correctness of the result, which will be required later to indicate the address of the error detection program. The Error and Interrupt subroutines are a sequence. operations of transferring the contents of the internal (operational) registers of the controlled processor. At the end of the subroutine, the contents of the register 13 of the subroutine address are entered into the instruction counter, which provides a return to the subroutine that detected the error. As it will be; Below, the hardware part of the device provides the ability to indicate the result of the operation at any program address, therefore, the entered transfers to the Error subroutine enable the contents of the internal registers of the processor to be indicated at the time of the error.

The address of the subroutine is written to register 13 via the data bus of block 4 of one of the operations of transferring information from the set of operations of blocks 4 and 5 (for example, by sending a constant whose value corresponds to the address of the beginning of the subroutine). The transfer of information to the register 13 is accompanied by a signal on one of the address circuits of block 4. Only with this signal, information 1 is entered into the register 13.

The performance check of an object is performed at two frequencies: high (working) and lower, multiple to working. This is due to the fact that at a high clocking frequency on the selector 9 of the signals, reliable and false signals of inconsistency are indistinguishable due to the short duration of the output signals.

At the first stage, the object is checked at a low frequency.

Before starting the test on the block

14 modes of tasks are set codes. The initial address of the control program and the resolution of the selectors.

15 and 16 for the first group of the same signals of the test and reference blocks. By pressing the Start button (not shown), blocks 4 and 5 begin the execution of the control program from the address set on the bus of the 14 modes block.

Comparison unit 7, performing modulo two bitwise addition, produces a single signal for each of the bits if the values of the input signals of the corresponding bits do not match, i.e. at the moments of noncomparison of pairs of input signals. Element 17 OR combining outputs of all bits of block 7 will form a common noncomparison signal with noncomparison of any pair of input signals of block 7. The general noncomparison signal, if its duration exceeds the allowable dummy of false noncomparisons, passes through the selector 9 of signals in duration to blocks 10 and 12 as an error signal. If the duration of the general signal of incomparison is less than permissible, then it is not passed by the signal generator 9 by the duration. Block 10, by an error signal, generates a signal to input the result of bit comparison and the current address of the program in block 11.

Block 12 of monitoring the progress of the program by an error signal turns on the first error indicator and issues a signal

0 interrupts for blocks 4 and 5, according to which the program is started, where the contents of register 13 (the starting address of the current subroutine) is recorded in the command counter, at the expense of

5 of which there is a looping on the subroutine, which generates an error signal.

If no error signal is generated in any of the subroutines, then

0, the control program reaches the final a, the address, which is recognized by the program control unit 12 and generates a validity signal. When looping (if an error is detected), the execution of the rest of the control program can be checked by setting in block 14 the starting address following the looped subroutine. After checking the first group of signals of blocks 4 and 5, the control program for the remaining groups of compared signals that are connected via selectors 15 and 16 to block 7 is checked in a similar way;

The location of the malfunction is determined by the diagnostic dictionary in accordance with the information displayed by the display unit 1I. In addition, looping the program in a small area allows controlling the dynamic sharply output signals of individual elements of the tested block 5 using an oscilloscope or other device to more accurately locate the fault.

Claims (1)

It often happens that the cause of the malfunction arises before the moment of malfunction detection, and there is a need to determine the state of the reference and verifiable blocks at the preceding error points in time. To do this, in the mode setting unit 14, a toggle switch is set to set the display mode to the unit 10 according to the comparison signal from unit 8. In this case, in block 14, you can select the required program adc as the sync address and disable one of the selectors 15 or 16 for indication in block 11 by the dialed address of the group of signals of the stadium (if the selector 15 is turned off) or the block being checked (the selector 16 is turned off). So, if at the mode setting unit 14 the resolution of the first group of signals is turned on, only for the selector-multiplexer 15 (for the selector 16, the resolution is not included), then the output of block 7 will be transmitted from the first group of signals of block 5, since the input of block 7 is received information only from the selector 15 and the result of one-by-one addition will be equal to the input code. At the time of formation of a pulse by the comparison unit 8, i.e. at the moment of comparing the current address of the program and typed in the mode setting block 14, from block 10, a signal is output by which information from block 7 (in this case, a group of signals from block 5) is entered into the display unit I1. The comparison signal from block 8 can also be used to synchronize an oscilloscope, with the help of which it is possible to examine the signals of the elements of the checked block 5 at any place in the program. G. .. The second stage of the inspection of the object is carried out at a high operating frequency. In this mode, the operation of the object is controlled by block 12 without taking into account the error signal from the selector 9 by analyzing the address outputs 26 of block 5; In this case, the prohibition of the error and the connection of the address inputs 26 for analysis in block 12 is carried out by signals 29 and 28, respectively, from a block of 14 modes. In case of improper fulfillment of individual operations by the checked block, which is detected by software comparison in block 5 of the obtained results with predetermined ones, the block switches to execution of the subroutine error. The program control unit 12 designates the address of the error subroutine and indicates the second error. The Error subroutine organizes the program looping in the same way as the Interrupt program. When the tested block 5 is working correctly, the program reaches the final address and turns on the expiration indicator. The remaining units of the device in the second stage are working identical to the first stage. To increase the reliability of the control, you can specify on display 14 for block 10 the indication condition by the signal from block 8 and dial as the synchronization address of the address of the program checkpoints, verify by the indications of the display 11 that the program passes through these checkpoints. At the first stage of testing (at a low frequency), block 12 also recognizes the address of the error subroutine and, as a result, malfunctions that are not displayed on the output signals can be detected, which increases the reliability of the control. Using the program control unit I2 and the display unit 11, it is possible to verify the operability of the proposed device (self-test) without the checked unit 5, which is necessary after the device has been manufactured, during repair and periodic checks. The test is carried out similarly to the described high frequency test with the difference that the output 27 of unit 4 is analyzed; At the same time, unit 12 controls the program run, thereby checking most of the operations associated with the transformation of information. and internal shipments. The output signals are checked visually on the display unit 11 at certain program addresses, which are specified by the mode setting unit 14. Claims An apparatus for monitoring microprocessor-based software blocks, comprising a clock pulse generator, a reference block, a first comparison block, a display unit, the output of the comparison block connected to the group. information inputs of the display unit, characterized in that, in order to improve speed, a frequency divider, first, second and third selector-multiplexers, a control program memory block, a second comparison unit, a signal selector by duration, an indication control unit containing the first and second elements AND and the OR element, the subroutine address register, the OR element, the mode setting block and the program progress control block, the output of the clock generator connected to the first W1 information input and through the frequency divider - with the second information input of the first selector-multiplexer, the output of which is connected to the clock inputs of the reference and checked blocks, the output of the start address of the program of the mode setting block is connected to the inputs of the initial address of the reference and checked blocks, the start of the work of the task block modes are connected to the control input of the first selector-1 multiplexer, information and address outputs of the tested block are connected respectively to the first and second information inputs second selector-multiplexer whose output is connected to a first input of the first comparator blo ka, address and information yield of the reference block soedinesh. respectively, the first and second information inputs of the third selector-multiplexer, the output of which is connected to the second input of the first comparison unit, the address output of the reference unit, is connected to the input of the record register of the subroutine's address, the first input of the second comparison unit, and the first information input of the display unit and with the address input of the memory of the control program, the output of which is connected to the inputs of commands of the reference and verifiable blocks, the information output of the reference block is connected to the information input The subprogram address register, whose information output is connected to the address inputs of the reference and programmable G6 blocks, the first and second outputs for determining the direction of the switch, and the mode setting block are connected to the first control inputs of the second and third selectors-multiplexers, respectively, address the output and output of the resolution of the indication of the mode setting block are connected respectively with the second input of the second comparison unit and with the first input of the first element And with the inverse input of the second element And the control unit and indication, the output of the OR element of the indication control unit is connected to the control input of the display unit, the output of the second comparator unit is connected to the second input of the first element AND of the indication control unit and is the error output of the device, the outputs of the first comparator unit are connected to the inputs of the NL element, output which, through the signal separator, is connected to the direct input of the second element AND of the automation control unit through the duration of the separator, the outputs of the first and second elements AND of the display control unit are connected to the inputs of the element ШШ, program control unit contains a switch, an And element, a decoder, the first, second and third triggers, the first error indicator, the second error indicator and the validity indicator, the output of the beginning of operation of the mode setting unit is connected to the first input of the And element and to the control input the switch, the output of which is connected to the input of the decoder, the first and second outputs of which are connected to the single inputs of the first and second trigger, respectively, of the output element And connected to the single input of the third trigger of the progress control unit n RGT, interrupt inputs of the reference and the checked blocks, the address outputs of the reference and the checked blocks are connected respectively to the first and second information inputs of the switch of the program’s progress control block, the outputs of the first, second and third triggers of the program code control block , the input of the indicator of the first error, the input of the indicator of the second error, the output of the signal selector is connected to the second input: the element AND of the program control unit. J8 26 thirty 32 27 2J 22  2 / (rig 2 Error 2 | J7 J " Fit 35 38 fi.Z From djfPKO§ 33 From the ify block O t block 9 4G H a block f g one (put. 4