SU1702370A1 - Microprogram control device with checking - Google Patents

Abstract

The invention is related to computer technology and can be used in functional diagnostics systems of a PAC. The purpose of the invention is to increase the reliability of the control. The device contains a micro-command memory block, two counters, a micro-register, a shift register, two multiplexers, a switch (addresses), a decoder, a comparison block, two modulo-two adders, a synchronization block, four triggers, four OR elements. three elements I. The purpose of the invention is achieved through the implementation of microprogram start correctness control, parity control, and control by comparison with a reference signature. 6 ill., 1 tab.

Description

The invention relates to computing and can be used in functional diagnostics systems.

The purpose of the invention is to increase the reliability of the control.

The essence of the invention is to increase the reliability of program control by providing three types of control. The first one is to control the correctness of the beginning of the program from the first microcommand due to the presence of a code combination (filling in the 1 field of the logic condition code) in the first micro instruction. At the beginning of a program with any other micro-command, the absence of a code combination will be the source of the error signal. The second, the parity check, is implemented using a special check bit contained in the microinstruction, which supplements the quantity 1 in

microinstruction to even. Odd number 1 is the source of the error signal. The third is the control by comparison with the standard. This control is random. Its essence lies in alternately switching the outputs of the inspected bits with a group of elements that, depending on the values of these bits, form a special control code combination - a signature and compare it with the reference code contained in one predetermined micro-command.

FIG. 1 shows a functional diagram of the device; figure 2 - the timing diagram of the work in the absence of errors; in fig. the same, with an error in the first microinstruction; figure 4 - the same, with the error control on parity; figure 5 - the same, with an error recorded in the control

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signature; 6 shows a variant of forming a control signature.

The device (Fig. 1) contains block 1 of a set of micro-commands, counters 2 and 3, register 4 micro-operations, register 5 shift, multiplexer b (logical conditions), multiplexer 7 (checks), switch 8 (addresses), decoder 9 ( such as a microcommand), block 10 of comparison, adder 11 modulo 2 (two). adder 12 modulo 2, synchronization block 13, trigger 14 (start), trigger 15 (program start control), triggers 16 and 17 (errors), first 18, second 19, third 20, fourth 21 OR elements, AND NOT element 22 the first 23, the second 24 elements And, the input 25 start, the address input 26, the input 27 of the logic conditions, the output 28 micro-operations, the first 29 and the second 30 outputs of the device error signals.

The decoder 9 is designed to decrypt the code coming from the outputs

1.1 and 1.2 blocks 1 of memory of microinstructions. The relationship between the signals at the outputs 1.1 and

1.2block 1 of the microinstructions memory and at the outputs of the decoder are represented by a table.

Block 10 is used for comparison in the presence of an enable signal from a decoder of the microcommand type of the control signature with a reference one and, if there is a mismatch, a signal is issued on the error trigger.

Modulo 2 adder 11 is designed to generate information for the signature register. Modulo 12 modulo 2 checks the microcommand for parity. Unit 13 synchronizes the operation of the device. The trigger 14 starts the block 13, the trigger 15 is designed to issue an error signal when the microprogram starts not from the first microcommand. Triggers 16 and 17 are designed to generate error signals at the output of the device during parity checking and comparison with the standard, respectively. The element OR 18 serves to modify the low-order bit of the address of the next microcommand. The OR element 19 stops the device, flips the trigger 14 when an error is detected, the OR element 20 generates a control signal for multiplexer 7. The OR element 21 commutes multiplexers 6 and 7 with the input of the accumulator 11. The IS-NOT element 22 generates an error signal and sends it to the informational trigger input 15. Element AND 23 supplies or blocks clock pulses to counter 2.

Element And 24 is intended to form a signal at the input of counter 3 and increase its contents by 1 when processed by the device of the final microcommand in the group of linear microcommands.

control the start of the program, when in the code field of the logical condition of block 1 there is at least one O when forming the first micro-command

Figure 6 shows a variant of forming a control signature by means of register 5 and adder 11. To create a signature, bits of fields of logical conditions, addresses, can be used.

micro-operations of block 1 of micro-operations memory and logical conditions from the input of 27 logical conditions of the device.

The proposed control device with control works as follows.

At the output of block 1, in the initial state, there is a microinstruction determined by the zero address of the counter 2 address, which is in the initial state. At the output of register 4 in all categories except QC

generated zero signal. As a result, the output QC opens the switch 8 to the input 26 of the device. The remaining memory elements are reset (the reset circuit is not shown). On the Start command, the trigger 14 is transferred to one state and starts block 13. On the first clock pulse, the address of the first microcommand from the device input is written to counter 2. The first microcommand is called from this block 1. Depending on the contents of the required field of labels 1 and 2 of block 1, the decoder 9 generates a control signal at one of the four outputs.

4 variants of microinstructions are possible.

Linear - 1 at the zero output of the decoder.

Through the element OR 20, a control signal is supplied to multiplexer 7. Multiplexer 7 at the address contained in the field

the logical condition code of block 1, switches the corresponding checked bit through the element OR 21 to the input of the adder 11; the first pulse Tg in the register 4 records the micro-operation code. amount

 1 in the field of tags, logical conditions, address, check bit of block 1 and at the output of register 4 in the total must be even. Otherwise, the adder Generates an error signal; In this way, the parity check is performed. In the field of the logical condition of the first microcommand of block 1, all bits must be single. If the firmware did not start with the first micr command, then And 22

a single signal is generated and when changing information in register 4 in trigger 15, 1 is written - an error signal. In this way, the correctness of the start of the firmware is monitored. Parity and firmware start are performed regardless of the type of microcommand. The zero signal at the output of QC switches the switch 8 addresses to the internal input. The input of the counter 2 is supplied with the address of the next microcommand from the address field of the microcommand memory block 1. On the first Gz pulse, the control signature corresponding to the first micro instruction is written to register 5. On the second impulse n, the address of the next micro-command is recorded in counter 2 and further, with the exception of monitoring the start of the program, the process will go the same way.

To reduce the amount of memory allocated for the verification code, which is written in the logic field of a linear microcommand, a microcommand is entered. The end of the group, which differs from the linear one, is that the signal removed from the fourth output of the decoder by pulse P (corresponding to the beginning following the microcommand The end of the next microinstruction group adds 1 low-order bit to counter 3, which forms the high-order bits at the address input of multiplexer 7. Otherwise, the operation of the device according to this micro-instruction corresponds to linear.

If it is necessary to branch the microcommand, the outputs 1.1 and 1.2 of block 1 organize the control signal at the second output of the decoder 9. Which is the control for the multiplexer 6. The corresponding external logical condition is switched by the logic condition code from block 1 to the address input of the multiplexer to the input of the element OR 18, to modify the least significant bit of the address of the next microcommand, and also through the element OR 21 to the input of the adder 11, and the pulse signature is written to the shift register 5 by the pulse g Dr. showing an logical condition. Further, the scheme works in a similar way.

Upon receipt of the reference command, a control signal appears at the first output of the decoder, which counter 2 of the address from the register operation mode switches to the counting one and turns on the comparison unit 10, to which the reference signature is fed from the address field of block 1 and the control from the shift register. A signature corresponding to the reference team itself is not generated. If there is a mismatch, block 10 generates an error signal. According to the sync pulse ri corresponding to the beginning of the next microcommand, the 1 is added to the low-order bit to the contents of counter 2.

The error signal from block 10 blocks the arrival of clock pulses to counter 2, freezes the program on an erroneous microcommand, and also triggers 16. In turn, the signals from the outputs of the trigger 16, 17 and trigger 15 through the element OR 19 form the Stop signal to the zero input of the trigger 14 and the stopping unit 13. When the last microcommand in the microprogram is processed, a single signal at the output of the RC register 4 through the OR 19 element zeroes the trigger 14.

Claims (1)

Invention Formula 5 A microprogrammed control device with a control containing a microinstruction memory block, a micro-operation register, a first multiplexer, a switch, a synchronization block, first and second triggers, 0 first element OR. the device start input is connected to the installation input of the first trigger, the output of which is connected to the start input of the synchronization unit, the output group of the micro-operation code of the memory unit 5 microinstructions are connected to a group of information inputs of the register of micro-operations, the group of outputs of which is a group of outputs of the device micro-operation code, the output of the end of the register command 0 microoperations are connected to the control input of the switch, the output group of the unmodifiable microcommand memory block address bits is connected to the first group of information inputs of the commutator, the output group of the logic code conditions of the microcommand memory block is connected to the address group of the first multiplexer whose information inputs are is a group of inputs of the logical conditions of the device, the output of the end of the operation of the register of microoperations is connected to the first input of the first OR element, the output of which is connected to the input House first reset flip-flop, a first output of block 5 synchronization is connected to the clock input of the register of micro-operations, the group of address inputs of the device is connected to the second group of information inputs of the switch. torus, the output of the second trigger is connected to 0 by the second input of the first element OR. characterized in that, in order to increase the reliability of the control, a shift register, two modulo-two adders, a decoder, a comparison unit, are entered into it, 5 second multiplexer, two elements I. element NAND. the second, third and fourth elements OR, the third and fourth triggers, two counters, with the group of outputs of the switch connected to the group of information inputs of the first counter, the group the bit outputs of which are connected to the group of address inputs of the microinstructions memory block, the output of the NAND element is connected to the information input of the third trigger, the second output of the synchronization block is connected to the direct input of the first and the first input of the second And elements, clock inputs of the second and fourth flip-flops, the output of the modifiable bit of the address of the microcommand memory block is connected to the first input of the second OR element, the output of which is connected to the third input of the switch, the first output of the decoder is connected to the first input of the third About the OR element, the output of the first mux multiplexer is connected to the first input of the fourth OR element and the second input of the second OR element, the third output of the synchronization unit is connected to the clock input of the shift register, the output group of which is connected to the first input body of the comparison unit and modulo two, the input of which is connected to the output of the fourth element OR, the second input of which is connected to the output of the second multiplexer, the resolution input of which is connected to the output of the third element OR. the second output of the decoder is connected to the resolution inputs of the comparison unit and the first counter, the third output of the decoder is connected to the resolution input of the first multiplexer, the fourth output of the decoder is connected to the second inputs of the second element AND and the third element OR, the output of the second element AND is connected to the clock input of the second counter , the clock input of the third trigger is connected to the output of the end of the micro-register command, the output of the third trigger is connected to the third input of the first OR element, the output of the fourth trigger is connected the fourth input of the first element OR is the second output of the device error signal, the information input of the fourth trigger is connected to the inverse of the first element AND and connected to the output of the comparator unit, the output of the first modulo-two is connected to the information input of the shift register, the information input of the second trigger is combined with the second inverse of the first element And and is connected to the output of the second modulo two, the output of the first element And is connected to the clock input of the first counter, information the inputs of the second multiplexer are connected to the outputs of the unmodifiable and modifiable address bits and the outputs of microoperations of the microinstructions memory unit; the second group of inputs of the comparison unit is connected to the outputs of the address bits of the microinstructions memory unit; the address inputs of the second counter and the outputs of the logic code the microinstructions memory block, the inputs of the NAND element are connected to the outputs of the logic code code of the microinstructions memory block, the micro-register register outputs and the bit outputs code logic conditions modifiable and non-modifiable address bits and an output control unit discharge microinstruction memory are connected to inputs of the second adder of modulo two, yields bits labels microinstruction storage unit connected to the inputs of the decoder. oley Fig.Z FIG L FIG. five 4S 3 ft