SU1758634A1 - Programmed control module with checking - Google Patents

Abstract

The invention relates to the field of digital computing and automation and can be used in the construction of software control systems with increased reliability of operation on the basis of modular microprogramming control devices. The essence of the invention is to increase the reliability of the functioning of the software module

Description

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This invention relates to the field of digital computing and automatics. It can be used in the construction of software control systems with enhanced function based on modular microprogrammed control devices.

The aim of the invention is to increase the reliability of the operation of the software module as part of the control of the 20 l of the system by providing the possibility of self-diagnosis. Reliability of functioning increases by 10-90X.

FIG. 1 shows a functional diagram of a software control module with a control; in fig. 2 - functional argatation scheme of the proposed program modules into the control system; in fig. 3 is a time diagram of the sequential operation of two control modules of the system; in fig. 4 illustrates the types of MK formats used in the module; in fig. 5 - an example of the interaction of 35 diagnostic firmware of two modules in the short test mode; FIG. 6 shows a long check procedure for a system of three control modules. 40

The program module contains: a memory block of 1 micro-commands (BPM) with outputs of fields 1.1 labels M1, 1.2 labels M2, 1.3 addresses of the next MC, 1.4 codes of logical conditions (LU), 1.5 codes, 45 micro-operations, register 2 addresses of the MC , register 3 microoperations, multiplexer 4 addresses, multiplexer 5 LU, demultiplexer 6, register 7 exit from the cycle, register 8 checks, counting 50 hours 9 pulses, decoder 10 with the first 10.1 and second 10.2 outputs, 1K trigger 11, trigger 12 type of test, error trigger 13, comparison circuit 14, switch 15, block of elements OR 16, element 17, element I-NP 18, input code 19 module commands, input 20 LU module, first 21, third 2, second 23 PU.ODY synchronicity

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45 50 n-,

module, output 24 micro-operations of the module, group transfer control input 25 of the module, module control transfer output 26, module error output 27, output 28 of the lower bit of the field 1.3 of the address M1 BPM 1, input

29 module error reset, 30 - clock generator.

As part of the control system, the software module works as follows. The module can be in the following modes:

1) Standby mode;

2) Working mode;

3) Short check mode;

4) Long check mode;

5) Control transfer mode.

The initial position of the module corresponds to its standby time. In this case, all the memory elements of the module are set to the zero state (the circuit for setting the initial conditionally is not shown). The inputs 21, 22, 23 of the module receive, respectively, the sequences of clock pulses shifted relative to each other, Ј, / s, fcj

from the corresponding generator outputs

30 ticks (smfig. 3).

From the output, BPM 1 reads a MC with a zero address (F1 format MC, see Fig. 4). The multiplexer 4 addresses on a single signal Ml labels from output 1.1 BPM 1, passes to the input register 2 addresses or the operation code from the input of the 19th module, or the address code from one of the inputs of the group input of the 25th module from one of the other modules of the system. As long as these codes are zero, registers 2 and 3 are clocked by Ј, and Ј2, and zeroes are overwritten and the state module does not change, т we. waiting. The simultaneous arrival of non-zero codes on the second and third group of information inputs of multiplexer 4 addresses is eliminated by the system operation algorithm.

Let the input code 19 of the modup receive the code of the command requiring the execution of the Kots command is the address

The first MK of the command, it is recorded in register 2 on the falling edge of the next clock pulse Ј from the input 2 of the module. The module goes into operation. Let the first IR be linear (F2 format, see Fig.4). At the same time, the signals of the labels M1, M2 are zero, and the microprocess code, which is then read from the input 24 of the module, is recorded at the falling edge of the next clock pulse Mo of the input 23 of the module into the register 3. The multiplexer 4 addresses with zero address signals transmits to the input of register 2 the high-order bits of the address code from the output field 1 „3 BPM 1 and the signal from the output of the multiplexer 5 LU. The multiplexer 5 LU but the zero LU code from the output of the floor 1.4 BPM 1 transmits to its output a signal of the lower order address of the next MC command from the output 28 output of the floor 1.3 BPM 1 Thus, for the next clock import it will write to register 2 The address of the next command MC is the same as the code at the output of field 1.3 BPM 1. The remaining module elements do not change state when the O2 format MC is executed. The implementation by the G branch module (the FZ format) differs from the linear MK implementation only in that the lower-order bit address of the next MC will be determined in multiplexer 5 by the LU whose code entered its address input. If the LU value is zero, then the lower-order d addresses the next MK zero, i.e. coincides with the value of the corresponding bit at the output of 28 field 1 ± 3 BPM 1. If the value of the LU is not zero, then the value of the lower bit of the next MC is determined by the multiplexer 5 of the LU as single. The modular execution of any linear MK and MK branching in the operating mode is carried out as described above.

After working its part of the algorithm, the module transfers control to another, for example, a module of the system. But before that, he checks his operability, the transition to the short mode, that is, a single-module test (om.fig, 3). The module enters this mode from the moment of recording in the register 2 of the address of the MC with the F4 format. A single signal of the M2 tag from the output of the field 102 of the BPM 1 is fed to the I-input of the 1K-trigger 11, to the control inputs of the trigger 12 of the check type that allow the recording,

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register 7 out of cycle and 8-checks, as well as the zero input of register 3 micro-operations. Multiplexer 5 LU by zero code LU from the output field 1.4 BPM 1 passes to its output the value of the signal from the output 28 low-order control address code from the output field 1.3 BPM 1. To implement a short check, the value of the low bit 1.3 field BPM 1 in F4 format MK is programmed zero. Thus, at the information input of the trigger 12 of the test type, there will be a zero signal from the output 28 of the field 1.3 of the address BPM 1, which determines that the test will be short. On the leading edge of the next clock pulse ЈЈ from the input 22, the module 1K-trigger 11 translates into a single state. On the falling edge of the same pulse, the exit control register MK of the checked module (MF of the FB format) is written in the loop exit register 7, an even control address code is written to the check register 8. The trigger 12 of the check type remains in the zero state. A single signal from the output of the IK-trlggera 11 allows the counter 9 to operate in the counting mode. On the trailing edge of the next clock pulse Јj, the contents of counter 9 are incremented by one, and the contents of register 3 of micro-operations do not change, i.e. remains zero At the next clock pulse, the short address control address code is written to the address register 2. According to this code, the F5 format MK is read from BPM 1 (see Figure 4). This is the first MK checking the i-th module. The single signal of the Ml tag from the output of field 1.1 of BPM 1 enables the demultiplexer 6 to work. By the same signal, the multiplexer 4 addresses forms a zero address code at the information input of the register 2; and on the second and third information inputs of the multiplexer 4 codes are zero. From the output of field 1.4 BPM 1, the code of the number of the module under test is fed to the address input of the demultiplexer 6, i.e. b. binary code of i. Using this code, the demultiplexer 6 passes the control code for the 1st module address code from the output field 1.3 of BPM 1 to the output of the group output 26 of the module corresponding to the i-th module. This code goes further to the input of the 25th 1-th module corresponding to the module in question, which As for all idle modules of the system, it is in standby mode. The multiplexer 4 addresses of the 1st module by the single signal of the M1 tag at its first address input passes the control address code from the output of the block of elements OR 16 to the information input of the register 2 addresses By the next clock pulses of the CS3 neither in the considered nor in the i-th The module does not make any changes, except for the next increase in the considered module of the contents of counter 9 by one. On the next clock pulse V, the control address code generated by the considered module is written into the register 2 of the 1st module. In register 2 of the module under consideration, using the same pulse, a zero code is written. From the output of BPMM 1 of the module in question, the null MK (F1 format MK) is read, while the multiplexer 4 addresses then passes the address code from the output of the block of elements OR 16 to its output, since at the input 19 of the module, the command code at this moment should be absent. From the output of BPM 1 of the 1st module, if there were no distortions, the L50 format MK is read. In its 1.4 field, the code of the module under consideration is written, and the control address code is inverted to the 1 „3 field.

code stored in the register 8 checks the module in question. The procedure for executing the F5 format MC has already been examined in detail, the i-th module transmits the control address code from the output field 1.3 of its BPM 1 to the input of group input 25 of the module in question corresponding to the i-th module. By the next clock pulse QJ, the counter 9 in the module under consideration increases the content by one. By the next clock pulse Ј, the control address code generated by the i-th module is written into register 2 of the module under consideration, and the i-th module by the same -multiply Ј switches to standby mode. If the control address code from the i-th module is written to register 2 of the module in question without distortion, then the second module of the check of the 1st module starts reading from the BPM 1 test of the module in question. This PC is also OZ format. Its difference from the first MC is only in the control address code written in the 1.3 field, which is inverse to the similar code in the 1.3 field of the first MC of the 1st module (cMofi 5). The implementation of the second module MK checking the 1st module with the module under consideration, followed by the transition to the standby mode, the reaction of the 1st module to the second control address code from the module in question is similar to that described. If there are no distortions in the transmission of control codes and the operation of the modules, the second response control address code generated by the ith module for the module in question must match the control code stored in check register 8 in the module in question. The control address code generated by the i-th module, in response to the second check module of the 1st module read from the module in question, comes from the corresponding input of the group input 25 of the module to the information input of the register 2 address and the second group of circuit inputs 14 comparisons (from the output of BPM 1 of the module under consideration at this moment is read out by an F1 format MC) "The next clock pulse increases the contents of counter 9 in the module under consideration up to the critical value of the Ukr.kor corresponding to the short drive mode Verka. The decoder 10 when it arrives at its input from the output of the counter 9 code corresponding to the Ukr.kor ,, forms a single signal at its first 10 output. When the short test is triggered in the zero state, the output 12 of the switch 15, with the appearance of a single signal at the output 10.1 of the decoder 10, also appears a single signal — a signal Verification. This signal arrives at the K-input of the 1K-flip-flop 11, the first input of the And 17 element, the second address input of the multiplexer 4 of the address, the second input of the element 18 and the error-triggering input of the trigger 13 of the error. Multiplexer 4 addresses by signal Check at its second address input pass to the input of register 2 the address code from the output of register 7 to exit from the loop. The control address code from the 1st module from the output of the block of elements OR 16 multiplexer 4 addresses at the end

The short check is ignored. If the second control address code from the 1st module does not match the control address code in check register 8, then the comparison circuit 14 at the time of the occurrence of the signal Check 1 will generate a zero signal. In this case, the element ECHNE 18 will form a single signal at its inverse output,

which with a single signal indicates an error resulting from a diagnostic procedure. On the next clock pulse Ј, in the event of an error, the next 15 seconds will occur. The error trigger 13 will be recorded by the unit from the output of the NAND 18 element. The register 2 will write the address code for the exit from the test cycle stored in register 7. However, register 2 will be 20 immediately reset by the error signal received at the R input of register 2 from the trigger output 13 error. The error signal from the output of the trigger 13 will also go to the output 27 of the error of the module under consideration, informing about the unsuccessful outcome of the test. The considered engine hangs in this state until the malfunction is corrected and repeated

start. The flip-flop 13 is reset to zero-state after the elimination of incomparability is performed by the signal from the input 29 of the module error reset.

If the verification error did not occur, then after the switch 15 generates a signal Check, by the next clock pulse, a zero signal from the output of the AND-NOT element 18 will be written to the trigger 13 error, and write to the register 22 from the address code from the register 7 output Exit game cycle check.

With any outcome of the 1st test

module in turn clock pulse l.

su, Ј the flip-flop 11 is zeroed, which indicates the end of the test and prohibits further operation of counter 9, in addition, the element 17 also generates a short impulse for this impulse, embedding the counter 9 and the output register 7 of the cycle.

If the error trigger 13 has remained in the zero state after a short check, i.e., the 1st module is ready to take control of the considered one, then from the moment the address code stored in register 2 is stored in register 7 exiting the irokerka loop, the considered module goes to mode

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control transfers to the i-rry module. For this address code, the IC of the BPM 1 is read into the NC format. Its implementation is similar to the implementation of the module MR Lormata F5. The difference is only in the following. The i-th module is not transmitted the control address code, but the control address code (ACC). In addition, by the next pulse of the register of micro-operations 3, the last micro-coding code from the module under consideration can be recorded, which can inform the control object of the system about the transfer of control functions to the i-th module. Note also that when the PC executes an FB format, in contrast to an F5 formatted IC, a 1K-trigger 11, a check trigger 12, a counter 9, a check register 8 and an exit from the test cycle are in the zero state. On the next clock pulse $ (a zero code will be written to register 2 of the module in question, ACU will be written into register 2, the ACU will be written to the i-ro module. The module will go into standby mode, and the i-th module will go into operation mode, i

Each module of the system contains s BPM 1 firmware of its operation in the long test mode. The controlling system enters this mode from the moment of recording in register 2 of any of its modules the address of the MC to transition to this mode. Such an MK has an F4 format. An example of long-term diagnostic firmware and their interaction for a three-module control system is illustrated in Fig. 6. In this case, the diagnostic firmware in each module consists of two MCs. All these MK have F5 format. The implementation of the MC for transition to the long test mode is similar to the implementation of the F4 format MC in the short test mode described earlier. The only difference is that in field 1.3 of the MK of F4 format with a long check, the control address code must be odd, i.e. its least significant bit must be single. In this case, the trigger 12 will be checked by the next impulse Ј2 one, and not zero as in the short test. A single signal from the output of the trigger 12 will allow the switch 15 to form a single signal. Check only after a single signal from the second 1002 output of the decoder 10 arrives at it.

In the long test mode, all modules of the system alternately, over a closed chain, exchange control address codes with each other. However, if during a short check the control address codes are exchanged twice, then with a long check only once. After each module is exchanged with all other JQ modules of the system with control address codes, since the chain is closed, the last transmission of the control address code in the absence of an error should occur in the t5 module, which initiated a long check. Moreover, this last control address code should be the ad / res of the first F5 MK format, from which | the swarm began a long check. This 20 code is stored in register 8 of the check of the initiating module where it was recorded when implementing the MC to switch to the long check mode. At this moment, when the initiator of the length test must come to the module with the last control address code, the decoder 10, using the code from the output of counter 9, generates at its output 10.2 a single signal by which the switch 153

generates a single signal Check. Further, the operation of the system module is completely similar to the operation of the module after generating a signal. Test in the short test mode The initiator module 3 of the long test either generates an error signal and hangs until the faults are eliminated, or exits the test cycle at the address stored in register 7.4

Claims (1)

Invention Formula v.45 A software control module with a control, which contains microcommand memory blocks, address and microcommand registers, address and logical conditions multiplexers, a demultiplexer OR block, and the output of the 111 label field of the microcommand label is connected to the control input of the demultiplexer 50 plexer and the first the address input of the address multiplexer, the output of which is connected to the information input of the address register, the output of the low-resolution bit of the address field of the micro 55-command memory block is connected to the low-order bit of the information input of the multiplexer logical conditions, the output of which JQ t5 20 25 30 . 35 40 .45 50 about 55 is connected with the low-order bit of the first group of information inputs of the address multiplexer, the output of the high-order bits of the address field of the micro-instruction memory block is connected to the high bits of the first information input of the address multiplexer, the output field of the address of the micro-memory block is connected the multiplexer whose outputs form the group transfer control output of the module, the output of the field field of the logic code code of the microcommand memory module is connected to the address inputs of the logic multiplexer condition and dem the multiplexer, the input of the logical conditions of the module is connected to the higher bits of the information input of the multiplexer of the logical conditions, the group input of the transmission of the decrease of the module forms the group of inputs of the block of elements OR, the group of outputs of which is connected to the second group of information inputs of the multiplexer of the address the multiplexer addresses of the address, the output of the register of the address is connected to the input of the microinstructions memory block, the output of the microoperations floor of which is connected to The micro-operations register’s first input, the module’s first and second synchronization inputs are connected to the address and micro-ops registers, respectively, the output of the micro-ops register is the output of the micro-ops of the module, in order to increase the reliability of its operation as part of the control system enable self-diagnostics, it further contains a loop-out and check registers, a pulse counter, a decoder, a 1K trigger, test types and error triggers, a comparison circuit nor, the switch, the AND – NES elements, and the output of the microoperations micro-operations floor of the micro-commands is connected to the information input of the register, exit the cycle, the output group of which is associated with the fourth group of information inputs of the address multiplexer, the output fields of the M2 tag and the address of the memory block These micro-instructions are connected respectively to the control and information input of the check register, whose output group and the output group of the OR block are connected respectively to the first and second groups of inputs of the comparison circuit, the output field The M2 tags of the micro-command memory module are connected to the control inputs of the check type trigger, the cycle exit register, with the embedding input of the micro-operations register and the I-input of the 1K-trigger, the output of which is connected to the control input of the pulse counter, JQ the second synchronization input of the module is connected to the counting input of the pulse counter, the output of which is connected to the input of the decoder, the first and second outputs of the decoder are connected respectively to the first and second information inputs of the switch, the output of the lower bit address field block in the memory of microinstructions, it is connected to the information input of the check type trigger, the JQ output of which is connected to the first inverse and second direct control inputs of the switch, the output of the switch is connected to the second address input 25 the address multiplexer, with the control input of the error trigger, with the K input of an IK trigger, with the first input of the AND element, the output of which is connected to the outgoing inputs of the counter and the loop out register, the outputs of the comparison circuit and the switch are connected respectively to the first and second inputs of the NAND element, the output of which is connected to the error trigger information input, the module error reset input, is the zeroing input of the error trigger, the output of which is connected to the zero address input of the address register and the error output of the module, the third sync input the module is connected to the second input of the And element and the synchronous inputs of the loop out check registers, the IK trigger, the check trigger type, the module’s first synchronization input is connected to the error trigger trigger input 7G98Sh 4 Spreader (j, -u) module i-u module FIG. five I Start 2nd module I 3rd module. I i i FIG. 6