SU1310776A1 - Device for programmed control and checking of cyclic process - Google Patents

Abstract

The invention relates to automation, in particular to software control systems, and is intended to control cyclic processes in an ACS. The purpose of the invention is to increase the reliability of control and expand the field of application of the device. The device contains a pulse generator, a frequency divider, a first time driver unit, a set of programs, an executive unit, an alarm unit, a zero unit, an AND block, an end sensor block, the first OR block, a first delay element, the first And block, a second time master unit, control register unit, signal fixation register unit, comparison unit, multiplexer unit, address counter, cipher. RATOR, decoder, second and first RS-flip-flops, block of elements OR, third element OR, second element SH, element OR-NOT, second, third, fourth, fifth and sixth elements AND, second delay element. The device has to control the work of the executive bodies both with an arbitrary and with a predetermined sequence of the end of their functioning. 6 Il. (L 05

Description

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The invention relates to automation, in particular to software control systems, and is intended to control cyclic processes in an ACS.

The purpose of the invention is to increase the reliability of the control device by providing full control, the entire time interval of the executive bodies, and fixing the end time of their work and expanding the scope of the device by introducing control over the order of completion of work by the executive bodies.

Fig, 1 2 shows a functional diagram of the device; FIG. 3 shows a block of a set of programs; figure 4 - diagram of the time of the master unit; figure 5 is a block diagram of the alarm; Fig, 6 - timing charts of the device.

The device for software control of cyclic processes (Fig. 2) contains a generator of 1 pulses, a divider 2 frequencies, a first time master unit 3, a block 4 of a set of programs, a block of 5 executive bodies, a block 6 for signaling and recording failure (failure), a block 7 zeroes, block 8 of elements AND, block 9 of sensors of the end of operations, first element OR 10, first delay element 11, first element 12, second time master unit 13, control register block 14, block of signal fixation registers 15, comparison block 16, block 17 multiplexers, counter 18 address , encoder 19, decoder 20, second RS-flip-flop 21 (start), first RS-flip-flop 22 control, block 23 of elements OR, third element OR 24, second element OR 25, element 26, second element AND 27, third element AND 28, the fourth element And 29, the fifth element And 30, the sixth element And 31, the second element 32 delay, input 33 Start, input 34 Stop the device, control input 35 of block 4 of the program set, first outputs 36 (group of control outputs) and p the third output 37 (label output) of block 4 of the program set, output 38 (group of outputs). the second time of the master block 13, the second 39 ;, the fourth 40 and t eti 41 outputs (respectively first and second groups and the group time code outputs kont62

role) block 4 of the set of programs, respectively, exit; 42 and 43 of the block 5 of the executive bodies and the block 9 of the sensors of the end of operations, respectively, inputs 44 are the counting inputs of the first 3 and second 13 time set-uifix blocks, output 45 (group of outputs) of the first time of the setting block 3, the first inputs 46 ( group information

the inputs of the signaling unit 6 are the second 47, the third 48, the fourth and the fifth 50 inputs and the output 51 of the signaling unit 6.

The program set unit 4 (FIG. 3) contains a memory 52 for storing a command code, a tag signal, a verification code, first and second time codes, an address counter 53 and a group of elements I.

Time master unit 3 (13) (figure 4) contains a counter 55, the elements And 56 and 57 and the element OR 58.

The alarm unit 6 (FIG. 5) contains a trigger 59, a block of elements I, an element WN 61, elements 62 of a light indication (LEDs).

The pulse generator 1 is designed to form pulses that synchronize the operation of the device. Frequency divider 2 is designed to reduce the frequency of impulses following at its input, and to generate signals used in the device for timing. The first time master unit 3 is designed to count the minimum operating time of the block 5 of the executive bodies for a given program. Unit 4 of the program set is intended for storing the work programs — unit 5 of the executive bodies and issuing signals 5 that check its operability. Block 5 of the executive bodies is intended to improve technological operations in accordance with their functional change. The signaling unit 6 is designed to register un-.

the correctness of block 5 executive bodies. The zeroing unit 7 is designed to stop the device when leaving the building block 5 of the executive organs or when applying

signal from the outside to the input Stop device. The block 8 of the elements And is intended to form control signals in the case when the executive bodies of the block 5 can okan313

work in any order. The block 9 of the sensors of the end of operations is intended to form signals at the end of work by the executive bodies of block 5. Element I 10 is intended to form signals for the transition to the execution of the next program.

The delay element 11 is designed to delay the transition signal to the execution of the next program.

Element And 12 is designed to ensure that the transition signal to the execution of the next program in the event of a malfunction of the block 5 of the executive bodies is not passed to the input of the program set block.

The timing of the master unit 13 is designed to count the minimum operating time of the block 5 of the executive bodies.

Block 14 of the control registers is intended to store a code defining the order in which the work is completed by the executive bodies of block 5, or a code defining which executive bodies of block 5 work according to a predetermined program and when the order of completion or work can be arbitrary.

The block 15 of the signal latching registers is intended to record the signals about the end of work by the executive bodies of the block 5, coming from the block 9 of the sensors of the end of operations.

Comparison unit 16 is intended for comparing the code corresponding to the executive body of unit 5 that completed the work with the code defining which executive body should have completed the work in a given sequence and generating signals informing about the compliance with this order or its violation.

The multiplexer block 17 is designed to sequentially read codes from the I4 control register block.

The address counter 18 is designed to set the cell address of the control register block 14, from which the codes are read.

The encoder 19 is designed to encrypt the state of the executive bodies of block 5. The decoder 20 is designed to decrypt the state

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the counter 18 of the address and the generation of the zeroing signals of the cell block 14 of the control registers. RS flip-flop 21 (start) is intended for starting and stopping the generator of 1 pulses. The RS flip-flop 22 (control) is designed to set the time interval during which the block 5 of the executive bodies must complete the work. Block 23

W elements HJTIi is designed for reset. laziness of cells of block 14 of control registers in case of termination of work by any executive body in case of correct functioning of the block

15 executive bodies. The element OR 24 is intended for zeroing the block 15 of the signal latching registers. The element OR 25 is designed to generate a signal informing

0 that any executive body of block 5 has finished its work. Element IPI-NOT 26 is designed to generate a signal informing that the block 5 executive bodies

5 completed the work. Elements 27 and 28 are intended for setting operation modes of the device without organizing control over the ending of work by the executive bodies of unit 5

30 and with the organization of such control, respectively.

Element And 29 is designed to generate a signal that informs about the premature termination of work by any executive body of the unit 5. Element And 30 is intended to generate a signal that informs about the false alarm of any sensor of the end of the operation of block 9.

40 Element And 31 is intended to form a signal informing that any executive unit of block 5 has not completed its work on time. Predelay delay element 32 is assigned to delay the signal input to the control input of the decoder 20.

The device operates as follows 0.

Before the start of operation, after power is turned on, all storage elements of the device are reset by applying a signal to the reset bus 55 (the reset circuits are not shown in the device diagram).

To start the device, to input 33, a single pulse signal is applied, which is fed to

513

the trigger input 21 (start) and the input of the first element 1-CHI 10. The trigger 21 switches to one state and starts the pulse generator 1. From the output of the element OR O, a single pulse arrives at the input 35 of the block 4 of the program set and the clock inputs of the master blocks 3 and 13 and the block 14 of the control registers. On the leading edge of the IT signal, a command code is issued to the groups of control outputs 36 of block 4 of the program set, which is fed to the group of inputs of block 5 of the executive bodies. On the falling edge of the same signal, the time codes are recorded during the specifying units 3 and 13 and the verification code in unit 14 of the control registers. Two modes of block 5 executive bodies are possible. In the first case, the order of completion of work by the executive bodies can be arbitrary, and then the code containing one unit and the rest of the cell are zero code are written into the cells of block 14 of control registers, the number of which corresponds to the number working according to a given program by the executive body of block 5.

In the case when the executive bodies of block 5 must complete work B of a certain sequence., The codes corresponding to the sequence of numbers of the executive bodies of block 5 are recorded in the cells of block 14 of the control registers in the sequence in which these executive bodies must finish work.

On the trailing edge of the signal received at the control input 35 of block 4 of the program set, information on output 37 (marks), a group of outputs 39 and 40 of the time code, change. At the same time, at output 37 (labels) of Zlok 4 of the set of programs, when monitoring the order of completion of work by the executive bodies of block 5, there is no signal. If the order of completion of work by the executive bodies of block 5 may be random, then the output 37 (marks) of block 4 of the program set contains a single signal.

The pulses from the generator output I pulses arrive at the second inputs of the elements And 27 and 28 vi through a divider

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2 frequencies on the counting inputs, time back, a-romiix of blocks 3 and 13, Since there are no third and fourth inputs of the elements And the 27 and 28 signals are missing, the latter are also absent at their outputs.

After time T ,,. Definition

During the start of the time interval during which the unit 5 of the executive bodies is supposed to finish work, at the output 38 of the time of the master unit 3, a single signal is generated which switches the RS flip-flop 22 (control) to one and closes the address-18 counter. A potential single signal arrives at the fourth inputs of the And 27 and 28 elements.

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Let it be necessary to control the sequence of the shutdown of the executive bodies of unit 5; working on a given program.

Then at the output 37 of block 4 of the program set, there is no signal. Therefore, the second element I 27 is locked and the third element 28 is open.

If any executive unit of block 5 finishes its work, a single signal is formed at the output of the sensor of the block 9, which terminates operations, which is fed to one of the information inputs of block 15 of the latch registers. The code from the block 15 of the signal fixation registers through the encoder 19 is fed to the first group of inputs of the block 6 of the comparison. The second group of inputs of the comparison unit 16 is supplied with a code that is read by the multiplexer block 17 from the first cell of the control register block 14. The cell address is set by the address chick 18 address. If the codes in the first and second groups of inputs of the comparison block 16 are equal, the next clock pulse received at the control input of the comparison block 16 through an AND 28 element, which is opened by a signal from the output of the third element OR 25, fed to its third input by the third OR 25 element, the output of the comparison unit 16 forms the normal signal, which is fed to the input of the delay element 32, the counting input of the address counter 18, and through the SHSh 24 element to the R and C inputs of the block 15 pe-. gistr fixing signal.ov. On the falling edge of this signal, the contents of address counter 18 are incremented by one, and zeroing the block of the signal latching registers closes the third element 28, as a result of which the pulses from the output of the generator 1 pulses do not arrive at the clock input of the comparison unit 16. delays, the norm signal is fed to the control input of the decoder 20. The information inputs of the decoder 20 is supplied with a code from the output of the counter 18. The signal from the output of the decoder 20 through the block 23 elements OR is fed to the input zero and (R) the first cell control registers block 14 and causes it to reset. Since the state of the counter 18 of the address has changed, the code of the next actuator, which is supposed to finish the work, will go to the second group of inputs of the comparison unit 16. When a new signal arrives in block 15 of the signal fixation registers, the described process is postponed, but only if the order of completion of work by the executive bodies is observed.

When is the last job done

the executive body and, if this AOR element input is And 27. At the same time, the time code did not complete the time interval from the output of block 15 of the latching registers, during which the unit 5 of the signals goes to the second group of bodies should be of the laws of the inputs of block 8 elements I. Signal, to work, then as a result, the output element of the AND

, from 27, when a clock pulse from the generator 1 output arrives at its corresponding input, it goes to the first group of inputs of the block 8 elements AND through the element OR 24

40

Sanny processes will occur a complete reset of the block 14 control registers. As a result, at the output of the element OR-NE 26, a unit signal is set which brings the control RS-flip-flop 22 to the zero state. Upon expiration of the operation time of the unit 5 of the executive bodies, the timing unit 3 generates a pulse signal arriving at the second input of the element 31 and the input of the first element 11 of the delay. Since the first inverse input element And 31 there is a signal unit, the pulse unit with the output of the first time at the R and G inputs of the block 15 registers latching signals, which causes it to be reset. By this time, at the output of the element And the block of 8 elements, at the inputs of which there are single signals, a signal will be generated which, through the block of 23 elements OR, will go to the null (R) input of that cell of the control register block 14, which corresponds to the executing unit 3 does not pass to the entrance of the 50th body that completed the work.

block 6 alarm.

After the time determined by the delay element 11.

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input element is And 12. Since the second (inverse) input of this element has a zero signal, the signal through the element OR 10 is fed to the control input 35 of block 4

a set of programs, the inputs 35 synchronization time master blocks. 3 and 3 and on the group of synchronization inputs of the block 41 of the control registers. As a result

this is the transition to the execution of the next program recorded in block 4 of the set of programs. After the last program is completed, the transition to the first one is made and the whole

the process is repeated. The described processes are depicted in the timing diagrams shown in Fig.6.

I

If the order of completion of work by the executive bodies of block 5 is arbitrary, a signal of unity is present at the output 37 (marks) of block 4 of the program set. This leads to the fact that the element And 27 is open, and the element

And 28 is locked. Then, when an information input (S) of the block 15 of the register of fixation of signals of the signal about the termination of work by an arbitrary executive body, is received

block 5, the output of block 15 of the latching registers will generate a code containing a single signal. This single signal through the element PLI 25 enters the third

40

on the R and G inputs of the block 15 registers latching signals, which causes it to be reset. By this time, at the output of the element And the block of 8 elements, at the inputs of which there are single signals, a signal will be generated, which through the block of 23 elements OR will go to the zeroing input (R) of that cell of the control register block 14, which corresponds to the rest of the the executive bodies of unit 5 are controlled in a similar way.

During the operation of the device 55 failures are possible.

In the case when there is no control over the order of completion of work by the executive bodies of unit 5, the following failures are possible: premature 913

to stop any executive body; the arrival of a false signal at the input of block I5 of the latching registers of signals after the end of work by the whole block 5 of the executive bodies and until the end of the time during which it must finish work; one or several executive bodies of block 5 did not finish the work on time.

When monitoring the shutdown sequence of the executive bodies of unit 5, in addition to the listed failures, failures are also possible in case of violation of the order of shutdown of the executive bodies of unit 5; stopping two or more executive bodies for one period of clock pulses produced by the pulse generator 1.

When any actuator of block 5 is prematurely stopped, elements AND 27 and 28 are locked because the RS control flip-flop 22 until the signal from the output arrives, the time of driver block 13 is in the zero state. The unit signal from the output of the block 15 of the signal latching registers through the element OR 25 enters on. the first inputs of the elements And 29 and 30.

Upon receipt of the signal T

min

on

the second input element And 29 at its output a failure signal is generated, which is registered by the signaling unit 6

If, after completion of work by all executive bodies of block 5, any information input (S) of block 15 of the fixing registers of the flash signals receives a false end-of-work signal, this signal will also go to the first inputs of elements I 29 and 30. At the second input of the element I 30, there is a single signal from the output of the element ШШ-НЕ 26, at its output a failure signal is generated, which is registered by the signaling unit 6.

If one or several executive bodies of block 5 have not completed work in time, then by the time the signal 31 of the output element 31 arrives at the output of the time of master unit 3, its first (inverse) input contains a signal zero from the output of the element OR-26X. the result at the output of the element And 3 form

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failure signal, which is fed to the input unit 6 alarm.

If, when controlling the shutdown sequence of the executive bodies of unit 5, this sequence is violated or during the period of the clock pulses from the output of the pulse generator 1, more than one executive unit of block 5 is working, then the codes on the first and second groups of inputs of the comparison block 16 do not match. As a consequence, when a signal arrives at the clock input of the comparator unit 16, a failure signal will be generated at the second output of the comparator unit 16, which will go to the input of the signaling unit 6 (see Fig. 6) 5 for any of the considered failures at the unit output 6 signaling (failures) a single signal will be formed, which will go to the second input of the first element 12 and close it, as well as through the zeroing unit 7 to the R input of the RS flip-flop 21 (start). The trigger 21 (start) switches to the zero state and the device stops operating. The stopping of the cyclic process control device is also possible by sending a signal from the outside to the input 34 of the device, I which, through the zeroing unit 7, zeroes the RS flip-flop 4 (start), which causes the generator 1 to stop.

I Time assignment. Block 3 (13) works as follows.

In the initial state on the group of information outputs 39 (40) the time of the master block 3 there is a code

0 time. At the output of counter 55, the zero code, the first element K 56 is locked, and the signals arriving at the counting input 44 of the time of the master unit 3 (3) do not pass to the counting input

5 counter 55. When the clock pulse arrives at the synchronous input 35, the time of the master unit 3, the time code that is present at the inputs of the D counter 55 is recorded in the counter 55. On the group

0 outputs of counter 55, a code other than zero appears. A single signal, formed at the output of element 1-ShI 58, opens the first element And 56, and on the counting input of the counter 55

5 begin to receive impulses. The time code arriving at the group of information inputs 39 (40) the time of the master block 3 (13) is chosen so that the time during which

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The counting of pulses received by the counting input 4– + the time of the master block 3 (13) before generating single signals on all the outputs of the counter 55, was the same for the first time of the master block 3 the maximum time T. tnizmov, and for the second time the master block 3 T .. ,,, - the minimum time n

nor the work of the executive bodies. . When single signals appear on all the outputs of the counter 55, a single signal is generated at the output of the element 57. The next pulse arriving at the counting input of the counter 55 resets it to zero, at the output of the element of RSHI 58 a zero signal appears that locks the first element And 56. At the same time at the output of the second element And 57 a single signal disappears. ,

Block 4 of the set of programs works as follows.

In the initial state at its input 35 and the group of control outputs 36 there are no signals. At the outputs of the counter 53 addresses - code zero. A check code is contained in the group of outputs 41 of the control unit 4 of the program set. In the first 39 and second 40 groups of outputs of the time code of block 4 of the program set, the first and second time codes are contained. On the first group of inputs of the block 54 elements And the command code is given. When a signal arrives at the input 35 of block 4 of the program set, the leading edge of this signal is opened by a group of 54 elements AND, and a command code is issued on the group of control outputs 36 of the block 4 of the program set. On the falling edge of the signal arriving at the counting input of the address counter 53, the contents of the counter increase by one, and information is read from the next cell of the storage device 52. At output 37 (marks) of the program set block 4, a single or zero signal appears depending on the operation mode of the cyclic process control device. When resetting the counter 53 of the address, a transition is made to reading the information on the first cell of the memory 52.

Block 6 alarm works as follows.

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In the initial state, the inputs 47-50 and the output 51 of the signaling unit 6 have no signals, the trigger 59 is in the zero state. d. A group of inputs 46 may contain any code. When a signal arrives at any of the inputs of the element OR 61. At its output, a signal is generated that switches the trigger 59 into a single state. A single signal from the output of the trigger 59 opens the elements And block 60 and is fed to the output 51 of the block 6 alarm. At the output of that element And block 60, at the inputs

5 of which there are single signal signals, a signal is generated that ensures the operation of the display element. When zeroing the trigger 59 on the group of outputs of the block 60 of the elements H and the output

0 of the signaling unit 6, zero signals are set.

Claims (1)

Invention Formula 5 A device for programmed control and monitoring of cyclic processes, comprising a block of a set of programs, a first time master block, a block of sensors for terminating an operation 0 zeroing unit, pulse, signaling unit, AND unit, first delay element, first element AND, first element 1SH, frequency divider, block of actuators connected by outputs to the inputs of the end-operation sensor unit, and inputs to the first inputs the block of the program set connected by the second outputs with the information inputs. Q is the first time of the driver, a block connected by a counting input to the output and a frequency generator connected to the output of the pulse generator; the first element AND is connected by the first input to  the output of the first delay element, the second input to the output of the signaling and recording unit fails, characterized in that, in order to gain control over the role and expand the field of application of the device, a multiplexer block, a control register block, an OR element block, a block are entered signal fixation registers, address counter, g comparison unit, second time master unit, encoder, decoder, two OR elements, second delay element, five AND elements, OR-NOT element, first RS flip-flop and second RS-trigger 35 1313 , a germ connected by a direct output to the input of the pulse generator, R-BXO-house to the OUTPUT of the zeroing unit connected by the first input to the second input of the first element AND, and the second input to the input Stop of the device whose Start input is connected to S-input of the second RS-flip-flop and the first input of the first element OR, connected with the second input with the output of the first element And, and the output with the control input of the dialing unit, programs and with the clock inputs of the first and second time of the master blocks and the control register block connected inputs will reset tim elements to respective outputs of the OR block and outputs. - to the corresponding information inputs of the multiplexer unit and to the inputs of the element OR NOT, and the information inputs to the third outputs of the program set block connected by the fourth outputs to the information inputs of the second time of the master block, and the fifth output to the first inputs of the second and third elements AND each of which is connected by the second input to the generator output, the third inputs to the output of the second element OR, and to the first inputs of the fourth and fifth elements AND, and the fourth input to the direct output of the first RS flip-flop, of the second input of the fifth element AND, with the first input of the sixth element AND with the output of the element OR NOT, and S-input with the output of the second time of the master unit, with the second input of the fourth element AND and with the input zero the address counter connected by bit outputs6 4 to the address inputs of the multiplexer unit and to the information inputs of the decoder associated with the control input with the output of the second delay element, and the outputs with the corresponding first inputs of the block of OR elements connected by the second ones. inputs to the corresponding outputs of the AND block, connected by the first inputs to the output of the second AND element and to the first input of the third OR element, and the second inputs to the encoder inputs, to the first inputs of the alarm unit, to the inputs of the second OR element, and to the outputs of the latch register connected by information inputs to the outputs of the sensor block of the end of the operation, and the synchronizing input and the zero reset input to the output of the third SHSh element connected by the second input with the counting input of the address counter, with the input torogo delay element and the first output of the comparison unit, connected to the clock input to the output of the third element And, the first and second information inputs respectively to the outputs of the encoder and to the outputs of the multiplexer unit, and the second output is to the second input of the alarm unit connected by the third and fourth inputs to the outputs of the fourth and fifth elements, respectively, and the fifth input to the output the sixth element And connected by the second input to the input of the first delay element and to the output of the first time of the master unit connected by the counting input with the counting input of the second time master unit. ih. five} . C -1-1  eM sa cy / ifu / i / J S / fOff 55 57 4-5 phage. b / 717 / f ci / e / cf f / 3aifL / u   S 49 50 61 & .  TO Sf 60  AND (pus.5