SU1238035A1 - Programmed control device - Google Patents

Description

actuator controls. In addition, from the memory block 8 from output 8.2, the unmodifiable part of the program's address code will be counted, the definition of the invention relates to automation and computing technology and can be used in positional systems for software control of machines.

The purpose of the invention is to expand the field of application by implementing an asynchronous control signal.

The drawing shows the functional diagram of the device for software control.

The device contains an IPI register 2 addresses with information inputs 2.1 and 2.2, an output register 3, a second delay element 4, a pulse shaper 5, a multiplexer 6, an address counter 7, a memory block 8 having the first 8.1, the second 8.2 and the third 8. information outputs, as well as control output 8.4 element OR 9, trigger 10, element 11 and 12, delay element 13, generator 14 clock pulses, element 15, counter 16, element RShI 17 element HE 18, input 19 logical conditions, the input 20 of the first program code, the input 21 controls the start of operation of the device and the control yuschy output. 22 devices.

Memory block 8 is designed to store the codes of the beginning and end of execution of control signals in the program, the code of the number of blocked clock pulses preventing the control signals at the output 22 of the device, and non-modifiable parts of the program address codes. The multiplexer 6 allows the transfer of the address to the counter 7 of the address from the register 2 of the address and either from the input 20 of the device in accordance with the control signals received at the inputs 6.2 and 6.4 of the multiplexer. The address slider 7 performs a sequential transition of the program depending on external conditions. - This information comes from information output 8.2 of memory block 8 to input 2.1 of address 2 register 2. 1 il.

telno sampling of information from memory block 8 in the mode of natural addressing. The counter 16 is designed to store a code for the number of pulses that are blocked by such 5 to 5 pulses. A .14 clock pulse generator generates pulses that synchronize the operation of the device. The address register 2 serves to store the address when moving to another branch of the program depending on the external (logical) condition being checked and makes a modification of the (change) address when: force; addressing. Trigger 10,

5, the elements 11 and 12 and the delay element 13 control the process of retrieving information from the memory block 8 and generating the address in the ad-meter 7. . ,, .: :

0 The device works as follows;

In the initial state, the memory elements of the device are in the zero state.

5 from the input 20 of the device to the information input 6.3 of the multiplexer 6 receives the first program code. At the same time from the input 21 to the equalizing input 6.4 multiplexer 6

0 a signal is received. Starting operation, the program code is transmitted through multiplexer 6 to the counter, the address 7 signal and in parallel to the input of the element OR 9. At the output of the element OR 9

5, a high potential is formed, KOt.oi sets the trigger 10 to a single state. After the trigger 10 is set to one, the Start Work signal is removed.

0 The signal 1 from the output of the trigger 10 is applied to elements I. 11 and 12 and enables the passage of clock pulses from the output of the generator 14 through the element 12 and further through the line 13 for the holder and the element 11 (counter 16 to

is in the zero state and at the output of the element HE 18 there is a signal 1 allowing the passage of clock pulses through the element 12). The first clock pulse from the output of the generator 14 through the element And 12 enters the synchronization input of the memory block 8 and samples information at the address recorded in the counter 7 of the address. The code of the control signals from the output 8.1 of the memory block 8 enters the output register 3 at the counting inputs of the flip-flops, setting the corresponding of them into one state. Transition to a single state of certain triggers of the output register 3 means the beginning of the corresponding set of control signals to the output. 22 devices for controlling actuators. The end of each control signal, carried out by bringing the trigger to the zero state, can be specified in any of the subsequent program control words stored in memory block 8. In addition, from block 8 of memory from output 8.2, the unmodifiable part of the program's address code is read, determining the possible transition of the program depending on any external conditions. This information is fed to the input 2.1 register 2 addresses.

The delay time of element 13 is equal to the duration of the clock pulse. Therefore, at the moment of termination of the clock pulse, the synchronizing input of the memory block 8 from the output of the delay element 13 through the element 11 to the summing input of the counter 7 of the address receives a signal, increasing its content by one. After that, the second clock pulse allows sampling from the memory block 8 of information containing only the code of control signals. This control word can simultaneously terminate part of the control signals, leaving the other part of the output signals unchanged, and by acting on the counting inputs of the triggers of the high-speed register 3, start issuing new control signals.

The simultaneous termination of some and the beginning of another control signal helps to eliminate the overhead of

0

five

0

five

0

five

0

five

0

five

retrieving information from the memory block, and the ability to not interrupt the control signal when changing control words (retrieved information from the memory block) provides an arbitrary duration of this signal within the control program.

Such an organization of the device operation involves the selection of information from memory block 8 only at the required time points when a change in output signals is required. If within a few clock cycles of the generator 14, for example, starting with (h + 1) -ro clock, no change is required in the output control signals, then in the control word read in the h-th cycle, the code of the number of blocked clock pulses is specified. This code From output 8.3 of memory block 8 is fed to the information input of counter 16 and through the element OR 17 and the element NOT 18 prohibits the passage of clock pulses through element 12. At the same time, the signal from the output of element OR 17 goes to the input of element 15, allowing passage through clock pulses from the generator 14 to the subtracting input of the counter 16. In the (H +1) th operation cycle of the device retrieving information from the memory block 8 does not occur, and the clock pulse from the generator 14 enters through the element 15 to the subtracting input of the counter 16 and reduces its soda per unit. After zeroing the counter 16 at the output of the element OR 17, the signal O is set, which through the element NOT 18 allows the production of the next clock pulse through the element 12 to be transmitted. the input of the counter 16 through the element is And 15. The blocking scheme thereby avoids the storage of empty information in the block 8 of the memory.

A linear sequence of program control commands is executed by the device in the natural addressing mode, i.e. Each subsequent selection of information from memory block 8 is preceded by an increase in the content of counter 7 of the address by one. This allows not to store in the memory block 8 the address parts of all control words (control commands) and.

therefore, reduce its scope and facilitate its programming.

The device can switch to one of two possible branches of the program depending on the validated external (logical) conditions, for example, in case of failures of one or another type of equipment.

In this case, from the output register 3, the device polling information is set, the state of which depends on the branch in the psamme. The signal from the polled device enters input 19 of the device and through the OR element 1 sets the trigger register 2 addresses to input 2.2 in the unit condition. If no signal has been received from the device being polled, the state of the bit-altering register .2 of the address remains Zero and thus the second possible transition address is generated. In the last control word of the linear sequence of program control commands, the end of the device polling operation (not shown in the drawing) and the rewriting control signal of the generated address from the address register 2 via the multiplexer 6 to the address counter 7 are set. After sampling information from memory block 8, the control signal from output 8.4 is fed to the input of the zero setting of trigger 10 and to the input of the pulse former 5. The signal O from the single output of trigger 10 prohibits the passage of clock pulses from the output of generator 14 through elements 11 and 12 As a result, the increase in the content of the counter 7 address is blocked. The pulse shaper 5, under the influence of a control signal at its input, generates a pulse whose duration is equal to the time of rewriting information from the register 2 of the address into the counter 7 of the address. This pulse from the output of the imaging unit 5 is fed to the control input 6.2 of the multiplexer 6, thereby permitting the rewriting of the address of the next linear sequence of commands in the counter 7 of the address. Through the delay element 4, the pulse arrives at the input of setting the address register 2 to zero, dropping its contents after rewriting the information. In parallel with the rewriting of the address, the address code from register 2 is through multiplexer 6 and the OR 9 element sets the trigger 10 to one state. ; The signal 1 from the output of the trigger 10 is fed to the elements 11 11 and 12 and again allows sequential sampling of information from the memory block 8. The branch in the program is caused not by the entire set of devices of the controlled object, but by its individual devices (actuating elements). For this reason, there is no need to stop sending control signals to the rest of the object.

The end of the operation of the device after execution of the program is set programmatically by moving to a command with a zero address part and the only control sign in the operating part. After sampling from the memory, the control signal from the output 8.4 of the memory block 8 sets the trigger 10 to the zero state, which blocks the subsequent signals to access the memory block and starts the pulse shaper 5. The pulse shaper 5 allows address rewriting through multiplexer 6 from register 2 to counter 7. But since the address code is zero, it passed the OR 9 element and cannot set trigger 10 to one, which keeps the clock lock pulses. The software control unit is ready to receive a code for executing the next program or repeating the previous one and the Start operation signal. Further, the device operates as described.

Thus, the asynchronous injection of control signals allows to improve the characteristics of the device and, therefore, expands its area of application.

50

Claims (1)

Invention Formula A software control device comprising a clock pulse generator, a memory block, an output register, an address register, a counter, a trigger, the first and second OR elements, an AND element, a delay element, a pulse shaper, an address counter whose output is connected to the information input of the memory unit, the first information output of which is connected through the output register to the control output, device, the output of the clock pulse generator is connected to the first input of the first element AND whose output is connected to the subtracting input of the counter, the output of the first element OR is connected to the input installation in 1 flip-flop, that is, in order to expand the scope of application by implementing an asynchronous control signal, it additionally contains a multiplexer, a second delay element, the second and third elements are AND, the third element is OR, the element is NOT, and the group of inputs of the second element OR is the group of inputs of the logical conditions of the device, the output of the second element OR is connected to the first input of the group of information inputs of the address registers, the remaining inputs of the group, information inputs which is connected to the second output of the memory unit, the third output of which is connected to the information input of the counter, the output of which is connected to the input of the third element OR The output of which is connected to the second input of the first element And-and Odom eleRedaktor AM / shda Order 31g89M7 Compiled by A. Isvravkoja Tehred O. Gortvay Proofreader L. Patay Circulation 836 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 : NOT which the output is connected to the first input of the second element I, the output of which is connected to the synchronizing input of the memory unit and the input of the first delay element whose output is connected to the first input of the third element AND whose output is connected to the summing input of the address counter, and the unit one the trigger output is connected to the second input of the second element I and the second input of the third element I, while the output of the clock generator is connected to the third input of the second element I, the control output of the memory unit is connected to the trigger input and the pulse driver input whose output is connected to the first control input of the multiplexer and through the second delay element to the installation input in the address register O, whose output is connected to the first information input of the multiplexer, the second control input of which is the control input of the start device, the second information input of the multiplexer is the input of the first program code, and the output of the multiplexer is connected to the information input of the address counter and the input of the first element OR.