SU1406595A1 - Programmed controller processor - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in control devices for technological equipment. The purpose of the invention is to increase the speed of the programmable controller processor. The processor of the programmable controller contains the synchronization chip 1, the control block 2, the microinstructor memory block 3, the microinstructions register 4, the I / O control register 5, the flag storage block 6, the processing bit bits and conditions block 7, the modifier 8, the first block 9 keys with three-stable output, register 10 of the processed bit code, second block 1 of keys with three-stable output, decoder 12 of the mask of the processed bit, arithmetic logic unit 13, input-output block 14, internal bus 15 micro-instructions, internal data J6, channel 17 data, the first element OR 18,, the second element OR 18. 15 Il. (L

Description

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The invention relates to automation and computer technology and can be used in process equipment control devices.

The purpose of the invention is to increase the speed of the processor.

Figure 1 shows the structural diagram of the proposed processor programmable controller; figure 2 - the system of microcommand processor; fig.Z - functional diagram of the synchronizer; 4 is a functional block diagram of the control unit; figure 5 is a functional block diagram of the analysis of the processed bits and conditions; Fig. 6 is a functional diagram of a flag storage unit; in Fig. 7, a table of the distribution of functions of the general purpose registers (RON) of an arithmetic logic unit; Fig. 8 is a table of the distribution of functions in the mode register; . on figure 9 - the overall algorithm of the processor of the programmable controller; in FIG. O, the algorithm for processing the command of a normally open contact; in FIG. JJ, the algorithm for executing the command Start of a parallel branch; Fig. 12 shows the algorithm for executing the command End of a Parallel Branch; Figure 13 shows the composition and size of tires connecting blocks 8-12; on Fig presents a timing diagram of the processor; 15 shows the structure of an I / O unit.

The processor of the programmable controller (Fig. 1) comprises a synchronizer control unit 2, a microprogram memory unit 3 (BPM), micro-command register 4, an input-output control register 5; a flag storage unit 6; block 7 analysis of the processed bits and conditions; firmware modifier 8, the first block of 9 keys with a three-stable output; register .10 code of the processed bit, the second block of keys with a three-stable output, the decoder 12 of the mask of the processed bit, the arithmetic logic unit (ALB) 13, the input-output unit 14, the internal bus 15 microinstructions, the internal data bus 16, the data channel 17, the first second 182 elements OR.

The synchronizer (FIG. 3) contains a generator 19, a counter of 20 cycles, a de- encoder 21 cycles, a second element OR 22, a trigger 23, the first element NOT 24, and the first element AND 25.

The control unit of the processor and the address of the microinstructions (figure 4) contains the decoder 26 of the microinstructions format, elements OR 27, 28, return register 29, the second element NOT 30, elements 2И-ШШ 31 and ЗИ-OR 32, counter 33 of the address micron.

The block of analysis of the processed bit and conditions (FIG. 5) contains a multiplexer 34, the element EXCLUSIVE OR 35 trigger 36.

The flag storage unit (FIG. 6) contains AND 37-42 elements and triggers 43-48.

The processor works as follows.

The synchronizer generator 19 1 (FIG. 3) generates a sequence of pulses, which is converted by a counter of 20 clock cycles and a decoder of 2J clock cycles into a system of clock pulses that synchronize the operation of the processor. The clock pulses arrive at the inputs of the AND-OR elements 31, 32 (Fig. 4) of the control unit 2.

From the outputs of the counter 33 of the address MK, the signals arrive at the address inputs of the BPM 3 and determine the address of the readable microcommand. From the outputs of the BPM 3 information is fed to the inputs of the register 4 micro-instructions, and from its outputs - to the internal bus 15 micro-instructions.

Older bits (MMK12-MMK15) of trunk 15 determine the format of the microcommand (Fig. 2) and arrive at the decoder 26 of the microcommand format (Fig. 4).

From the outputs of the decoder 26 of the micro-command format, the control signals (Fi) are fed to the inputs of various processor units, and the execution of the micro-commands of this format is determined.

In format 01, ALB 13 commands are executed. The executable microcommand code determines the lower bits of the 15 microinstruction trunk (MMKOO-MMK 1), ALB13, signaling its readiness to receive microcommands, exposes a high level of the F1 signal at the output of the microinstruction, which arrives at the inverse input element 22 (Fig.Z). At the same time, the input element And 25 receives a signal F 01 s. Descriptor, torus 26 format, the second input element And 25 receives a signal from the inverse output of the D-flip-flop 23, which at the initial moment is set to zero-state with a reset signal (not shown). From the output of the AND 25 element, the media signal (ALB clock) is sent to the clock input of AL) 13, allowing execution of a microcommand, and to the second input of the OR element 22, from the output of which a signal is received Brake, blocking the counter operation of 20 clock cycles for the reception time and the execution of the microcommand ALB 13, which sets the low level of the signal F1, With the appearance of the signal The brake, the decoder of 21 strokes generates a signal that blocks the decoder of the format 26, which removes the signal of the format F 01 and, accordingly, CMII. At the end of the execution of the microclock ALB 13 sets the high level of the F1 signal and the clock counter 20 is unlocked. The execution of ALB 13 microinstructions with the exchange-reception of information from the channel and the issuance of information to the data channel 17 should be preceded by a microcommand that sets the corresponding signals in the I / O control register 5 (F 13 format). The I / O control register 5 is made on a K589IR12 chip.

The installation inputs of the I / O control register 5 are supplied to the lower bits of the 15 micro-instruction trunk. (ММКОО-ММК07).

To the clock input of the register 5, the control of the INPUT 7 OUTPUT comes from the decoder 26 format signal of the corresponding format (F J3). Signals corresponding to the addressable peripheral device are removed from the outputs of the I / O control register 5 (random access memory, I / O blocks, diagnostics panel and others are not shown in the drawing), and control signals issued or received: , THU (reading), VA (issuing addresses). The I / O control register 5 is reset by an F 13 micro-command with all zeros in the lower-order micro-instruction. Signals BA, ZP, THU through the element OR 18 are fed to the input of D-trigger 23, Information about the execution of a microcommand with exchange (the presence of one of the signals BA, KP, THU) is entered into the D-trigger 23 by the signal drop F1 from J to O D-flip-flop 23 through the element OR 22 starts braking the counter of 20 cycles. Braking is removed when the SP signal appears (reception synchronization). The AS signal is generated by the information receiver after the information has been received. Thus, an asynchronous exchange between ALB J3 and peripheral devices is performed. After the deceleration is removed, the synchronizer 1 generates a clock pulse, which is fed to the inputs of elements 2И-ШШ 31 and ЗИ -ЛИ 32 and increases the value of the counter 33 of the MK address by one if the microcommand of all formats was executed, except F 02, F 03, F 04 , F 07.

Using the F 02 format, a command is received from a user work program (DF) written to RAM (not shown). The operation code of the RPT command from channel 17 through the block 14 of bus drivers is fed to the data bus 16 and to the inputs of the key block 9. The F 02 format switches the block of 9 keys in such a way that the operation code of the RPT command enters the lower bits of the J5 microinstruction trunk (MMKOO-MMK05) and the installation inputs of the counter 33 of the MC address. When receiving a command, two bits of the 15 micro-command trunk (MMK06, MMK07) depend on the state of the 8 microprogram modifier, which consists of two triggers set by the preliminary micro-command of the F 05 format. Thus, in the counter 33, the MC address is set by the micro-command of the F 02 format the directory address (the RAM area), which is determined by the operation code of the RPT command and the status of the modifier 8 firmware. By switching the modifier 8 firmware, you can receive the same RPT command in four modes (modifications).

The microcommand of the F 03 format unconditionally jumps to the address specified in the lower order of the microcommand (MM-CCM-11). The microcommand of the F 04 format, depending on the condition of the trigger 36 condition (FIG. 5), or conditionally jumps to the address specified in the lower order microcommand (MMKOO-MMK1I) (if the condition is met), or increases the contents of the counter 33 of the MC address by +1 (if the condition is not met).

The microcommands of the F 06, F 07 formats switch to the nested subprogram and exit from it. According to the F 06 micro-command, return register 29 (FIG. 4) records the return address from the subroutine contained in the MCS-11 lower order micro-instruction. The transition to the nested sub-program is done using the F 03 micro-command (unconditional). At the end of the nested subprogram, the F 07 format microinstruction is set, which performs the installation of the counter 33 of the MK address to the value written in the return register 29

The main function of the processor of the programmable controller is the quick analysis of the processed bit (the state of the input or output being analyzed). G1p receiving the RSh1 command (F 02 format) into the register 10 of the code of the processed bit is entered from the address part of the command through the I / O block 14 and the key block 9 the address code of the processed

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data (addresses) in the RHON ALB 13, where the control action on the output is formed.

According to the F 1 microcommand, flags are set in the block. 6 flags storage, which consists of a group of D-flip-flops 43-48 (FIG. 6) and input logic on AND 37-42 elements.

Depending on the value of the bits of the J5 micro-instruction trunk (MMKOO-MMK11), one flag or another is set or cleared. The state of the 15 flags is analyzed by the analysis and processing block 7 of the bits and conditions. The microcommands of the F J5 and F 17 formats are redundant.

Two clocks are used for clocking.

batted bat. When a sequence of clock pulses of analysis of the processed bit (format F 14) arrives, the code of the processed bit from register 10 of the code of the processed bit via the key block 11 is fed through the internal micro-commands (MMK02-MMK06) to the address inputs of the multiplexer 34 (FIG. 5). The information inputs of multiplexer 34 receive the status of all inputs (outputs) recorded in the word at the address specified by the RPT command. The signal from the output of multiplexer 34 is fed to the input of element 35 EXCLUSIVE OR, to another input of which receives the discharge of the MMKOO micro-commands main line, which goes to the execution of the next microtor and indicates what is being analyzed-1 or O,

Depending on the analysis of the processed bit, a trigger 36 is set, the clock input of which receives signals of the formats F 14 or F 16. Similarly to the analysis of the processed bit, analyzes of the state of the flag storage unit are performed.

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Consider data records-. On the first microcommand, the control signal VA is set to the data channel.

40

(address), and the following microcommand sends an order to the ALB to output the contents of the address register to the channel. The ALB uses the principle of information acknowledgment, i.e., the status alarms of the ALB 13, the modified information given is accompanied by microprogram 8. All of these are analogous to the CB signal (delivery tracking),

LIZAS are performed using an F 16 micro-command,

The generation of a control action and its issuance according to a certain output from the group of outputs recorded at a specific address of the state table is performed using an F 10 microcommand (mask reading). According to this microcommand, the address code of the processed bit, coming from register 10 of the code of the bit being processed, and the decrypted mask of the processed one: the bits are read from the main 16

Sov C1 and C2: CJ is used to change the microcommand -address, and C2 - to write the micro-command code in the micro-instruction register, after which its execution begins. If the microinstruction is an ALB microinstruction, then an ALB synchronization signal C is generated. The active level of the signal C is O,

Signal C will be in the active state until the signal about the end of execution of the microcommand I is received from the ALB. Signal And removes signal C and

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Consider data records-. On the first microcommand, the control signal VA is set to the data channel.

(address), and according to the following microcommand, the ALB is instructed to issue the contents of the address register to the channel. The ALB uses the principle of information acknowledgment, i.e., the output information is accompanied by a CB signal.

The direction of the CB signal depends on the direction of the information.

The information receiving device issues a SP signal (reception synchronization), the SP signal is always issued as a response that the information has been received by the receiver. Such a principle makes it possible to exchange at the maximum possible speed with high credibility.

To complete the write cycle, the processor B1p1 introduces into the channel the control signal OT (write), Next in

The data from the ALB data register is set up, which is also accompanied by the CB signal and is in the channel until the SI signal is received,

 The reading cycle in the address part is performed in a similar way, and in the reading part, according to a CB signal received from the source of readable information. The data is recorded in the battery register, which assigns the SP signal to the source address.

The processor of the programmable controller operates according to the algorithm shown in FIG. 9. After pressing the Start button, an initial setup program follows, in which general constants are written to the ALB 13 general registers, microprogram modifier 8 is set to Initial Setup mode, the I / O control register 5 is reset, and flags are set. The address counter RS1 (user work program) is set to the number of the first RPT command. The RON J5 ALB 13 is assigned to the RPP address counter. The distribution of functions of the general purpose registers (Fig. 7) allows minimizing the number of exchanges between the processor and peripheral devices. In addition to the four modes of operation of the processor, set by the modifier. 8 microprograms (initial setting, programming, processing, indication), which define the address in the directory where the processor goes to receive the command, it is possible to perform several additional functions; searching for the desired element and highlighting the desired circuit on the screen, forcibly closing and opening the contacts of the external circuit (impact), the program editing functions (recording, inserting, deleting), etc.

Signs of performance of these functions are recorded in the RHONE 14 (Fig. 8 shows the table of the distributions of the functions of the RHONE 14 - the mode register).

After the RPF address counter is set to the first RPF word, the mode / work / programming switch is analyzed. In the Programming mode, the RAM (not shown) enters the P1SH and the RSHG editing functions are performed. The firmware modifier is set to Programming mode (not shown).

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Since the firmware fixer 8 is set to the Start position (the first scan cycle has been scanned), the mode register is cleared, and the J flag is set to, the program proceeds to receive the first command in the initial setup mode. The address of the directory to which the program for receiving a command goes is the beginning of the corresponding subroutine, after which the unit is added to the DSP address counter and the transition to the next DFS command.

By the initial setup program, the processing flag is entered into the I / O state table — the RAM area in which the state of the input sensors of the actuators are stored. The final RPT command is the End Program command. This command scans the input sensors and records their values in the state table of the inputs,

after which the firmware modifier. | Switches to the Processing mode, the counter of the DFR address is again set to the address of the first DFR command.

In the Processing mode, the feature Search in the mode register is analyzed and, if available, the current word PSS is compared with the search word, and then. flag J is analyzed. In flag 1

.jg remembers the value of the function of solving the zero equation of the current circuit. If the circuit is closed, flag J is 1, if the circuit is open, then flag 1 is set to O.

40 Once the sequential chain is opened, further processing of its contacts is meaningless and if the current command is not the beginning or the end of the parallel branch (t., J)

45 HJfii output (- C), then. The program goes to the processing of the next command (+ in the address counter RPT). If the flag is 1, the command is received in Processing mode,

50 Receive commands Start parallel

branches (T), The end of the parallel branch (J), Conclusion (- С J) osushcheg-. This is independent of the state of the J flag. All subprograms in mode 55 Processing go to the analysis of the display. This analysis is carried out by comparing the addresses of the beginning of the current circuit and the address of the beginning of the displayed circuit contained in the ROH. If no indication.

then a transition is made to + J in the DFR address counter. If the current price is displayed, the feature Listing in the mode register is analyzed. In the presence of this feature, the subroutine Listing displays the command number and its contents in the digital serial, then goes to the + J e DIP address counter. If there is no feature Listing, the program receives the command in Indication mode, Before receiving the command modifier The firmware is set to display mode. After testing the corresponding subprogram, the firmware modifier is again switched to the Processing mode,

In the Display mode, the corresponding subroutines display the circuit on the screen in the form of a relay-contact circuit (examples of subroutines in the Processing mode are shown in Figs 10-12).

After receiving the command-II- (FIG. 10), the address of the state table is formed from the address part of the command and the contents of the state table are read into the RHONE 11 ALB 13, after which the bit is analyzed (by one F 14 format micro command)

If the bit is O, then O is set to flag 1, if the bit is 1, the state of the flag remains one.

Upon receipt, the command C (the beginning, the parallel branch) analyzes the position of the flag 4 (in the flag 4, the value of the flag 1 is remembered by the command of the beginning of the chain),.

If before the start of a parallel branch the circuit is not open (flag 4 is 1), then flag 2 remembers the value of flag 1, i.e. the result of solving the previous parallel branch.

If flag 1 is 1, then this unit is remembered in flag

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The 45th bit, the analysis block of the processed bit and conditions, the first and second outputs of the synchronizer are connected respectively to the synchronization inputs of the control unit and the arithmetic flag 1 is set to O,

This allows you to exclude processing of a sequential block, the first output of the next parallel branch, if the control is connected to the address terminal, is closed, the home of the microprogram memory unit, the output

. Which is connected to the informational input of the command -G (the end of the parallel-register of the microinstructions, first to

branch), the 55th seventh outlets of the first group of outlets

OR between flags 1

2, the result is written to the flag J (FIG. 12). Similarly, the processing of other RPT commands is performed,

the control unit is connected to the first input of the synchronizer lock, rc, the first and the second inputs, respectively.

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The command Output (- C J) outputs the result (flag 1) to the corresponding actuator, changes the starting address of the current circuit (goes to the processing of the next circuit), and processes the timers. When the Timer condition is met, one is added to the current values of the timers, which are currently raised, are added.

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Condition The timer arrives from a trigger (not shown) on the multiplexer 34 conditions. The trigger is set by the network frequency (0, J s) and is reset by the F 12 program microcommand after the value of the excited timers is increased by one

25

thirty

The algorithm for executing the command. Output to the Quarter is not shown.

After the end of the PDP processing cycle, the End of Program program scans the inputs and writes them, new values in the TS (state table), reads the keyboard of the diagnostics and programming console (not shown), and writes the corresponding signs to the mode register. Then the first word number of the DFS is set in the DFR address counter, and the DLP processing cycle begins again.

Claims (1)

Invention Formula A programmable controller processor containing a synchronizer, 40 control unit, microprogram memory unit, microinstructions register, arithmetic logic unit, processed bit code register, input / output unit, processed bit mask decoder, processed bit and conditions analysis unit, the first and second outputs of the synchronizer are connected respectively to the inputs synchronization of the control unit and the arithmetic unit, the first output of the control unit is connected to the first input of the synchronization lock, respectively, with the first and second inputs of the starting analysis block abatable bits and conditions, with a micro-command register synchronization input, with a bdt code register register synchronization input, with a mask bit decoder's gate input, with an arithmetic logic unit operation control record input, output attribute of the result of the arithmetic logic unit operation with the first information input of the block analysis of the bit being processed and the VIIU bit, the output of the analyzed bit of which is connected to the input of the condition of the control unit, the output of the register of the bit being processed is connected to inf The mask input of the mask decoder is processed with a bit, the input / output control of receiving information from the arithmetic logic unit is connected to the first input output of the data transfer attribute of the I / O unit and the second input of the synchronizer lock, input output of the output information indication of the arithmetic logic unit is connected to the second input-output of the data transfer attribute of the I / O unit, the output of the indication of the end of the operation of the arithmetic logic unit ka is connected to the third input of blocking-30 synchronization of the synchronization control register of the synchronizer, characterized in that, in order to increase speed, a flag storage unit, a modifier of micdome output, whose outputs are connected to the outputs of the input and output of the processor, are entered into it , the information input / output of the processor is connected to the second roprogram containing the first and second 35 information input-output unit swarm triggers, first and second key blocks with three-stable output, I / O control register, first and second OR elements, and the outputs of the micro-command register are connected via bi-directional micro-command bus to the control-module micro-command inputs and outputs, and the arithmetic logic-logic operation block, with the information input of the flag storage unit, with the input of the choice of the logical condition of the block of analysis of the processed bit and conditions, with the information inputs of the first and second trigger-. The first output of the first and second key blocks with a three-stable output, with the information input of the I / O control register, the output of the first OR element is connected to the input of the synchronizer mode and the input to the third state of the I / O unit, the first information input the output of which is via the internal data bus of the processor with the first information input of the first key block with a three-stable output, the second output of which is connected to the information input of the register of the code of the processed bit, the outputs of the first and second triggers are connected, respectively, to the informational, input-output of the arithmetic logic unit. the second and third information inputs of the first key block with a three-stable output; in addition, the outputs of the first and second triggers are combined and connected to the second information key. At the input of the processed bit and condition block, the output of the processed bit code register is connected to the information input of the second key block with a three-stable output, the output of the flag storage block is connected to the third information input of the processed bit and condition block, the first to the third outputs of the second group of block outputs controls are connected respectively to the control inputs of the third state of the first and second key blocks with a three-stable output and to the input of syn0 five control register register home-output, the outputs of which are connected to the output I / O control outputs of the processor, information input-output of the processor is connected to the second input and output, with the fourth information input of the processing bit and condition block, the third and fourth input-output of the data transfer feature of the input-output unit are connected respectively to the first and second input-outputs of the information transfer characteristics of the processor, the first and second outputs of the input control register - you are connected to the first and second inputs of the first and second OR elements respectively, the output of the second OR element is connected to the first control input of the transmission direction of the I / O unit, the second input at the direction of transmission of which is connected to the third output of the I / O control register and the third input of the first OR element, and the control unit contains the return register, the microcommand address counter, the microcommand format decoder, the first and second OR elements, the first NOT element, 2I-1WI element and element The synchronization input of the control unit is connected to the gate input of the micro-command format decoder, with the first and second inputs of the element 2И-OR and from the first to the third, the inputs of the element ZI-OR, from the first to the fifth outputs of the first decoder group of the format of micro-commands are connected respectively with the synchronization input and with the control input of the third state of the return register, with the first and second inputs of the first OR element, and the fourth input of the ZI-OR element, the fifth input of which is connected to the third: the input of the 2I-OR element and the sixth you - I with the course of the first group of the decoder of the for-: mat of microinstructions, the outputs of the second group: which are connected to the corresponding inputs of the second OR element and to the outputs of the second group of the control unit, the input of which is connected to the sixth input of the ZI element -INI. and through the first element NOT to the third input of element 2И-OR, the outputs of the first and second elements ШШ are connected respectively to the fifth, the input of element 2И-OR and the seventh i input of the element ZI-OR, the outputs of which are connected respectively to the sum A control input and a microcommand address record control input, the outputs of which are connected to the outputs of the first group of the control unit I, the inputs and outputs of the microcommand of the first group which are connected to the informational inputs of the register of the gate and the address address of the microcommand I and from the exit and return register that enter-exit rows grup- nN second microinstruction control unit connected to the data inputs of the decoder microinstructions format, the analysis block of the processed bit and the conditions contains a multiplexer, an EXCLUSIVE OR element and a trigger, the output of which is connected to the output of the logic condition of the processing bit and conditions analysis block, the first to the fourth information inputs of which are connected respectively from the first to the fourth information inputs of the multiplexer, the output of which is connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the information input of the fourth trigger, whose synchronous input is Inen with the synchronization input of the processed bit analysis block and conditions, the logical condition selection input of which is connected to the multiplexer control input, and the lower bit of the logical condition selection input of the processed bit analysis block of the condition and bit is connected to the second input of the EXCLUSIVE OR element, and the flag storage block contains the first to the sixth triggers and the first to the sixth elements And, the outputs of which are connected to the synchronous inputs from the first to the sixth trigger, the outputs of which are connected to the outputs of the storage unit f lags, information inputs from the first to the sixth flip-flops are connected respectively from zero to five bits of the information input of the flag storage unit, from sixth to eleventh bits of the information input of which are connected respectively to the first inputs of the first to sixth elements And, the second inputs of which are connected with the synchronization input of the flag storage unit. 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