SU670935A1 - Processor - Google Patents

Description

with the third input of the addressing unit. The first memory output is connected to the third input of the data transfer unit.

The disadvantage of this processor is relatively low speed.

The purpose of the invention is to increase the speed of the processor.

The goal is achieved by the addition of an electoral logic analysis block, a command information processing block, a temporary memory interface block, and a hardware simulation block. The first inputs of the hardware simulation unit and the command information processing unit are connected to the output of the data transmission unit, the first, second, third and fourth outputs of the hardware simulation unit are connected respectively to the fourth and fifth local memory inputs, to the fourth input of the virtual address conversion unit and with the second input of the processing unit of command information, from the first to the seventh outputs of which are connected respectively with the second, third and fourth inputs of the hardware simulation block, with the fourth input of the addr block , with the second and third inputs of the buffer command block, with the fourth input of the buffer command block and the first input of the analysis and selective logic block, the first and second outputs of which are connected to the third and fourth inputs of the arithmetic logic unit, the second output of which is connected to the second input of the block analysis and selective logic, the third and fourth inputs of which are connected respectively to the second output of the second switch and to the fifth output of the microprogram control unit, the sixth, seventh and eighth outputs of which are connected respectively, the first and second inputs of the temporary memory interface and the fifth input of the hardware simulation unit; the sixth, seventh, eighth and ninth inputs of which are connected respectively to the second outputs of the buffer command block, basic addressing block, virtual address conversion block and the output control, her memory. The third and fourth inputs of the command information processing block are connected respectively to the third output of the buffer command block and the output of the addressing block, the third input, the first and second outputs of the temporary memory interface block are connected respectively to the second output and the third operational memory input and about the second input microprocessor control unit.

The command information processing block contains a node of address registers, a command control selection register, an unconditional jump matrix, a command control decoder, a conditional jump decoder, a buffer synchronization node

Commands, Microcommand Address Switch. The first input of the address register node is connected to the first input of the block, the second input of which is connected to the first input of the conditional transition decoder, the second input of which is connected to the third input of the block, to the second input of the address register node and the first output of the command buffer synchronization node the third input of the conditional jumper, the fourth input of which is connected to the first output of the instruction control decoder, the second output of which is connected to the first input

the switch address microcommand, the second and third inputs of which are connected to the outputs of the conditional transition decoder, respectively, and the matrix without conditional transitions. The fourth block input is connected to the unconditional transition matrix and the sampling control decoder through the sample control register, the third and fourth outputs of which are connected respectively to the first and second outputs of the block, the third and fourth outputs of which are connected to the address switch output microinstructions The fifth output of the command control decoder is connected to the second input of the command buffer synchronization node, the seventh block output and the third input of the address register node, the second output of which is connected to the fifth output of the command buffer buffer, the second output of which is connected to the sixth block output. The hardware simulation block contains an address transfer switch, a decoder

register registers, output switch, switch-on indication node, element I. The switch-on indication switch inputs are connected to the first and fifth inputs of the unit, the third and fourth inputs of which are connected to the first and second inputs of the transfer switch of the address. the output of which is connected to the third output of the unit and ne, the first input of the output switch, the output of which is connected to the second output of the unit,

the seventh and ninth inputs of which are connected to the inputs of the decoder of the decoder to the registers, the outputs of which are connected respectively to the input of the element AND, the third input of the address transfer switch, and

the second input of the output switch, the third, fourth and fifth inputs of which are connected respectively to the sixth, second and eighth inputs of the unit. The output of the switch-on indication unit is connected to the fourth output of the block and through element I to the first output of the block.

The unit of analysis and selective logic contains a node for forming a constant switch shift, a decoder and a register

states The first inputs of the decoder,

The shift switch state register n is connected respectively to the first, second and third inputs of the block, the fourth input of which is connected to the second inputs of the decoder and the state register, the first output of which is connected to the second input of the shift switch and the first input of the constant shaping node, the second input of which is connected with the nerve output of the decoder and the third input of the shear switch, the output of which and the output of the constant-forming unit are connected to the first output of the block, the second output of which is connected to the second outputs of the re state gistra and decoder.

The temporary interface unit contains a free zone indication unit, a one-shot, a foto, a mode and a time base node, a synchronization indication unit, two AND elements, and an OR element. The first inputs of the synchronization indication node and the first element I are connected to the first input of the block, the second input of which is connected to the first input of the free zone indication node, the third input of the block is connected to the second input of the free zone indication node and through the one-shot with the nerve input of the second element I, the second input which is connected to the output of the synchronization indication node and the second output of the block, the first output of which is connected to the first output of the time sweep formation node, the second output and input of which are connected respectively a second input node and the output synchronization indication OR gate, whose inputs are connected respectively to the output of the second AND gate and via a first AND gate with the output node of the free zone indication.

FIG. 1 shows a block diagram of a processor; in fig. 2 shows a block diagram of a command information processing unit; in fig. 3 is a block diagram of a hardware simulation unit; in fig. 4 is a block diagram of an analysis and electoral logic block; in fig. 5 is a block diagram of a temporary interface unit with memory.

The processor contains a buffer block 1 of commands, a block of 2 basic addressing, a block of 3 registers, a local memory 4, a block 5 of aerial simulation, a block 6 of firmware control, a block 7 of addressing, switches 8, 9, a random-access memory 10, a control memory 11 , arithmetic logic unit 12, data transmission unit 13, virtual address conversion unit 14, unit

15 processing command information block

16 analysis and electoral logic, blogg

17 temporary memory interface. The command information processing unit 15 comprises an address register node 18, a command control selection register 19, an unconditional jump matrix 20, a command selection control decoder 21, a conditional jump decoder 22, a node 23

command buffer synchronization; switch 24 micro-command addresses.

The hardware simulation unit 5 comprises an address transmission switch 25, a register access decoder 26, an output switch 27, a switch-on indication unit 28, and element 29.

Block 16 analysis and selective logic contains a node 30 forming a constant,

switch 31 shift, the decoder 32, the register of 33 states.

The temporary memory interface unit 17 includes a free zone indication unit 34 1, a one-shot 35, a time base formation unit 36, a synchronization indication unit 37, elements 38 and 39, and element 40.

In memory 10, programs are stored, i.e. instructions n operands, according to which the calculations are made. Local memory 4, where information comes from RAM 10 through block 13, serves as a high-speed buffer that stores operands processed in the arithmetic-logical unit 12. Local memory 4 stores general registers, floating-point registers, and working cell processor. The local memory signal 4 is fed to the inputs of the arpfmetico logical unit 12 via switches 8, 9, which select the source of the processed operands, as well as switch the processed bytes during byte processing.

Arithmetic logic unit 12 has a width of two bytes and parallel circuits for simultaneous execution of all the operations embedded in it. The selection of the result of a given operation is carried out at the output of the arithmetic logic unit 12 by a signal from block 16. The processing of words and decimal data is performed in the arithmetic logic unit 12 for two passes in one processor cycle. The result of the operation from the output of the arithmetic logic unit 12 through the block 13 is recorded in the local memory 4 or in the block 3, which contains the interrupt registers, the operation registers, the registers of the selector and multiplex channels. Unit 2 is intended for storing addresses of currently available local memory areas 4 and unit 3, as well as indirect local memory addresses. These addresses come in

unit 2 from the output of the arithmetic logic unit 12, as well as from the buffer unit 1.

The execution of any instruction in the processor is divided into two phases. In the first phase, the command is sampled, during which the command is read from the RAM 10 into the buffer unit 1 through block 13, the formation of the addresses of the operands and the transition to the next phase - the execution phase. In the execution phase, the operation is performed on processing the operands in accordance with the operation code.

All the functions of the processor in phase are controlled by the microprograms stored in the control memory 11. The microcommands read from the control memory II are transferred to the microprogram control unit 6, which generates a sequence of control signals. To quickly read the operands on the inputs of the arithmetic logic unit, the address fields of micro-instructions come directly from the output of the control memory 11 to block 3, local memory 4, block 5 and block 14.

The microinstruction can specify the following actions: processing operands in the arithmetic logic unit 12; reference to the RAM 10 or to the control memory 11; ) the word or unconditional transition to the next microinstruction.

The microcommand for accessing the RAM 10, unlike other microcommands, is executed during two processor cycles. The address to which the call is made can be stored in one of the local memory 4 cells, from where it goes through the switch 9 to the block 7. The block 7 serves to generate the addresses of the access to the RAM 10 or the control memory 11. The source of the address of the operative memory 10 may also be block 14. The address of the control memory And comes either from block 6 or from block 15.

Data for recording in the operational memory 10 is received from block 3 or from local memory 4 via switch 8. Reception of information read from RAM 10 through block 13 to block 3, local memory 4 or buffer block 1 and access to the control memory 11 for the next microinstruction is produced in the second cycle of the microcommand for accessing the memory.

In the sampling phase of the command, all processor functions are controlled by the microprogram-hardware method, i.e., in each processor cycle, except for the actions specified by the microcommand, a series of actions specified by the hardware-generated microcommand address are performed.

Block 15 is intended for analyzing the buffer block 1 and advancing command information in it, storing, building and issuing addresses of instructions and operands, and for managing address arithmetic and instrumental generation of addresses of micro instructions.

Block 5 is designed to simulate the local memory cells 4 by the registers of the block 15 and block 14. When using the microcommand, specific cells of the memory 4 instead of their contents are sent to the output of the local memory 4, the xpaiHinuix command addresses of the operands which are in block 15 and block 14.

Block 14 is designed to translate the logical addresses of the program into absolute addresses of the RAM, depending on the location of the programs and data in the RAM 10. Block 17 is provided for implementing

a memory communication algorithm 10, independent of the parameters and the type of memory.

Block 12 is designed to control the selection of the operation performed in the arithmetic logic unit 12 and switch the input and output circuits necessary for the selected operation.

Consider the work of the processor when executing a command format RX.

At the end of the execution phase of the previous command, in block 15, the address of the micro-command to enter the sampling phase is determined. This address goes to block 7, where it is used to retrieve a micro-command, and from where

returns to block 15 for memorization. There are three cases when going to the command sampling phase depending on the filling of the buffer block 1: the command being executed is completely in the buffer block.

block 1; the executable command is partially in buffer block 1; the executable command is absent in the buffer unit 1. Let the executable command be absent

in the buffer unit 1. Then the first microcommand of the command sampling phase will be the microcommand for accessing the operational memory 10. In this case, the address of the command from block 15 is entered into block 5, and the address

the commands from block 5 are sent to the local memory 4. The executed microcommand as the source of the address indicates the cell of the local memory 4. The information on the cell number is fed to the inputs of block 5 from the output

the control memory 11 and from block 2. In block 5 it is determined that instead of the local memory 4 cell, information from block 15 should be used as the address source. From the local memory 4 output

the address of the RAM is received, through the switch 9 into block 7 and then into the RAM 10. From block 6 the signal of sampling of the RAM 10 enters into block 17.

The information read out from the RAM 10 is transferred to the buffer unit 1 through block 13. At the same time, the microcommand address received in block 15 in the latter generates the appropriate signals for entering and advancing command information in the buffer unit 1. After that, from the buffer unit 1 Block 15 issues a command length code of 2 to determine the address following P1, its double word command information.

9

used in the prefetch, the need for which is determined in block 15.

When operating in the address translation mode, the command address is transferred from the output of block 5 to block 14, where it is translated to the absolute address of the working memory 10. In this mode, block 7 receives the address from block 14. On the status of the buffer block 1 block 15 forms the address of the microcommand prefetch.

When the microcommand prefetch is executed, the addresses of the next double word from block 15 through block 5 and through block 14 enter block 7. In the absence of the translation mode, the address is transmitted through block 14 without changing. At the same time, unit 15 organizes the transfer of the offset from the buffer unit 1 to the output of the local memory 4, from where the offset is fed to the switch 9. The switch 8 is supplied with a base read from the general registers in the local memory 4. The address of the base register goes to block 2 from the buffer block 1.

Double-byte arithmetic logic unit 12 performs processing of input operands. The address arithmetic signal coming from block 15 produces the final result at the output of arithmetic logic unit 12, i.e. ". based address of the second operand coming through block 13 to block 15.

The information from the RAM 10 through the block 13 enters the buffer block 1, where it is gated in accordance with the signals received from the block 15.

The prefetch micro-command is the last instruction in the sampling phase. At its address in block 15, control signals are generated, which are used to modify the address of the command and the address is entered into the firmware of the command execution phase.

In the execution phase, the control information specifying the functions of the arithmetic logic unit 12 is transferred from block G to the inputs of block 16.

The last microcommand of the command execution phase is the microcontrol of the transition to the sampling phase. In the sampling phase, depending on the result of the analysis of the filling of the buffer unit 1, an access to the main memory for command information may be missing.

Block 15 work em as follows.

In the initial state, the node 23 generates a signal about the absence of the executed command in the buffer unit 1. From this signal and the enable signal of the sampling phase coming from block 5, the decoder 22 generates the address of the microcommand for accessing the operational memory 10. This address is fed to the switch 24 and on a signal from

ten

decoder 21, where the absence of the address of the microcommand of the sampling phase in register 19 is analyzed, is output to block 7. During the execution of the first microcommand of the sampling phase, this address from block 7 is entered into register 19, via which the decoder 21 sends to control 5 a selectable control signal as the source of the address register of the address of the executed command, located at node 18, and sends a control signal for the subsequent reception of command information to 23, which organizes the placement of the read information in the buffer unit 1.

After receiving the executable command by the decoder 22, the length and itnn of the command is analyzed, the need for prefetching. According to the results of the analysis, the decoder 22 generates the address of the microcommand of a certain branch of the sampling phase, where the number of microcommands and their type will be different.

Suppose, by the state of the lower bits of the register of the address being executed

commands from node 18 and the length of the command, node 23 determined that the next command is not in the buffer block 1. In this case, the decoder 22 forms the address of the micro-command of the prefetch,

which is outputted to block 7 followed by overwriting to register 19. At the address of the micro-command of the prefetch, the decoder 21 sends to block 5 a signal to output the register of the address of the next double word located in node 18, as the address of the operational memory 10, to block 16 issues a signal address arithmetic with simultaneous supply of a control signal to node 23 to determine the base register address and offset located in buffer block 1, and to block 5 sends a second offset signal for address arithmetic.

Formation of addresses to follow

The micro-commands of the sampling phase are produced by the matrix 20 at the addresses of the previous micro-commands.

The decryptor 21 at the address of the control memory 11 determines the last microcommand of the sampling phase and generates a signal of the final actions of the sampling phase, according to which in node 18 the command information addresses are increased by the length of the executed command depending on its format and double word length, and the decoder 22, using the instruction operation code, generates the output address in the microprogram of the execution phase. Block 5 is activated at each

access to the local memory 4, if the node 28 is in a single state. The reset and installation of node 28 is performed by firmware. The decoder 26 receives the address of the local memory 4 contained in

microinstruction, and determines whether

eleven

it is to the hardware simulated cells of the Local. Step 4. For such cells, when node 28 is turned on, the output of the And 29 element is excited, and information from the output switch 27 is supplied to the output of the local memory 4.

When prefetching, the output switch 27 is supplied with an offset from the buffer unit I. In this case, the access to the main memory goes through the switch 25 to the block 14. During normal access, the output switch 27 receives the address from the switch 25.

During the processing of the operands by the arithmetic unit 12, block 16 arranges operands according to the microcommands set by the zeroes and the result of the previous operation, selects the appropriate circuits for their passage, and selects the desired result at the last level of the arithmetic logic unit 12, in order to improve speed The new functions (AND, OR, EXCLUSIVE OR, BINARY COMPOSITION) embedded in it are executed simultaneously, regardless of the specified operation.

In the sampling phase, a signal is generated by the address arithmetic signal from the output of block 15 in decipher 32, which is used to select the result of the operation of binary word addition during nerve transmission (processing the lower half-word). Register 33, based on the result of the first approach, establishes the input circuits for the second pass (processing the higher half-word) in the arithmetic logic unit 12.

The control information, specifying the functions of the arithmetic logic unit 12, enters the FAS, enters from block 6 the decoder 32 and register 33, where the analysis of the corresponding zeros of the microinstruction and the result of the previous operation is performed and the necessary operation of the specified arithmetic logic is switched block 12, if required, blocking, rearranging part or all of the operand, inverting, as well as memorizing the transfer or taking it into account from the previous cycle.

The decoder 32 samples the desired result.

During the operation of decimal addition, performed in two passes through the arithmetic logic unit 12, according to information that comes from register 33 and decoder 32, node 30, a correction constant is formed, which enters the input of arithmetic logic unit 12 as one of the operands during a second binary addition, in which iB as the other operand uses the result from the first binary addition.

The decoder 32 selects at the output of the arithmetic logic unit 12 the result of two-fold addition in both cycles.

12

When performing the shift operation to the right by 4 bits, the switch 31 performs a special transfer of the shifted operand by reassembling the transmission circuits of one of the inputs and blocking the other input of the arithmetic logic unit 12. The information for filling the bits that are cleared when the switching is not switched is determined in register 33 and transmitted to the switch 31. The shift operation is two-cycle (shifted to the left), with the binary decoder sampling 32 of the result of the binary addition in both cycles at the output of the arithmetic logic unit 12.

The microcommand for memory access is executed in two processor cycles, which are separated by a pause to wait for the read data. The memory area being accessed can

be free or busy working out the previous call cycle or internal data update cycle.

In the nerve cycle of the microcommand on the output of block 7, potential

memory address signals, and the start signal from block 6 enters block 17 on element 38 and node 37, the signal from whose output enters block 6 and prohibits starting the second cycle of the access control micro command before receiving read signal on node 37 from the output of node 36.

The start of the free zone of the operational memory 10 is carried out immediately.

through, element 38, .element OR 40 and node 36.

When occupied by the zone of the RAM 10, its immediate start is blocked on the AND 38 element by a signal from the output of the node 34, on

the input of which receives a busy signal from the RAM 10 and a signal from the block 6, which fixes the moment of the end of the internal cycle of updating the RAM data. The start of the node 36 is made

after the memory zone becomes free. When the memory busy signal 10 is removed on the one-shot 35, an impulse is formed at the end of the memory cycle that arrives at AND 39, the second input of which receives the enabling signal of the memorized query from node 37. The auto-start pulse further through element OR 40 starts node 36 The moment of the beginning of the second cycle in block 6

synchronized by pulses of the clock generator, which ensures minimal loss of time to use the read information. The use of command buffering and apnatural - microprogram processing of command information made it possible to significantly reduce the time of the most frequent microprogram selection of commands due to the greater likelihood of finding the command s

buffer prefetching double

words of command information from operative memory and combining address arithmetic with the mentioned sample, instrumental formation of transitions into microprograms .e sample, autonomous recalculation of the current and pre-emptive addresses of commands.

The hardware simulation unit allowed us to combine the address field of the working area of the local memory and hardware instruction registers and operands, thereby removing the need for an additional microprogram change of the address base in the basic addressing block.

Due to local memory and command buffering, the dependence of the processor speed on the time characteristics of the RAM has decreased. The use of a temporary memory interface allows the processor to flexibly complete the processor with various memory devices with maximum use of their speed. Expansion of the RAM addressing area by introducing an address translation block and using automatic page exchange with an external storage device simplifies programming and facilitates system utilization of the processor in the time and real time division mode.

Thus, the speed of the processor rises compared to machines of a similar class (for example, with the EC-1022 twice at the same cost).

Claims (5)

1. A processor containing a main memory, a control memory, a local memory, a data transmission unit, an addressing unit, a basic addressing unit, a virtual address translation unit, a microprogrammed control unit, an arithmetic unit, a buffer instruction block, a register block, two switches , the output of the first switch is connected to the first inputs of the arithmetic logic unit and the control and main memory, the second inputs of which are connected to the output of the addressing unit, the first input of which is connected to the first output of the conversion unit calling virtual addresses, the first input of which is connected to the output of the control memory, with the first inputs of the data transmission unit, the firmware management unit, the register block and the local memory, the output of the local memory is connected to the first inputs of the switches, the second inputs of which are connected to the first output the basic addressing block, the second output of which is connected to the second inputs of the local memory and the register block, the third input of which is connected to the output of the data transmission unit, to the First input of the buffer command block and to the third input mi-memory and virtual address conversion unit, the second input of which is connected to the first output of the firmware control unit, the second output of which is connected to the third inputs of the switches, the fourth input of the first switch is connected to the output of the register-in block, the first output of the second switch is connected to the second inputs of the addressing unit and the arithmetical unit, the first output of which is connected to the second input of the data transmission unit and to the first input of the unit — basic addressing, the second and third inputs of which are soy Inns, respectively, with the first output of the buffer command block and with the third output of the firmware control block, the fourth output of which is connected to the third input of the addressing block, the first output of the main memory is connected to the third input of the data transmission block, which is different -snaps of speed, an analysis and selective logic block, a command information processing block, a temporary interface block, a hardware simulation block, are entered into it, the first inputs of the hardware simulation block and the block The command information processing is connected to the output of the data transfer unit; the first, second, third and fourth outputs of the hardware simulation block are connected to the fourth and fifth inputs of the local memory, respectively, to the fourth input of the virtual address conversion block and to the second input of the command information processing block, the first to the seventh outputs of which are connected respectively with the second, third and fourth inputs of the hardware simulation block, with the fourth input of the addressing block, with the second and third inputs of the buffer block and commands, with the fourth input of the buffer command block and the first input of the analysis and selective logic block, the first and second outputs of which are connected to the third and fourth inputs of the arithmetic logic unit, the second output of which is connected to the second input of the analysis and selective logic block, the third and fourth the inputs of which are connected respectively to the second output of the second switch and to the fifth output of the firmware control block, the sixth, seventh and eighth outputs of which are connected respectively to the first and second inputs of the time interfacing unit with the memory and with the fifth input of the hardware simulation block, the sixth, seventh, eighth and ninth inputs of which are connected respectively to the second outputs of the buffer command block, base addressing block, virtual address translation block and control output The third and fourth inputs of the command information processing block are connected respectively to the third output of the buffer command block and the output of the addressing block, the third INPUT, the first and second outputs of the time block voltage to a memory are connected respectively to the second output and the third input onerativnoy memory and WTO, ring input control unit firmware. 2. Processor according to item I, characterized in that the command information processing unit contains an address register node, a command selection control register, an unconditional transition matrix, a command selection control decoder, a conditional jump decoder, a command buffer synchronization node, a microcommand address switch the first input of the address registers node is connected to the first input of the block, the second input of which is connected to the pitch input of the conditional jumper decoder, the second input of which is connected to the third INPUT of the block, to the second input the address register node and the first input of the command buffer synchronization node, the first output of which is connected to the third input of the conditional transition decoder, the fourth input of which is connected to the nerve output of the selector control decoder. commands, the second output of which is connected to the first input of the microcommand address switch, second and the third inputs of which are connected to the outputs of the conditional transition decoder and the unconditional-transitions matrix, respectively; the fourth input of the block via the registrar of selection control. the matrix of unconditional transitions and a sampling decoder, the third and fourth outputs of which are connected to the first and second outputs of the block, the third and fourth outputs of which are connected to the first output of the address register node and the output of the address decoder switch, the fifth output of the control decoder. command selection is connected to the second input of the synchronization node of the command buffer, the seventh output of the block and the third input of the address register node, the second output of which is connected to the fifth output block and the third input of the node synchronization buffer. commands, the second output of which is connected to the sh. output of the block. 3. The processor according to claim 1, about tl and h and w; and with the fact that the hardware simulation unit contains an address transfer switch, register decoder, output registers, switch-on indication node, AND element, the inputs of the Turn-on display node are connected to the first and fifth inputs of the block, the third and fourth the inputs of which are connected to the first and second inputs of the address transfer switch, the output of which is connected to the third output of the unit and the first input of the output switch, the output of which is connected to the second output of the block, the seventh and ninth inputs of which are connected to the Inputs of the register access decoder, the outputs of which are connected respectively by the input element I, the third input of the Address Transfer switch and the second input of the output switch, the third, fourth and fifth inputs of which are connected respectively, with the sixth, second and eighth inputs of the block, the output of the switch-on indication unit is connected to the fourth output of the block and through element I to the first output of the block. 4. The processor according to claim 1, characterized in that the block of analysis and selective logic contains a form node | Constant Constants, a shift switch, a decoder and a registrar of states, the first inputs of the decoder, the status register and the shift switch are connected respectively with the first, second and third inputs of the block, the fourth input of which is connected to the second inputs of the decoder and the state register, the first output of which is connected to the second input of the shift switch and the first input of the constant value node, the second input of which is connected to the first output of the decoder and the third input of the switch shift, the output of which and the output of the node formiro.vani. The coistants are connected to the first output of the block, the second output of which is connected to the second outputs of the register of states and the decoder. 5. The processor according to claim 1, characterized in that the temporary interface unit the memory contains a free zone indication node, a one-shot, a time sweep shaping node, a sync indication node, two AND elements, an element OR, the first inputs of the synchronization indication unit and the first element I are connected to the first input of the unit, the second input of which is connected to the first input of the indication unit of the free zone, the third the input of the block is connected to the second input of the free zone indication unit and through the one-shot with the first input of the second element I, the second input of which is connected to the output of the synchronization indication node and the second output of the block, the first output of which is connected to the first output of the time sweep forming node, the second output and the input of which is connected respectively to the second input of the display unit synchronization and the output of the OR element, the inputs of which are connected respectively to the output of the second element AND and through the first element AND to the output of the display unit of the free zone. Information sources, taken into account in examination 1. US Patent No. 3959777, cl. 340-172.5, 1976. 2. U.S. Patent No. 3,656,123, cl. 340- 172.6,1972. and 33