SU1293732A1 - Device for debugging programs - Google Patents

Abstract

The invention relates to computing and can be used when debugging digital computer programs. The purpose of the invention is to improve the speed when debugging programs. For this purpose, registers 3, 5, 7, switches 8, 9, 10, decoders 15, 17, counter 16 microinstructions, triggers 12, 13, i (triggers 12, 13, i (tri L with

Description

14. When performing an interrupt with this device, the device does not require memorization and further restoration of the state of the machine implementing the program being debugged. In this way

f5

one

The invention relates to digital computing and can be used when debugging programs of digital computing control machines (DVUM) .5

The purpose of the invention is to increase the speed of the device.

Figure 1 shows a block diagram of a device for debugging programs.

The device contains the fourth 1, O first 2 and fifth 3 registers, comparison circuit 4, sixth 5, second 6 and seventh 7 registers, first 8, second 9 and third 10 switches, combinational control unit 11, first 12, second .13 to the third 14 triggers, the first decoder 15, the microcode 16 counter, the second decoder 17, the third register 18 input 19 of the interrupt processing end, the second 20 and 20 first 21 clock inputs, 22 interrupt input, 23 output commands, the second 24, first 25 and third 26 information inputs, address inputs 27, the second information inputs 28, inputs 29 command, od 30 interrupts output termination mode 31, the first data inputs 32 and 33 inputs initial installation.

FIG. 2 shows a micro-30 meter 16 counter which is formed by a counter 34, a delay element 35, elements OR 36-39, elements AND 40-43, elements 44 and 45 of a delay g elements And 46-49, a delay element 50.

Вх.26 Рг1 Вх.32 Рг1 Вх.32 Ргб

61.5 78.8 76.3 81.2 78.3 76.2 81.2 78.3 76.4

the time taken to obtain technological information about the processing of the data with a debugged program is reduced. 1 hp f-ly, 3 ill. 1 tab.

0

And 51-54 elements, delay element 55, And 56-59 elements and OR 60 element. FIG. 3 shows a combination unit 11 of a direction containing the first clock inputs 61, the second 62, the third 63, the fourth 64, the fifth 65 outputs, the input 66 interrupt request, third mode control input 67, sixth 68 output, first 69 output of the initial setup, seventh 70 output, second 71 output of the initial setup, eighth 72 output, third

73 exit initial setup, first

74 mode control input, ninth

75 output, mode setting outputs 76, reset indication input 77, second 78 mode control inputs, tenth. 79 outputs, availability 80 input, second 81 clock inputs, first 82 output, elements OR 83-85, elements AND 86-89, element OR 90, element AND 91, elements OR 92-95, elements AND 96-99, elements OR 100 and 101, elements AND 102-110, element OR 111, elements AND 112-114, element OR 115, elements NOT 116 and 117, element AND 118, element OR 119, element NOT 120 and element

And 121.

The combination control unit 11 at each moment of time produces control signals depending on the state of its inputs. The logic of operation of block 11 is given by the logical equations given in the table,

03 10

81.2 (78.3 78.4) 61.2 78.9

61.378,5 61.4 78.6

66 (76.4 76.4 74) 76.4 74

61.6 78.7 80 76.3 Sch16 81.1 78.2 (76.1 76.3) Sch1b 61.6 78.7 80 76.4 74

During operation, the proposed are installed to the data buses of the dna TWO, which is connected to, the programs 45 command outputs 23 of the device to which are to be debugged. In this case, command buses, output 22 interrupt- address inputs 27 of the device connecting to the TWUM interrupt bus, are connected to the address bus of the TWUM command, three command inputs 29 of the device connect information inputs 26 to the control outputs of the UVB device. data output pfs 5fl input interrupt 30 - with a control TWUM, the first clock inputs 2t of the output device UVV, on which the output is with clock psnami DVU, an interrupt request signal. the first information inputs 32 us- signals T1 - T7, respectively, the inputs from which are connected to the output buses of the device — from the control output — the UEVM, the first information output bus of the TWUM, on which developed-moves 25 devices connected to the input response signal (TSS) after you-ny information buses UEVM. complete interrupt. Second information - Second clock inputs 20, device outputs 24 devices are connected to output control devices

Table continuation

UEVM tires for which signals C1 (VP-I1), C2 (VP-I2), SZ (VP-I1) are received from the UEVM, respectively. The output of the end of mode 31 of the device is connected to the readiness bus UEVM, through which the signal of the GT (GT-112) comes from the device. Input setup 33 is connected to one of the control outputs UEVM.

The device commutes to the input of the CEM the interruption request received from the air-blast device or formed in the device itself. In this case, both requests have the same priority. As a result, the request generated earlier is switched to the device output, and the later one is waiting for its turn.

The mode of operation of the device is determined by the code set in the S register and decoded using the decoder 17, which outputs signals 76.1-76.4 at its outputs 76.1-76.4 to the inputs 76 of block 11. In the process of performing each of the modes, the signals generated at each moment

time, are determined by the countercap of the counter 34, decoded in block 15, as well as the state of the trigger 14 (TrA) and the output from the comparison circuit 4 (At

Mode I is designed to start the DVR to execute the program being debugged from the specified command address. In order to implement this mode, signals C1 and C2 are successively supplied from the UEVM. According to the signal C1 supplied to the second input of the element AND 102 through the input 81.1 of the block 11 from the input 20 of the device, in accordance with the state of the counter 34 01, which is permitting, the N тен potential is at the first input of the same

AO). The state of the CHO element, the signal is generated on

as well as signals from the output of the descramble exit 79.2 of the block 11 from the output of the element I 102 in mode I, since in this mode there is a resolution on the third

the input element And 102 from the output of the descramble. The initial installation is carried out, .. t-- 4 G

....-. m, g ... 00 .. 35 Ratio mode via input 76.1 of the block

1 I and the first input of the element OR 111, which through the input 1.2 of the block 16 and the delay element 44 enters the first inputs of the elements AND 40-43. In the second 15, when describing the operation of the device, they are designated with octal codes.

by applying the signal NU to the input 33 of the device, from which it enters the input 77 of the block 11 and through the first inputs of the elements And 92, 93 and 84 generates at the outputs 69, 71 and 73, respectively, lp ,,,,,.

  ry inputs of elements And 40 and 41 giving signals, resetting through

the second inputs are triggers 12-14, and the potential corresponding to the level O is counted, and the inputs of the elements 42 and 43 are the potential of level 1, which corresponds to a drift in the counter 34

34 at the input through input 2 of block 16 to the zero state.

To set the operating mode of the UEVM to the first input of the element 118 and 118 through the input 81.1 of the block 11 from the input 20 of the device, a signal C1 is sent. Since the counter 34 in the initial state is zero, then according to the state 00 of the counter 34, which is the potential potential at the second input And 118, the signal C1 present on its first input is produced

the output 75 of the block 11 signal, the post-55 input 20 of the device enters through the input 81.2 of the block 11 on the control input 1 of the register 11 of the block 11 to the second inputs 18, it records the mode code received from the UEVM via the buses 32 to the inelements I 99, 105, 106 and 110 and the first input of the element AND 104. The signal passes through the element AND 106, since

 formation inputs 2 regis tra 18. With

five

0

five

the output of register 18, the code fixed in it is decrypted in block 17, the outputs of which are fed through inputs 76.1-76.4 to block 11. In addition, the same signal C1 is fed to the second input of the element 97, at the first input of which there is a resolving potential through the first input of the element OR 101 in the state of the counter 34 00, and therefore, at the output of the element AND 97, a signal is generated which, through the sixth input of the element OR 90, the output 79.1 of the block 11, the input 1.1 and the delay element 35 of the block 16, sets the counter 34 to the state 01. I

The state of counter 34 is decrypted in block 15, the outputs of which are fed through inputs 78.1-78.11 to block 11.

Mode I is designed to start the DVR to execute the program being debugged from the specified command address. In order to implement this mode, signals C1 and C2 are successively supplied from the UEVM. The signal C1 applied to the second input of the element AND 102 through the input 81.1 of the block 11 from the input 20 of the device, in accordance with the state of the counter 34 01, which is permissive

the potential, corresponding to the level O, to the inputs of elements I 42 and 43 is the potential of level 1, which corresponds to a drift in the counter 34

5 of code 03. The signals from the outputs of the elements AND 40-43 through the first inputs of the elements OR 36-39 are fed to the information inputs of the counter 34, respectively. The code in the counter 34 is entered

0 sync pulse at its input C, coming from the input 1.2 of block 16 through the delay element 44 and the first input of the element OR 60.

Following this is the C2 signal with

input 20 of the device is fed through the input 81.2 of the block 11 to the second inputs

elements And 99, 105, 106 and 110 and the first input element And 104. The signal passes through the element And 106, since

7

At its other input there is a permitting potential caused by the state of the counter 34 03. At the output 64 of the block 11 from the output of the element AND 106,

There is a signal with the help of which, through control input 1 of register 7, the command code recorded at information inputs 2 of register 7 from inputs 32 of the device is recorded in it. The code received is an unconditional branch command, containing the address of the command from which to run the program being debugged.

In addition, the output element And 110 at the output 79.1 of block 11 through the third input element OR 90 also produces a signal, i.e. on its first input there is a resolving potential through the second input of the element OR 115 in the state of counter 03, which transfers the counter 34 to the next state - state 04. In this state of the counter, the block 11 through the input 61.3 of the TK clock signal from input 21 devices. Due to this, signals at outputs 65 and 79.1 are generated. The signal at output 65 of block 11 is due to the presence of a sync signal at the first input of the AND 107 element from input 61.3 of block 11 and the resolving potential at its other input when the counter is 34 04. The same signal passes through the first input of the element

OR 90 to output 79.1 of block 11. Signal 35 is blocked by output signal 68, and from output 65 through the first controlling trigger to the first input of trigger 12. Input 2 of register 5 rewrites to re- trigger is set to 1 state 5 register 7 from the first run, as a result of which, to the outputs 24 information inputs 3 registers 5. and 23 devices, through the first information, the Signal from output 79.1 translates the counting 40 inputs 1 of switches 8 and 9

34 in state 05. By this state, the counter is allowed to pass to block 11 through input 61.4 of signal T4 from input 21 of the device. Due to this block 11, a signal is output at output 68 in the event that there is no interrupt request from the air-blast device at input 30 of the device and input 66 of block 11. The output of registers 1 and 5 is pre-switched, respectively. At the output of device 22, an interrupt request from this device appears through the input of the commutator 10.

Thus, the interrupt request and command code from the device is received in the DVC. In addition, at output 79.1 of block t1,

jerking is characterized by the presence of a signal that increases the content

counter 34 per l, after which it becomes equal to 06. The following clock signal, which passes the input 61.6 of block 11 from input 2 yy device, is a clock imp. According to state 06 of counter 34, the presence of a signal from a response at input 80 of block 11 from input 19 of the device is interrupted. The specified signal coming

the decisive potential at the first input of the element AND 91 through the element NOT 120 from the input 66 of block 11. At its other entrance there is a resolving potential through the first input of the element OR 94 and the element NOT 117 from the input 76.4 of block 11 in any mode except IV, when the state is analyzed trigger trigger 14. The resolving potential from the output

ten

15

93732 8

And 91 comes through the second input of the element OR 85 to the third input of the element AND 121, at the first input of which there is a clock pulse T4 from the input 61.4 of block 11, and at its second input - the state of the counter 34 - 05. The signal from the output of the element I 121 enters to the output 68 of the block 11 and through the second input of the element OR 90 to the output 79.1 of the block 11. If the indicated interrupt is present, the operation of the device is blocked until the interruption is cleared. Due to the fact that the trigger 12 is in the initial state, the output from its zero arm (first output) generates a enable signal on the first control inputs 4 of the switches 8-10, and the output from its single arm (output 20 turn) forms a inhibitory the signal at the second control inputs of the 3 switches 8-10. As a result, the outputs of the device 24 through the second information inputs 2 switch 8

 The code of the UVB number from the inputs 28 of the device arrives, the outputs 23 through the second information inputs 2 of the switch 9 - the command code from the UVB from inputs 29, and to the output 22 via the first information input 1 of the switch 10 - the interrupt from the UVB from the input 30. After the interrupt from the air-blast is processed and the signal is removed from input 30, the signals 11 and the registers 1 and 5 are turned off by the signal T4 by block 11. At the output of device 22, an interrupt request appears from this device through the input of switch 10.

Thus, the interrupt request and command code from the device is received in the DVC. In addition, at output 79.1 of block t1,

increasing signal

counter 34 per l, after which it becomes equal to 06. The next clock signal that passes through the input 61.6 of the unit 11 from the input 21 of the device is the clock pulse. According to state 06 of counter 34, the presence of a signal is interrogated at the input 80 of unit 11 from input 19 of the device. The specified signal is received

91

when working out. Intercept request message. The signal arrives at the device. The response corresponds to the resolution at the fourth inputs of the And 87 and 88 elements and the third inputs of the And 86 and 89 elements of state 06 of the counter 34 (the resolution at the second inputs of the And elements 86-89). The T6 signal from input 61.6 of block 11 passes through AND 88, since its third input has resolution through the first input of element OR 95 in mode I. The signal from the output of AND 88 through the second input of element OR 83 enters output 70 of block 11. With this signal, through the first input of the flip-flop 13, it is set to one state, which appears at the device output 31, informing the UEVM about the execution of the mode. In addition, the signal from output 70 through the fourth input unit 16 and the element 55 of the delay is supplied to the first inputs of the elements And 56-59. The second inputs of the elements 57 and 59 are supplied with a potential corresponding to the level O, to the second inputs of the elements 56 and 58 - the potential of level 1 which corresponds to the code 34 counter 12. Signals from the outputs of the elec

cops And 56-59 through the fourth inputs of the signal C2. the elements OR 36-39 are supplied to the inje jjj to output the formation inputs of the counter 34 corresponding to the numerical information preferentially. The code in the counter 34 is recorded. The execution of this mode is synchronized at its input C, mode 1 Until reaching the input 16 of block 16 through counter 34 state 06. At the delay element 55 and the fourth input of the element OR 69. After that, the C2 signal is transmitted again input 81.2 of the block through the second input of the element AND 99, since at its other input the resolution of the state of the counter 34 12. The signal from the output of the element AND 99 through the second input of the element OR 93 goes to the output 71 of the block 11j which through the input 2 of the block 16 zeroes counter 34 and through the second trigger input 13 sets it back to its original state.

As in mode I, block 11 receives a signal T6. However, in the presence of a signal from the TSP at the input of the block, a signal is generated from the video signal.

40 elements And 87, and not from the output of the element And 88, as in the previous mode, since in this mode the resolving potential at its third input is due to mode III. This output signal

45 elements AND 87 through the fourth input element OR 90 enters the output 79.1 of block 11 and further to the counting input of block 16, increasing by one the contents of the counter 34, By state

45 elements AND 87 through the fourth input element OR 90 enters the output 79.1 of block 11 and further to the counting input of block 16, increasing by one the contents of the counter 34, By state

Mode II is for inputting a numeric interrupt code into the DVR. 50 counter in block 11 through the input To implement this mode from UEVM 61,5 from the input 21 of the device receives a signal C1. In accordance with the clock signal T5 from the HVAC, the mode code II in register 18 and the so-called one present at the first input, then at the 1st 01 of the counter 34 there is a difference And 103, the second input permitting potentials through the first input 55 is solved by the state counter 34 07, element OR 119 on the second and first and third - mode III. As a result, the inputs of the AND 114 element, respectively, at the output of the AND 103 element, and, as a result, from the output of the element, at the output 82 of the block 11, the resolving potential is formed and the signal received at

ten

O

five

through the second input of the element OR 101 at the first input of the element AND 97, at the other input of which there is a sync pulse C1, which passes through the sixth input of the element OR 90 to the output 79.1 of the block 11.

According to the state of the counter, 02, there is a resolution at the second input of the AND 104 element, the third input of which is due to mode II, and the first clock contains a C2 clock pulse. As a result, there is a signal at the output of the element 104, and, consequently, at the output 62 of the block 11. In addition, a signal is generated at output 79.1 through the third input of the element OR 90 from the output of the element AND 110, the first input of which is resolved according to the state of the counter 34 02 through the first input of the element OR 115, and the second input has a sync pulse. The first of them through the second control input 2 of register 1 enters the numeric code from the inputs 32 of the device through the second information inputs 3 of the register 1, and the second through the counting input of block 16 sets the counter to state 03. Next, the mode is performed similarly to mode I starting from next

0

about signal C2. pjjj is intended to display ygy numerical information on conversion. Execution of this mode by mode 1 Before counter 34 reaches state 06. By condition 06, as well as in mode I, block 11 receives a signal T6. However, if there is a signal OTV at the input of the block, a signal is produced from the video signal.

40 elements And 87, and not from the output of the element And 88, as in the previous mode, since in this mode the resolving potential at its third input is due to mode III. This output signal

45 elements AND 87 through the fourth input element OR 90 enters the output 79.1 of block 11 and further to the counting input of block 16, increasing by one the contents of the counter 34, By state

The 50 counter in block 11, via input 61.5, from input 21 of the device, receives a clock signal T5 from the HVAC, which is present at the first input of the element I 103 ,, the second input split 55 is determined by the state of the counter 34 07, and the third - by mode III. As a result, at the output of the element I 103, and, as a result, at the output 82 of the block 11, a signal is generated that is fed to

the first control input 4 of the register 1 for the census of information from the digital buses 26 TWUM through the second information inputs 1 of the register 1. The digital information from the output of the register 1 enters the first information outputs 25 of the device. In addition, the signal from the output of the element 103 comes through the first input of the element OR 83 to the output 70 of the block 11. This signal sets the trigger 13 to one state, informs the UEVM about the mode, and also through the fourth input of the block 16, the counter 34 is set to 12. Next, the signal C2, as well as in mode I, zeroes the counter and clears trigger 13.

Mode IV is designed to interrupt work when executing a command with a specific address. To implement this mode from UEVM serves signal C1. In accordance with the mode code IV in register 18, there is a resolving potential through the second input of the element OR 119 at the second input of the element AND 114, at the first input of which there is a resolution according to the state of the counter 3.4 01, as a result of which the resolution from the output of the element 114 is fed through the second input element OR 101 to the first input element AND 97, at the second input of which there is a clock pulse. The clock pulse from the output of the element And 97 is fed to the output 79.1 of block 11 through the sixth input of the element OR 90 to the counting input of the block. 16 and translates it into state 02. By state 02 of counter 34, the enable potential is applied to. the first input element AND 110 through the first input element OR 115, at the other input element AND 110 next sync pulse C2 from the input 81.2 of block 11, coming in this mode from the UEVM on the input device. As a result, from the output stroke of the element 110, at output 79.1 of block 11, a signal is generated, which through the counting input of block 16 sets the counter to state 03. The clock signal C2 is simultaneously applied to the second input of element 105, the other two inputs of which are allowed state 02 and mode IV, in

As a result, at output 63 of the block named output 79.3 of block 11, which is a signal from the output of the element 105, which is fed to control input 1 of register 6 and carries into it the stop address code from the inputs

cut input 1.3 of block 16 and the delay element 50 is fed to the first inputs of the elements And 51-54. The second inputs of the elements And 52-54 is supplied potentio

five

five

0 0 5 0 5

32 devices via information inputs 2 of register 6. According to states 03 and 04, the device operates in the same way as in mode I. By state 05, the resolving potential is fed to the second input of element I 121 from input 78.6 of block 11. At the first input of the same element is present a sync signal T4, which passes through element 121 in the event that an interrupt request is not present at input 30 of the device, which is characterized by a permit potential at the first input of element 91, through element NO 120 from input 66 of block 11. Another input of element 91 allowed if triggered 14, then at the first input of the AND 108 element the positive potential from the input 74 of the block 11 through the HE 116 element, and the other input of the AND 108 element is determined by mode IV. The resolving potential from the output of the AND 108 element is fed to the second input of the AND 91 element through the second input of the OR 94 element. The first input of the AND 91 element is open in the absence of a request to interrupt. then, from the output of the element I91, there is a resolving potential at the third input of the element AND 121 through the second input of the element OR 85. As a result, the output of the element AND 121 produces signals at the output 68 and at the output 79.1 through the second input of the element OR 90. The first of these signals through the first input of the trigger 12 sets it to the single state, and the second, through the counting input of the block 16, sets the counter 34 to the state 06. By the state of the counter 34 06 and if there is a signal from the DVUM there are resolving potentials on the second and third inputs element And 86 respectively. The T6 signal present on the first input of this. the element passes through it at the zero state of the trigger 14, which corresponds to the resolving potential at the fourth input of the element And 86, coming from the output of the element 108, the first input of which is allowed at the zero state of the trigger 14 through the element HE 116, and the second is due to the mode Iv. As a result, signal 86 is generated from the output of the AND 86 element.

output 79.3 block 11, which through the input 1.3 of block 16 and the delay element 50 is fed to the first inputs of the elements And 51-54. The second inputs of the elements 52-54 are supplied with a potential 1312.

al, corresponding to the level O, to the second input of the element AND 51 is the potential of the level G, which corresponds to code 10 being entered into the counter. Signals from the outputs of the AND 51-54 elements through the third inputs of the OR 36-39 elements are fed to the information inputs of the counter 34, respectively . The code in the counter is inputted by a clock pulse at its input C, coming from input 1.3 of block 16 through delay element 50 and the third input of element OR 60. According to state Yu, the enabling potential is present at the second input of element 98 and through the first input of element OR 100. At the first input element AND 98 signal T2, which passes from the output of element AND 98 through the second input of element OR 92 to output 69 of block 11. At the same time, a signal is produced at output 79.1 of the block through the fifth input of element OR 90 from the output of element AND 96, on the first and second inputs of which state 10 and T2 are present respectively. The signal from output 69 of block 11 through the second input of trigger 12 resets it to the zero state. As a result, a request is removed for. shutdown of DVR from this device. The signal from output 79.1 according to the previously described circuits sets the counter 34 to state 11. In this state, the device is until the address of the current command, coming from the output of register 2 to the first inputs of the comparison circuit 4, does not coincide with the address set in register 6 and arriving at the second inputs of the comparison circuit. As a result, a signal is generated at the output of the comparison circuit (AT AO). At the same time, the current address supplied to information inputs 1 of register 2 from inputs 27 of the device is rewritten into it for each clock signal T7 arriving at control input 2 of Input 21 devices. Result of the comparison of the addresses from the output of the comparison circuit 4 is supplied to the input 67 of block 11. By the state 11 of the counter 34 there is a resolving potential at the third input of the element 112. If the compared addresses are equal, the resolution is present at the fifth input of the same element, the fourth input of it determined by mode IV. At the second input element And 112 there is a resolution with no

14

interrupt request from the air-blast from input 66 of block 11 through the element NO 120. The signal T1 at the first input of the element I 112 passes through it when the listed conditions are fulfilled and generates at output 72 of block 11 a signal that goes to the second control input 4 of register 5 and overwrites the contents of register 3 through the second information inputs 1, and also sets the trigger 14 to the one state through the first input. In addition, the signal from output 72 goes through the third input of the block 16 and the delay element 45 to the first inputs of the AND 46-49 elements . The second inputs of the elements 46 and 48 are supplied with a potential corresponding to the level O, to the second inputs of the elements 47 and 49 - the potential of level 1, which corresponds to code 05 in the counter. The signals from the outputs of the elements 46 46 through the second inputs of the elements OR 36 -39 arrive at the information inputs of the counter 34, respectively. The code is recorded in the counter by a synchronization signal from input 3 of block 16 through delay element 45 and the second input of element OR 60. Then, state 05 has a resolution at the second input of element AND 121, at the first input of which is a signal T4. The signal T4 passes through the element 121 at resolution of its third input, which is determined by the unit state of the trigger 14 at the input 74 of the block 11 and the first input of the element 109, the other input of which is determined by mode IV. The opening from the output of the element AND t09 is fed through the first input of the element OR 85 to the third input of the element AND 121. Simultaneously with the output 68 of block 11, the output 79.1 of the same block appears through the second input of the element OR 90, the first of these signals coaxes trigger 12, will form an interrupt request, and the second will increment by one the contents of counter 34. As for counter 34 06, there is a resolution on the second inputs of elements 86, 87, 88, 89. After the response signal from the CVD to the generated request appears, on the third entrance dah elements And 86 and 89 and at the fourth inputs of elements And 87 and 88. The unit state of the trigger 14 in mode IV determines the presence of the resolving potentials on

the first and second inputs of the element AND 109. The resolution from the output of the element AND 109 is present at the fourth input of the element AND 89 and through the third input of the element OR 95 - at the third input of the element And 88. The clock signal T6 is fed to the first inputs of the elements And 86-89 and passes through the elements of And 88 and 89, since all their other inputs are allowed for the reasons listed above. The signals from the outputs of the AND 88 and 89 elements form the outputs 70 and 73 of block 11 through the second inputs of the OR elements 83 and 84, respectively, the signals, the first of which takes the counter to position 12 and cocks the ready trigger 13, and the second through the second input resets the flip-flop t4, the output of which is fed to the input 74 of the block 11. Further, as well as in other modes of operation, the counter and the trigger 13 are zeroed by the signal C2.

According to the zero state of the counter 34, it is possible to install from the UEVM any mode of operation of the device without removing the interrupt and repeating the previously issued mode, and by issuing the SOC signal to remove the interrupt request. In this case, if there is an Sz signal, a speed increase, the fourth, fifth, sixth and seventh registers are entered into the device, the first, second and third switches, the first and second decoders, the microinstructor counter, the first, second and third three heras, and the first the information input of the device is connected to the information inputs of the second and third registers and the first information input of the fourth register, the information output of which is connected to the first information input of the first switch and is the first information input device output, the second information input of the device is connected to the second information input of the first switch, the output of which is the second information output of the device, the information output of the fifth register is connected to the first information input of the sixth register, the information output of which is connected to the first information input of the second the switch, the third information and command inputs of the device are connected to the second information inputs of the fourth register and the second switch, respectively

.

25

The input of the device interrupt sign and then through the input 81.3 of the block 11 to the first input of the element And 113 there is a resolution at the second input of the element And 113. The signal from the output of the element And 113 goes to the second input of the element And 98 through the second input of the element OR 100. At the first input of the element AND 98 there is a clock signal T2, which passes to the output 69 of the block 11 from the output of the element 98 and through the second input of the element OR 92. This signal through the second input of the trigger 12 zeroed it, which means interrupt request from data about the device. ,

Claims (2)

Invention Formula 1 .. A device for debugging programs containing a combinational control unit, a comparison circuit, first, second and third registers, the information outputs of the first and second registers being connected connected to the first information input of the third switch and the interrogation input of the combinational control unit, the first information 35 device input is connected to the information input of the seventh register, the output of which is connected to the second information input of the sixth register first, second, third, fourth The 40 and fifth outputs of the combinational control unit are connected respectively to the first and second inputs of the fourth register record, the second register record input, the seventh record input 45 of the register and the first input of the sixth register, the first clock input of the device is connected to the first clock input of the combinational control unit and the record input of the first The register 50, the second clock input and the input of the termination processing of the device are connected respectively to the second clock input and the readiness input of the combinational unit in accordance with the first and second inputs, the initial installation input by the comparison circuit devices, the address input of the device is connected to the initiating input device is connected to the informational input of the first register, p tl and - that, in order to Vanilla reset combinational control unit, the first, second and third outputs of the initial installation of the 5 373216 increase the speed, the fourth, fifth, sixth and seventh registers are entered into the device, the first, second and third switches, the first and second decoders, microinstructions counter, first, second and third triggers, the first information input of the device connected to the information inputs of the second and third registers and the first information input of the fourth register, the information output of which is connected to the first information input of the first switch and is the first information output of the device, the second information The unit's input is connected to the second information input of the first switch, the output of which is the second information output of the device, the information output of the fifth register is connected to the first information input of the sixth register, the information output of which is connected to the first information input of the second switch, the third information and command inputs of the device connected to the second information inputs of the fourth register and the second switch, respectively. five 25 30 input sign interrupt device 30 input sign interrupt device connected to the first information input of the third switch and the interrupt request input of the combinational control unit, the first information 35 input device connected to the information input of the seventh register, the output of which is connected to the second information input of the sixth register, first, second, third, fourth The 40 and fifth outputs of the combinational control unit are connected respectively to the first and second recording inputs of the fourth register, the recording input of the second register, the recording input of the seventh 5 register and the first input of the sixth register, the first clock input of the device is connected to the first clock input of the combinational control unit and the recording input of the first The register 0, the second clock input and the input of the termination processing of the device are connected respectively to the second clock input and the readiness input of the combinational control unit, the input of the initial installation of the device is connected to the input initiating Vanilla reset combinational control unit, the first, second and third outputs of the initial installation ko121293732 connected to zero inputs n t n the first, second and third flip-flops, respectively, the direct output of the second flip-flop is the device ready output, the direct output of the third flip-flop is connected to the first control input of the combination control unit, the second initial setting of which is set by the first inputs of the tenth, eleventh and twelfth elements I, input block interrupt request through the first element is NOT connected to the second input of the first element I.and the first input of the thirteenth element I, the first input of the mode control is connected to the first stroke fourteenth AND gate and via a second NOT member to the first WMOs Dinen with the reset input of the micro-counter of the eleventh element I, the second commands, the sixth, seventh and eighth outputs of the combinational control unit are connected to the single inputs of the first, second and third flip-flops, respectively, the outputs of the first and second decoders are connected respectively to the second control input of the mode and to the control input of the combinational control unit, the seventh output of which is connected to the first by the installation input of the counter Qcocomand, the output of the comparison circuit is connected to the third control input of the mode of the combinational control unit, the eighth output of which is connected to W eye sixth input register write input and the second mounting microinstruction counter, ninth and tenth outputs Raman block connected to the input of the third register and the counting input of the microinstructor counter, the information outputs of the counter and the third register are connected respectively to the inputs of the first and second decoders, the zero output of the first trigger is connected to the first control inputs of the first, second and third switches, direct output the first trigger is connected to the second control inputs of the first, second, third switches and the second information input of the third switch; the outputs of the second and third switch are in the command and outputs an interrupt srotvetstvenno device. 2. The device according to claim 1, 1 and 2, so that the combinational control unit contains thirteen OR elements, twenty-three AND elements, three NOT elements, the first, second, third, fourth, the fifth, sixth, seventh, eighth and nine clock inputs of the block connect yen with the first inputs, respectively, of the elements And, respectively, the second first, second, third, foursome mode setting input is connected to the third, fifth, sixth, seventh, dark blue input of the eighth element And, the eighth and ninth elements And, neck -th input, the first element OR and the fourth clock input of the block is connected to the first input of the sixth element OR the first inputs of the tenth, eleventh and twelfth elements I, the block interrupt request input through the first element is NOT connected to the second input of the first element I. And to the first input of the thirteenth element I, the first control input is connected to the first input of the fourteenth element I and through the second element NOT with the first log in5 0 five 0 50 the mode control input is connected to the second inputs of the ninth and seventh And elements and through the first input of the first element OR to the first input of the sixteenth element And, the third input of the mode control is connected to the first inputs of the seventeenth and eighteenth elements And, the fourth input of the control mode is connected to the second and first the inputs of the eighth and nineteenth elements AND respectively, and through the first input of the second element OR to the first input of the twentieth element AND, the fifth input of the mode control is connected to the first input twenty new The second element And the second input of the second element of the RSHI, the sixth, seventh, eighth and ninth input of the mode control are connected to the second inputs of the third, fourth, sixth and fifth elements of the And, respectively, the eighth mode control input is connected to the second inputs of the tenth, eleventh and the twelfth elements AND, the tenth input of the mode control is connected to the first input of the twenty-second element AND, and through the first input of the third element OR to the second input of the second element AND, the eleventh and twelve inputs of the mode control ineny with the third and first inputs of the first and the twenty-third AND elements, respectively, the seventh clock input block is connected to the second inputs of the sixteenth and eighteenth elements And, the eighth clock. The input of the block is connected to the second inputs of the nineteenth, twenty-first, twentieth and twenty-third elements AND, the first input of the mode setting through the first inputs of the fourth and fifth elements OR is connected to the third inputs of the eighteenth and eleventh with the second input of the seventeenth element And, the third input of the mode setting is connected to the third inputs of the fifth and tenth elements of AND, and the second input of the fourth element OR, the fourth with the mode setting input is connected to the second inputs of the fourteenth and fifteenth elements of AND, the third input of the nineteenth element And, the fourth input of the first element AND, through fO cut the third element NOT and the first input of the seventh element OR with the second input of the thirteenth element AND and the second input of the sixth element OR, the thirteenth input of the mode control connecting 5 yen to the first input of the first element I, the input of the reset initiation is connected to the first inputs of the eighth, ninth and tenth elements OR, the input of the final state of the block is connected to the third inputs of the sixth and twelfth elements I and the fourth inputs of the tenth and eleventh, elements I, the first, second, third, fourth, fifth, sixth outputs of the block are connected to the outputs of the fifth, eighth, nineteenth, twenty-first, third and fourth elements of AND, respectively, the seventh output of the block is connected to the output of the eleventh element OR, first- 30th and tue swarm inputs of which are connected the outputs of the fifth and eleventh lementov And accordingly, eighth ninth block outputs are connected to And accordingly, the tenth output of the block is connected to the output of the twelfth element OR, the first, second, third, fourth, fifth and sixth inputs of which are connected to the outputs of the third fourth, twentieth, tenth, twenty-second and sixteenth elements And respectively, eleventh and The twelfth block outputs are connected to the eighteenth and sixth elements of the outputs. And the thirteenth, fourteenth and fifth exits of the block respectively are connected to the outputs of the eighth, ninth and tenth elements OR, respectively, the fifteenth The AND element is connected to the second input of the seventh OR element and the fourth input of the sixth AND element, the output of the fourteenth element AND is connected to the first input of the thirteenth element OR, the second input of which is connected to the output of the thirteenth element AND, and the output is connected to the third input of the fourth element AND , the outputs of the ninth and seventeenth elements. And connected to the second inputs of the third and first elements OR, respectively, the outputs of the second and twenty-third elements And connected to the second inputs of the eighth and ninth elements IL, respectively Of course, the second input of the twenty-second element AND is connected to the first input of the second element AND, the output of the fourteenth element AND is connected to the third input of the fifth OR element and the fourth input of the twelfth-output of the twelfth the outputs of the first and seventh elements35 of that element And, element And is connected to the second input, the tenth element OR. 3-t the first, second, third, fourth, fifth and sixth inputs of which are connected to the outputs of the third, fourth, twentieth, tenth, twenty-second and sixteenth elements AND respectively; the eleventh and twelfth outputs of the block are connected to the outputs of the eighteenth and sixth elements AND respectively, the thirteenth, eleventh and fifteenth outputs of the block are connected to the outputs of the eighth, ninth and tenth elements OR, respectively, the output of the fifteenth element AND is connected to the second input of the seventh element OR and the fourth the input of the sixth element AND, the output of the fourteenth element AND is connected to the first input of the thirteenth element OR, the second input of which is connected to the output of the thirteenth element AND, and the output is connected to the third input of the fourth element AND, the outputs of the ninth and seventeenth elements. And connected to the second inputs the third and first elements OR, respectively, the outputs of the second and twenty-third elements AND connected to the second inputs of the eighth and ninth elements IL, respectively, the second input of the twenty-second element AND connected to the first input m of the second element And, the output of the fourteenth element And is connected to the third input of the fifth element OR and the fourth input of the twelve - output of the twelfth of the element And,