SU1661766A1 - Fault simulation device - Google Patents

Abstract

The invention relates to computing and is intended to simulate faults in the active devices of computer systems in an experimental study of their reliability. The aim of the invention is to enhance the functionality of the device by simulating failures and failures of active devices. A device for simulating faults includes a block for extracting and analyzing input information 8, containing RAM, encoders, triggers, multiplexer, bus driver unit, counters, delay element, registers, processor blocking unit consists of an encoder, the malfunction simulation unit contains a microcommand register, registers, multiplexers , encoders, descrambler, SIS, ALU, trigger, registers, counter, clock generator, RAM, write control unit, including a bus driver unit, decoder, registers, trunk receiver. The BVI selects the transmission cycle of the information layers to the processor, identifies the source of the message, compares and controls the number of simulated faults. The BP unit performs the functions of blocking the process of inputting the information word to the PR. Fault Simulator Simulates Fault. The recording control block is used to record information in the RAM, counters and control the operation modes of the blocks. The device performs a number of different fault simulation commands, depending on the sequence of information words (commands, addresses, data, interrupt vectors). In this case, physical malfunctions of active computer devices, such as a processor, disk controller, etc., are simulated. The application of the proposed device in the process of experimental investigation of the reliability of BC devices significantly expands the number of simulated faults, which makes it possible to increase the reliability of estimates of the reliability of these devices. 7 il.

Description

The invention relates to computing and is intended to simulate faults — failures and failures of various durations and

the multiplicity of processors working in the composition of computers (complexes) in real time, and can be used to experiment

Rationally investigating the reliability of fault-tolerant computing systems.

The purpose of the invention is to expand the scope by simulating failures and failures of active nodes.

FIG. Figure 1 shows the complex for the study and imitation of failures and failures and references of active devices; on Ј | ig. 2 is a block diagram of the selection and analysis of input information (BWA) and block processor blocking (PSU); in fig. 3 - block diagram of the simulation of faults (VIN); in fig. 4 is a diagram of a write control flock (AUS); in fig. 5 is a timing diagram of the device for simulating malfunctions for the case when the conditions for simulating malfunctions are highlighted; in Fig. 6 (the same, for the case when the conditions for the imitation of the malfunction are not highlighted; Fig. 7 is a fragment of the timing diagram

The complex for investigating and simulating failures and failures of active devices (Fig. 1) contains a device 1 for simulating faults, an information bus 2 and a control 3 inputs, an information 4 and a control 5 outputs, a computer 6 and a trunk 7,

The device 1 (Fig. 1) contains the BVA 8, BP 9, BIN 10, BUZ 11, trunk 12, tires 13-18, highway 19, tires 20 and 21,

FIG. 2 shows diagrams of blocks 8 and 9 containing the first memory block 22 (RAM), encoders 23,24, triggers 25-27, multiplexer 28, block

29shine shapers counters

30-32, delay element 33, first and second registers 34, encoder 35, communications 36-39 of blocks 30-32 and 24, respectively, with outputs of register 40 (Fig. 3).

FIG. 3 shows block 10. It includes a register of 40 micro-commands (RMK), external devices 41-45 connected to block 10, registers 46-51, multiplexers 52-54, encoders 55-57, decoder 58, block 59 comparisons, arithmetic logic unit (ALU) 60, trigger 61, registers 62.63 bus driver 64, counter 65, clock pulse generator 66, second memory block 67 (RAM).

FIG. 4 shows a block including a decoder 68, registers 69-74, trunk receiver 75.

about

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five

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five

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five

Line 7 is conventionally divided into two groups of buses - informational 7 (, and control 7 (2). Block 9 performs the functions of blocking the process of inputting the information word into the active device (processor).

Block 8 performs the following functions;

the allocation of cycles of transmission of information words to the active device from the total flow of transmissions on tires 2-5;

identifying the source of the message (memory or external device) and determining the type of information word entered by the active device: command, data;

comparison of the words entered by the processor with the given etalons and selection of the moments of time of occurrence of certain words or their sequences (selection of certain sequences of information words);

control of the number of simulated malfunctions (repetitions of certain firmware simulating malfunctions).

Block 10 performs the functions of simulating faults (the consequences of faults in the form of distortions of information words stored in the memory elements of the processor). It blocks the outputs of information sources on the interface and generates sequences of signals necessary for transmitting information sequences to the processor (these can be commands, addresses, data) for reading information words from the processor (device 1 acts as a receiver of information) to distort the read information words and transfer them to the processor.

The recording control unit 11 is used to record information in blocks 4.22, 67, 30-32 and control the operation modes of blocks 8-10.

Highway 12, going from block 11, includes 6 groups of tires.

12 (1) - a 16-bit tire information group connected to the information inputs of block 22;

12 (2) - a 20-bit bottom information group of buses connected to the address inputs of block 22 (via multiplexer 28);

13 (3) —32-the bottom of the information group of tires connected to the information inputs of block 67;

516

12 (A) - 10-bit bottom information group of buses connected to the address inputs of block 67 (via multiplexer 53);

12 (5) - 16-bits of the information group of tires, connected to the information inputs of the counters 30-32;

12 (6) - 12 (20) - control buses;

12 (7) - 12 (10) - enable blocking of the imitation of a malfunction from the corresponding counter 30-32;

12 (11) - 12 (13) - record counters 30 - 32, respectively;

12 (14) - signal Reset E of the initial installation;

12 (15) - signal recording unit 22}

12 (16) is the control signal for multiplexer 28;

12 (17) is a control signal for multiplexer 53;

12 (18) - signal recording unit 67.

The functional purpose of the component parts of block 8 is as follows.

The encoder 23 and the triggers 25-27 with the appropriate links perform the allocation of transmission cycles of information words to the processor, the identification of the source of the message and the determination of the type of information word.

The input of the encoder 23 receives the following signals:

X (- sign of processor addressing;

X - a sign of the source of information: memory, external device

X, is the command sign: set to 1 if the processor enters a command;

 - signals of prohibition of analysis of certain information words, respectively X - all, X §- - commands, Xg - data from the VU; - control signals from input 3;

X7 - signal sign of addressing (PRA);

X- is the address acknowledgment signal (П11А);

Xcj - signal of the external device (PVU);

X, 0 is the signal of the receiver (PP);

Hz - blocking signal reset reset (BSV);

X4 / i - data request signal (PD);

X4 - data availability signal (ND);

X, d - signal reset (initial installation);

X (- signal Blocking the transfer process to the processor installed;

766 ,,

 - command input signal - means that the processor enters the command;

X17 - Signal Analysis Result - means the presence of an analysis result on the coincidence of reference values with the analyzed ones;

X, „- signal Condition imitations not yi

health highlighted;

X “- the block of imitation of malfunctions works;

2 a write signal to block 22. The outputs of the encoder 23 control the setting and resetting of the triggers 25-27

g (), writing and reading block 22 - Y-p, Yg, and also participates in the logic of the encoder 24 (Y-).

The trigger 25 serves to memorize the addressing cycle, since any exchange

Information on the interface begins with the addressing cycle executed by the processor, all cycles (including the input cycles of information words into the processor) are preceded by an addressing cycle. The signal from the output 25 of the trigger is fed to the input X of the encoder 23.

The trigger 26 serves to memorize the type of device — external or memory — that will act as

about the source of information for the processor. The trigger 27 serves to memorize — the selection of the instruction by the processor (instruction indication).

The signals from the outputs of the flip-flops 26 and 27 are fed to the inputs of the block 23, as well as the multiplexer 28, and participate in the shaping of the read signals of the block 22 and the address at which the information is read.

Q Three inputs of block 23 - are connected to the output of register 34 and serve to control the sequence of analysis of input words for the processor. Management using these outputs makes it possible to analyze either all words entered by the processor, or only words read from the memory (words from the control unit are not analyzed), or only words from the memory that are commands, etc. moreover, the sequence of analysis of words can be given completely arbitrarily in block 22.

Block 22 is designed to compare the words entered by the processor with the 5 given standards. To the address input of block 22, informational words are received from the information group of buses 2.4, through the bus driver and multiplexer 28 from outputs Y7 and Ys of block 23

five

15

20

25

signals are read. The result of the comparison is fixed to register 34.

The information outputs of block 22 are divided into 3 groups: D1, D2, D3.

D1 is a 6-bit busbar group, 3 times it is used to control the sequence of the input analysis, and 3 bits are indications of a sequence — i.e. use Qs to select specific sequences.

D2 - 2-bit bottom tire group:

1 bus - Failure simulation conditions highlighted;

Bus 1 - Unblocking the word transfer process to the processor (no conditions selected).

D3 is an 8-bit bus group through which the initial address of the fault simulation firmware is transferred to block 10.

The multiplexer 28 serves to organize the recording in the presetting unit - the address is fed to the input 12 (2) of reading at the address that comes to the second information input of the block 22. The control input - 12 (16) of the multiplexer 28 is connected to the register 74.

Register 34 is used to capture data from the output of D1 and D2 of block 22. The register is divided into two parts, which are recorded by one signal, and the reset inputs are different. The output of the register is 34, with connected to the input. - The result of the comparison does not have a corresponding output to the RAM 22. The input corresponding to this output is connected to -M.

The delay element 33 serves to organize the recording in the register 34 of information from the output of block 22.

The bus driver unit 29 includes 4 chips K589AP26 and serves to match the signals from 16 address buses (data to the input of multiplexer 28).

The number of repetitions can be recorded on each of the counters 30-32 for three different fault simulation firmware. The encoder 24 controls the reset of the register 34 in the event that the number of repetitions of fault simulations is exhausted (counters 30-32 cleared) on the control from the encoder 40 or 74.

The inputs of the encoder 24 receives the following signals:

Xo reset signal from the encoder 23;

thirty

40

45

50

55

five

0

five

Q

, with

thirty

40

45

50

55

 - Equalization signals of Ochikov 30 - 32, respectively;

 - enable signals (reset) of register 34 from; ,

Ho - reset signal from register 74}

X- - reset signal from register 40.

The outputs Y and Y of the encoder 23 reset the first and second parts of register 34, respectively.

The encoder 35, which performs the function of blocking the process of transmitting the information word to the processor and is included in block 9, has the following inputs:

X. - Process lock signal

transfer set (CPU lock);

I

X - unlock processor

from RMK 40;

X - - unblocking the transfer process (if the conditions for simulating a malfunction are not highlighted).

FIG. 3 shows the component parts of block 10. A group of RAM 67, registers 40, 46-51, 62, 63 of encoders 55-57, decoder 58, distortion and comparison schemes 59, multiplexers 52-54, ALU 60, trigger 61, clock generator 66 Pulses is a firmware automaton that performs the functions of conditional and unconditional signal generation through buses 2-5 for recording and reading processor memory elements, performing the analysis of read words — codes from ROH, SC, CSP, US, performing analysis of the state of internal elements memory and conditional transitions depending on separate audio bits and sets them in the analyzed words.

The address for RAM 67 can be configured in seven different ways and fixed at SC 65;

Recorded from the output of the RAM 22-D3 through the M 52. Thus, the initial address of the malfunction simulation firmware is set.

Increase by +1, which corresponds to the unconditional transition and is controlled by the signal X from the output of the PMK 10;

Increasing by -H, depending on the state of tires 2-5, allocated by block 59 (signal X to Ø 55) is controlled by signal X from the output of the PMK 40.

Change by 1 in the highest (10th) rank, depending on the state

flip-flop 61 and block 59, which is controlled from the output of the PMK 40;

Change to 1 in the 9th bit, which corresponds to the conditional transition, depending on the analysis of certain bits in the codes recorded on registers 62 and / or 63 using the ALU 60.

Through the second input of M 52 from the output of P 46 to the SC 65, during the execution of the firmware, any address can be written. Modes 1-6 are used during firmware execution.

In the mode of initial installation (recording) of RAM 67, through the input 12 (4) M 53, any address can be fed to the address input of RAM 67.

The encoder 55 controls the writing, incrementing by +1, resetting the SC 65, writing and reading the RAM 67, gating the LH 58.

The inputs of the W 55 receive the following signals;

Xj-Xj - clock signals;

X, - conditions of imitation of malfunction are highlighted;

Xg- - signal recording RAM 67;

Xg - reset signal (initial setting);

X - reset signal (from counters 30-32);

X - condition signal from block 59;

HD - reset signal (from RMK 40);

X. - unconditional transition of the 2nd type;

X (- conditional transition of the 3rd type;

 - Work RMK 40;

 - record counter;

-40

The outputs of the encoder 55 perform the following functions:

Y - increment of SCh 65

Y2 - record SC 65;

UZ - reset of SCh 65; 45

V4 - signal Sampling crystal RAM 67;

Ys - signal Write / read RAM 67;

Y, is the gating signal of the decoder 58.

In the RAM 67, firmware imitations of malfunctions in the processor, consisting of sequences of microinstructions, are recorded.

In the process of executing microprogram microprograms one by one after 50

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They are properly connected to the RMK 40, the outputs of which control:

permission to issue an information word from the R 47 tires 2-5;

permission to issue data from register 48 to tires 2-5;

the direction (switching) of information in M 52;

writing registers 63 and 62, respectively;

reset the midrange 65;

unconditional transition of the 2nd type (Hyu) to II 55;

unconditional transition of the 3rd type (Х „) to Ш 55;

the work of the RMK 40;

record counter 65;

operation code on the ALU 60;

resolution analysis of the corresponding output of the ALU 60;

increments of +1, respectively, MF 30-32;

resetting the register 34 (input X Ш24) by signal 39;

removing the blocking of the transfer of the information word to PR 2 (signal 20);

setting blocking information sources (signal 18);

blocking the process of analyzing informational words by block 8 (signal 17);

the direction (switching) of information in M54;

writing and reading the register 51;

trigger resolution 61.

Register 46 is used to write jumper addresses in the firmware (10-bit register).

Register 47 is intended to record address codes, data commands, and other information words transmitted via lines 2-5 to the processor.

Register 48 is used to issue control and implementation signals to the IAS buses 2–5, thus implementing various interface modes.

Registers 49.50 are used to set the operation modes of the comparison unit 59 by setting the distortion codes or bit numbers to be compared, as well as the values of the bits to be compared. The logic of operation of block 59 is represented by a table and a system of minimized switching functions (PF) .. X, X2 X3 Y z Yt X, (X2 © X3) - the comparison code

v -X (X2 © X) + X, Xg - distortion code

Register 51 records codes of distorted information words, which will then be transmitted to the processor.

Registers 62 and 63 record informational words transmitted from the processor or read from the processor during a fault simulation.

The decoder 58 is designed to control the recording registers 46-50, RMK 40.

Distortion multiplexer 59 is used to add 3 types of distortion to the information words read from the processor (or transmitted to it): constants O, constants 1, inversion of the logical value of the bit. The code thus distorted is written through M 54 to P 51.

ALU 60 is used to introduce other types of distortions into information words read from the processor into information words read from the processor (transmitted to it). This may be addition, subtraction, etc. over a certain code through other logical operations. The distorted code from the output of ALU 60 through M 54 goes to R 51. Another purpose of ALU 60 is to organize (together with W 56) conditional jumps - depending on the results of operations on operands R 62 and R 63. Four information bits from the output of ALU 60 are fed to the input of W 56, and depending on their values, bit 10 of the address of RAM 67 will be formed.

Elok 59 is necessary to perform the operation of comparing codes on buses 2-5 with codes set on registers 49, 50.

On the flip-flop 61, a bit 10 of the address of the RAM 67 is formed. The encoder 57 serves to set the mode of the register 51 - write or read.

The multiplexer 53 serves to transfer the address to the input of the RAM 67 from the output of the SC 65 or the register.

0

five

0

five

0

five

0

five

The operation of the device 1 includes 2 modes:

pre-setting (writing) in the information RAM 22 for synchronization and in the RAM 67 of the fault simulation firmware;

condition condition selection and fault simulation.

At the initial moment of time (after turning on the power), the interface 7 generates a reset signal, which through the MP 75 resets the registers 69-74, sets the signals equal to O at their outputs. The output 12 (14) of the register 74 resets (sets) to О all connected elements to it at 12 (14) 0: registers 46-51, 40, MF 65, triggers 25-27. Register 34 is reset by signal 12 (7) 0. After that, the microcomputer 6, via the trunk 7, performs a program of presetting RAM 22 and RAM 67. For this, addresses 70 and 72 are written to RAM 22 and 67, and registers 69 and 79 are data. Register 74 is recorded first by controlling bits of multiplexers 12 (16) and 12 (17), then recording controls 12 (15) and 12 (14), respectively. Thus, in RAM 22 and RAM 67, one word is written. To write several words (firmware), the actions are repeated as many times as required.

Counter 30-32 records the number of repetitions for the three firmware, although in principle they may not be specified. After the information is recorded in the RAM 22 and the RAM 67, the reset signals 12 (7) and 12 (14) are removed in P 74. The corresponding bits are recorded 1 and the signal 12 (6) is set - blocking the process of transferring information to the processor. Setting this signal is the beginning of the transition to the second mode of operation. After the installation of signal 12 (6), the operation of the encoder 35 is enabled, the logic of which is described by system III (1).

Y, X ..

Yt-x

hg he

(one)

The signal U2 from the output of the encoder 35 allows the operation of the encoder 23, the logic of which is described by the PF (2)

Y, X

one

Yi. Y

15g X7- Xg X10

H

X7-X “j.

X × + X

(7 Х1б Х15 + Х)

(2)

X16- X, 5

Y $ -AV

YT-X№. X „- (X1-X4 + X5-Xg + X6.X3) + X

. Х „- (Х, -Х4 + Х. Х2 + Х6-ХЭ)

Y ") X17 X1 X1Ј X48

Register 34 is cleared by a signal.

Y from the output of Ш 23 (via encoder 24) in the event that the analysis of the input information was carried out and the conditions were not selected. The work of the encoder Ш 24 is described by P (3)

Y, X2.X5-X X6 + X4-X7 + X3 + X9 + X, (3)

Ґ4 - Hg. X7-X8n-X,

The signals Y and Y flush register 34 differently in order to be able to select specific sequences of information words entered by the processor. The lower part of the register is reset after each word is entered into the processor and the device analyzes; the upper one stores information to proceed to the analysis of the next word in the sequence.

The timing diagrams of the operation of the BP9 and BVA8 units are shown in FIG. 5 and FIG. 6. FIG. Figure 5 shows a case in which malfunction simulation conditions are highlighted and the word transmitted to the processor is distorted; FIG. 6 — The conditions for simulating a malfunction are not highlighted and the processor lockout process is cleared.

The time diagrams accept the following notation:

BLP - processor lock (signal 13);

ShAD - 16 tires 2.4 data addresses}

T25, T26, T27 - signals from the outputs of the trigger 25-27, respectively;

PC - a sign of the command (signal X at the input W 23);

MF signal

Y-, output M 23 (read RAM 22);

HALL - register recording signal 34 - from output 333;

RA - the result of the analysis (at the entrance of Ш 23);

BIN - works BIN 10.,

After installing signal 13 at time T, the processor performs the normal addressing cycle on buses 2-5,

ten

,five

20

25 -

35

40

45

,

50

55

which consists in the generation of address signals at the SEC, as well as the signals of the PVU, SPR, BSV, PRA. The PPA signal is generated by the information source. Triggers 25-27 are set in accordance with the logic of the encoder 23. Analysis of the word transmitted to the processor occurs at time T — after the source sets the ND signal, the occurrence of which will lead to reading RAM 22 and writing the contents of RAM 22 to register 34. If In the word read from RAM 22 is set to 1 bit, connected to bus 15, block 10 is activated.

The operation of block 10 is shown in more detail in FIG. 7 and corresponds to the time period T5-T8 in FIG. 5. The signal from bus 15 is fed to the input of the encoder 55. The logic of the operation of the encoder is described by the following PF system (4)

YJ X, + X (X ,,. X g

 IT. X | ,

Y, X6 + X7 + X9 Y4 X5 + X4 Xg

v Y - le

(four)

The timing diagram of the operation of block 10 is shown in FIG. 7. At time T1, a PMK 40 is recorded by a code word (a microinstruction containing an unconditional jump bit (X (0) from the output of RAM 67, then P 47 (T2) is written (the word for transmission to the processor), P49 (TK) and P50 (T4) - to configure block 59, the register P 51 - at time T, after the end of the recording of the PMC 40, the codes of the distorted information words are entered.

Writing and reading the register 61 controls the encoder 57, the logic of which is represented by the PF (5)

Yi-X1 (5)

Y x x s

The application of the proposed device will significantly expand the classes of simulated malfunctions of active modules of computing systems by analyzing commands, the state of memory elements in these modules and analyzing commands, addresses, data, interrupt vectors arriving at their inputs, and simulating faults depending on this information and thus essentially

2

to increase the depth and detail of experimental studies of aircraft reliability conducted with the help of a device.

Claims (1)

Invention Formula A device for simulating faults, containing a clock generator. pulses, first and second memory blocks, three counters, three registers, two blocks of bus drivers, delay element, first encoder, arithmetic and logic unit, four. the trigger and the first decoder, the first output of which is connected to the input of the first register, the information inputs of the group are connected to the outputs of the group of the first block of bus drivers, the inputs of the group are informational inputs of the device group, the address inputs of the first decoder group devices, characterized in that, in order to expand the field of application of the device for. imitation of malfunctions of active nodes, a second decoder, a comparison unit, four multiplexers, a counter, 8 encoders, fourteen registers and a trunk receiver, whose output is connected to the reset input of the first to sixth registers, are entered into it, the second and third outputs of the first decoder are connected with a recording input and a clock input, respectively, of the second register, the outputs of the group of which are connected to the information inputs of the first group of the first multiplexer, the outputs of the group of which are connected to the address inputs and groups of the first memory block, whose information inputs of the group are connected to the outputs of the first register, the fourth and fifth outputs of the first decoder are connected to the recording input and the clock input of the third register, respectively, the outputs of the group of which are connected to the information inputs of the second memory block, input the first counter is connected to the first output of the sixth register, the recording input and the clock input of which are connected to the sixth and seventh inputs of the first decoder, the eighth output of which is connected to the recording input The Fourth register group outputs are connected to data inputs 3 five five 0 -. , 5 building 35 50 55 the first group of the second multiplexer, the outputs of which are connected to the address input of the second memory block, the ninth output of the first decoder is connected to the recording input of the fifth register, the outputs of the group of which are connected to the information inputs of the first, second and third counters, the outputs of which are connected to the first, second and third inputs of the first encoder respectively, the fourth, fifth, sixth and seventh inputs of which are connected to the second, third, fourth and fifth outputs of the sixth register, respectively, the sixth output of which o is connected to the first input of the second encoder, the first output is the first output of the device, the information inputs of the second-sixth group of registers are connected to the outputs of the group of the first bus driver, the seventh output of the sixth register is connected to the write input of the second counter, the write input of the third counter is connected to the eighth output of the sixth register, the first and second outputs of the third encoder are connected to the S and R inputs, respectively, of the first trigger, the output of which is connected to the first input of the third encoder, the second input of which This is connected to the output of the second trigger, the S and R inputs of which are connected to the third and fourth outputs of the third encoder, respectively, the third input of which is connected to the output of the third trigger, and the S and R inputs of which are connected to the fifth and sixth outputs of the third encoder, respectively The fourth, fifth and sixth inputs of which are connected to the outputs of the first group of the seventh register, the recording input of which is connected to the output of the delay element and to the recording input of the eighth register, the clock input of which is connected to the first output of the first cipher A torus, the second output of which is connected to the clock input of the seventh register, the information inputs of the group, is connected to the outputs of the first group of the first memory block, the selection input of which is connected to the seventh output of the third encoder, the seventh to thirteenth inputs of which are the control input and the group the second bus driver, and the fourteenth input is connected to the ninth output of the sixth register, the second output of the second encoder is connected to By the fifteenth input of the third encoder, the sixteenth input of which is the input of the input of the device command, and the seventeenth input is connected to the first output of the eighth register, the second output of which is connected to the second input of the second encoder, the third output of the eighth register is connected to the eighteenth input of the third encoder, nineteen the input of which is connected to the tenth output of the sixth register, the eleventh output of which is connected to the control input of the first multiplexer, the information inputs of the second group of which are connected to the outputs of the second group of the seventh register, with the outputs of the second and third triggers, with the outputs of the group of the second bus driver, the eighth output of the third encoder is connected to the input of the delay element and the read-write input of the first memory block, the information inputs of the group of the eighth register are connected to the outputs of the second group - the bits of the first memory block, the outputs of the third group of which are connected to the information inputs of the first group of the third multiplexer, the information inputs of the second group of which are connected to the outputs of the group the register, the information inputs of the group of which are connected to the outputs of the first group of the second memory block and the information inputs of the group of the tenth to fourteenth registers, the outputs of the second group of the second memory block are connected to the information inputs of the group of the second decoder, the first to the fifth outputs of which are connected with the input of the record of the ninth-thirteenth registers, and the sixth output is connected to the input of the fourteenth register, the first output of which is connected to the resolution input of the eleventh register, the second output is nen to the input resolution tenth register fourteenth third output register coupled to the control input of the third multiplexer whose outputs are connected to groups of information inputs of the fourth group counter, the count input of which is connected to the first output of the fourth encoder, a second output connected to WMOs Record house of the fourth counter, the reset input of which is connected to the third output of the fourth encoder, the fourth output of which is connected to the input 0 -n, 5 Q% Q 5 - five five the selection of the second memory block, the read write / read of which is connected to the fifth output of the fourth encoder, the first, second and third inputs of which are connected to the first, second and third outputs of the clock generator, respectively, the fourth input of the fourth encoder is connected to the third output of the eighth register, the fifth input is connected to the twelfth output of the sixth register, the thirteenth output of which is connected to the control input of the second multiplexer, the information inputs of the second group of which are connected to the outputs of the fourth group the first counter, with the output of the fourth trigger and the output of the fifth encoder, the inputs of the first group of which are connected to the outputs of the first group of the arithmetic logic unit, the outputs of the second group of which are connected to the information inputs of the first group of the fourth multiplexer, the information inputs of the second group of which are connected to the outputs of the group Comparison unit, the output of which is connected to the D-input of the fourth trigger and the sixth input of the fourth encoder, the seventh input of which is connected to the eighth input of the sixth regit and with the reset inputs of the ninth through sixteenth registers, the fourth and fifth outputs of the fourteenth register are connected to the recording inputs of the sixteenth and seventeenth registers, respectively, the information inputs of the group of which are the information input of the device group, the first output of the first encoder is connected to the eighth input of the fourth encoder, the ninth - thirteenth inputs of which are connected to the sixth - tenth outputs of the fourteenth register, the eleventh t thirteenth outputs of which are connected to the inputs of commands of the ar group an optical logic device, the information inputs of the first group of which are connected to the outputs of the sixteenth register group, and the information inputs of the second group are connected to the outputs of the seventeenth register group and to the inputs of the first group of the comparison unit, the inputs of the second group of which are the control inputs of the device group, information the inputs of the group of which are the inputs of the third group of the comparison unit, the inputs of the fourth group of which are connected with the outputs of the twelfth register, the outputs of the thirteenth register group are connected to the inputs of the fifth group of the comparison unit, the inputs of the second group of the fifth encoder are connected to the fourteenth to seventeenth outputs of the fourteenth register, the eighteenth, nineteenth and twentieth outputs of which are connected to the counting inputs of the first, the second and third counters, respectively, the twenty-first output of the seventeenth register is connected to the eighth input of the first encoder, the ninth input of which is connected to the ninth output of the third encoder, The second input of the second encoder is connected to the twenty-second output of the fourteenth register, the twenty-third output of which is an output of the device, the twentieth input of the third encoder is connected to the twenty-fourth output of the fourteenth register, the twenty-fifth output of which is connected to the control input of the fourth multiplexer, the outputs of the group which is connected to in  Shig.1 five five 0 The friths of the pnadt register group, the recording and resolution outputs are connected to the first and second outputs of the sixth encoder, respectively, the first input of which is connected to the twenty-sixth output of the fourteenth register, the twenty-seventh output of which is connected to the second input of the sixth encoder, the third input which is connected to the fourth output of the clock generator and to the C input of the fourth trigger, whose R input is connected to the twenty-eighth output of the fourteenth register, the sixth output of the fourth encoder connected to the enable input of the second decoder, the input of the trunk receiver is the device reset input, the outputs of the tenth and fifteenth registers are the information outputs of the device group, the outputs of the eleventh register group are the control outputs of the device group. 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