SU1001103A1 - Program interruption device - Google Patents

Description

The device relates to computer technology and can be used in interrupt systems of digital computers.

A device for interrupting ⁵ programs is known, comprising an interrupt register, a mask register, a priority block, OR elements, an encoder, a priority prediction block, half adders, a trigger, an AND element, an adder, and a register. ¹⁰ The disadvantage of this device is the low reliability of the output information.

The closest to the proposed technical essence is ustroy- ¹⁵ GUSTs comprising register interrupt mask register, the priority of the node encoder, a comparison circuit, odd code decoder, the output availability interrupt control output, and the interrupt code output node registers the analysis conditions including the group elements AND, AND NOT, and the element OR.

A disadvantage of the known device is the low reliability of the output 'information.

The purpose of the invention is to increase the reliability of the functioning of the device programs.

This goal is achieved in that a device for interrupting programs containing an interrupt register, a mask register, a comparison circuit, two groups of AND elements and an OR element, and the outputs of the mask and interrupt registers are connected respectively to the first and second inputs of the AND elements of the first group, the outputs of which are connected to the inputs of the OR element, the information inputs of the mask register are connected to the corresponding inputs of the group of information inputs of the device contains two triggers, the first and second elements And, the third, fourth, sixth and seventh th group of AND gates, OR element group, interrupt enable register;

the address register and the unit for generating a generalized interrupt signal, the first inputs of the first and second elements AND, the first inputs of the elements And the second third groups, the first group of inputs 5 of the comparison circuit and the first input of the unit for generating the generalized interrupt signal connected to the corresponding inputs of the group of information inputs of the device, the clock input of the first Trigger is the 10th and the first inputs of the elements of the fourth group are connected to the clock input of the device, the outputs of the elements of the fourth group are connected respectively to the second input of the unit to generate a generalized interrupt signal, the clock input of the mask register, the clock input of the register of allowed interrupts, to the second inputs of the first and second AND elements, to the second inputs of the 20 AND elements of the second and third groups and to the first 'inputs of the AND elements of the fifth and sixth ( groups, the outputs of the first and second elements AND are connected respectively to the input of the installation to zero and to the input of the installation 25 in the unit of the second trigger, the direct and inverse outputs of which are connected respectively to the third inputs of the elements of the third group and the first inputs the elements of AND elements of the seventh group, jg whose second inputs are connected to the inputs of the device interrupt signals, the outputs of the third and seventh groups of AND elements are connected respectively to the first and second inputs of the corresponding elements of the OR group, the outputs of which are connected to the unit inputs of the corresponding bits of the interrupt register, the outputs of the second group of elements AND are connected to the inputs of setting to zero the corresponding bits, the interrupt register, the outputs of the first group of elements AND are connected to the information inputs of the register allowed interrupts, the outputs of the register of allowed interrupts and the register of the mask are connected to the second inputs of the AND elements, respectively, of the fifth and sixth groups, the outputs of the fifth and sixth groups of elements AND are connected to the information outputs of the device, the output of the OR element is connected to the third input of the unit for generating a generalized interrupt signal, the output of which connected to the interrupt output of the device.

5s

In addition, the block generating the bypassed interrupt signal contains a trigger, an AND element, an NAND element, an element

OR, an inverter, a clock and a counter, the first and second inputs of the AND element connected respectively to the first and second inputs of the block, the inverter input and the first input of the AND gate NOT combined and connected to the third input of the block, the outputs of the inverter and the AND element connected respectively with the first and second inputs of the OR element, the output of which is connected to the installation input to the trigger unit, the trigger output is connected to the second input of the AND-NOT element, the output of which is connected to the installation input to the counter zero, the generator output is connected with a counter counter input, the first and second outputs of which are connected respectively to the output and to the zero input of the trigger.

The drawing shows a functional diagram of a device for interrupting programs. ^J

The device contains a group of inputs 1 of the device interrupt, a comparison circuit 2, address register 3, trigger 4, group of elements 5-11, group of elements OR 12, elements 13 and 14, trigger 15, register 16. masks, register 17 interrupt-, register, enabled interrupt 18, OR element 19, block 20 generating an invalid interrupt signal, which includes AND 21, inverter 22, OR 23, trigger 24, clock generator 2 5, AND-NOT 26 element, counter 2 7 , the output 28 of the interrupt device, a group of information inputs 29 of the device, the clock input 30 of the device, in ormatsionnye outputs 31 of the device.

The device operates in two modes programmatically set by a digital computer (digital computer): in the main mode and the control mode.

In the main standby mode of external requests for interruption of a digital computer using circuit 2, trigger 4, group of elements And 5 and register 3 connects the device to the communication channel and sets the mode to 'Uncontrolled'. For this, by the commands of the supervisor program (supervisor program) of the digital computer from the group of inputs 29 connected to the output information line of the digital computer, the device receives the mathematical address of the device, which is compared in comparison circuit 2 with the physical address of the device, hard-coded into register ^ 3 addresses and the fact of comparison from the output of the comparison circuit 2 is sent to the information input of trigger 4, where it is fixed by the control signal of the digital computer supplied to the clock input of trigger 4 as a signal for tracking the mathematical address. The output of trigger 5 4 is connected to the inputs of the group of AND 5 elements; in the case of address comparison, the high level of the logical unit from the output of trigger 4 allows the computer to receive ¹⁰ control signals from the input 30 from the input 30. After that, the supervisor The digital computer sets the trigger 15 to zero, and the mask code is sent to register 16 for the bitwise horse - ⁵ filtering of requests for interruptions based on their priorities. Software resetting of the trigger 14 is carried out through the element And 13, the signal from the output of which is fed to the input of the installation at zero _hours ^{20 of the} trigger 15.

The code in register 16 from the digital computer also enters through the group of inputs 29 and is fixed by the accompanying control digital computer, which receives 25. From the outputs of the group of elements And 5, to the clock input of the mask register 16. Trigger 15, set to zero, allows a high level from the inverse output to passing through the group of elements AND 8, the group of elements OR 12 at the inputs of the bitwise installation in the register unit 17 asynchronous interrupt request signals from external devices, other digital computers, etc. coming from the group of inputs 1. At the same time, the level of logical zero from direct out Yes, trigger 15 blocks the passage of signals through the group of elements And 9, the signals of bitwise zeroing of the register 17 are received through the group of elements And 7. Each external subscriber is assigned a priority level and a channel is assigned (discharge in the register of 17 interruptions). Interrupt request signals are fixed in the interrupt register 17 and bitwise logically multiplied by the register code 16 on the And 6 elements, where interrupts allowed by the mask are detected, which from the outputs of the And 6 elements go to the information inputs of the register 18, as well as to the inputs of the OR element 19. At the output of the OR element 19, a logical unit signal appears when the unit in at least one bit in the interrupt register 17 coincides with the unit in the corresponding bit in the mask register 16. This signal is fed to the third input of the generalized interrupt signal generating unit 20. In the absence of interruptions (initial state), the logic level zero signal from the output of the OR element 19 through the third input of the block 20, the inverter 22, the OR element 23 rigidly sets the trigger 24 to a single state at the input of the unit. At the same time, this signal from the output of the OR element 10 through the third input of the node 20 generates, together with the signal of the logical unit, from the output of the trigger 24, the output is the course of the AND-NOT 26 element, the signal of the level of the logical unit, which hardly resets the counter 27 to the zero output and blocks the count of pulses of the generator 2 5 received at the clock input of the counter 27. When the output of the first element OR 19, the signal level of the logical unit, indicating the presence of the mask allowed interrupts (interrupts), this signal through the third input of block 20, inverter 22, OR element 23 removes a high-level signal from the zero output of trigger 24. In this case, trigger 24 remains in a single state until a control signal of positive polarity arrives at its zero input. At the same time, the logic level signal from the output of the OR element 19 through the third input of block 20, 'together with the logic level signal from the output of the trigger 24, generates a logic zero level signal at the output of the AND-NOT 26 element, which unlocks the counter 2 7. The first pulse from the generator 2 5, arriving at the counting input of the counter 2 7, will generate not the first output of the counter 2 7 pulse, which is issued to the computer as a generalized interrupt signal. The next pulse from the generator 25 produces a pulse signal at the second output of the counter 27, which is fed to the input of the zero to the trigger 24 and resets it. The logic zero level from the output of the trigger 24 through the AND-NOT 26 element again resets the counter 27. Having received a generalized interrupt signal, the digital computer connects the device to the communication channel through block 1, after which the control signal from the output of the And 5 group of elements arrives at the clock input register 18, overwrites the code of allowed interrupts from the outputs of the group of elements And 6 to register 18. Then, the computer reads the information from the outputs of the register 18 of allowed interrupts and register 16 of the mask through the group of elements And 10 and 11 according to the group of outputs 31 of the device. After that, the computer supervisor program analyzes the priority of the contents of register 18 of allowed interrupts and determines the highest priority subscriber who requested it if there is more than one allowed Request in register 18. Then the program supervisor resets the discharge of register 17 of interruptions corresponding to the requested subscriber, and also resets everything . bits of register 16 of the mask are of lower priority, but opens the bits of the register of the mask of higher priority in relation to the requestor. In this case, the signal of the logic zero level from the output of the OR element 19, supplied to the third input of the block 20, sets the block 20 to its initial state, i.e., the counter 27 is reset and blocked through the AND-NOT 26 element, and the trigger 24 through the inverter 22. and the second element OR 23 is set to a single state. Then, the supervisor program command to increase reliability through the first and second inputs of block 20; associated Accordingly with the group of inputs 29, through the element And 21, the element OR 23 confirms the installation of the trigger 24 in a single state. The device is ready to receive a new request signal with a higher priority than the requestor. After that, the digital computer goes to the processing program of the subscriber who requested it. The register 18 serves for the intermediate storage of requests allowing the mask, so during the reading of the digital computer its state does not change. The introduction of the register eliminates the loss of repeated applications, since at the beginning of the program processing the request mask allowed, the code from the output of the group of elements And 6 is written into register 18, and the bit of register 17 allowed by the mask is programmatically extinguished and register 17 can receive new applications from this category.

In the Control mode, the digital computer sets the trigger 15 in a single state through the And 14 element. The output toggle of the 15 trigger goes to the inputs of the And 9 element group and allows the gate of the information from the digital computer coming from the input group 29. The signals from the outputs of the And 9 elements through the group OR elements 12 are supplied to the corresponding inputs of the installation in the unit of bits of the register 17, simulating the signals of external applications for. interruption.

In the Monitoring mode, the computer programmatically enters signals simulating external interrupts into the interrupt register 17, processes them using the mask register 16 according to the above algorithm 15 and thus monitors the serviceability of the interrupt request paths, and also monitors the functioning of the circuit of the generalized signal generating unit 20 A20 la interruption.

The use of the proposed invention improves the reliability of the operation of the device.

Claims (2)

The device relates to computing technology and can be used in digital computer interruption systems. A device for interrupting programs is known comprising an interrupt register, a mask register, a priority block, OR elements, an encoder, a priority prediction block, half adders, a trit ger, an AND element, an adder, and a register. The disadvantage of the device is low accuracy of the output information. The closest to the proposed technical entity is a device containing an interrupt register, mask register, priority node, encoder, comparison circuit, code oddity decoder, interrupt status output, control output, interrupt code output, and the register analysis node, including elements AND, and-NOT, and the element OR. A disadvantage of the known device is the low accuracy of the output information. The purpose of the invention is to increase the reliability of the operation of the device programs. The goal is achieved by the fact that a device for interrupting programs that contains an interrupt register, a mask register, a comparison circuit, two groups of AND elements and an OR element, with outputs of the mask and preregional registers connected to the first and second Inputs of the AND elements of the first group, the outputs of which the JK inputs of the OR element are connected, the information inputs of the mask register are connected to the corresponding inputs of the group of information inputs of the device contains two flip-flops, the first and second elements AND, the third, fourth, sixth and the seventh group of elements is AND, the group of elements OR, the register of enabled interrupts, the address register and block of the generalized interrupt signal, the first inputs of the first and second elements AND, the first inputs of elements AND of the second and third groups, the first group of inputs of the comparison circuit and the first input of the block the generation of the generalized interrupt signal is connected to the corresponding inputs of the group of information inputs of the device, the clock input of the first trigger and the first inputs of the elements AND of the fourth group are connected to the clock input of the jT device , the outputs of elements AND of the fourth group are connected respectively to the second INPUT of the bypass signal generation unit, TEI to the new input of the mask register, the clock input of the register of enabled interrupts, to the second inputs of the first and second elements And, to the Second inputs of the And elements of the second and third groups and to the first the inputs of the elements of the And the fifth and sixth groups, the outputs of the first and second elements of And are connected respectively to the input of the setup to zero and to the input of the installation in the unit of the second trigger, the direct and inverse outputs of which are connected to Responsibly with the third inputs of the elements of the third group and with the first inputs of the elements of the seventh group, the second inputs of which are connected to the inputs of the signals from the device's distortion, the outputs of the third and seventh groups of elements of AND are connected respectively to the first and second inputs of the corresponding elements of the OR group, whose codes connected to the installation inputs to the unit of the corresponding bits of the interrupt register, the outputs of the second group of elements AND are connected to the installation inputs to the zero of the corresponding bits of the interrupt register The codes of the first group of elements I are connected to the information inputs of the register of allowed interrupts, the outputs of the register of allowed interrupts and the mask register are connected to the second inputs of the elements AND of the fifth and sixth groups respectively, the outputs of the fifth and sixth groups of elements AND are connected to the information outputs of the device, the output of the element OR is connected to the third input of the generator generating a generalized interrupt signal, the output of which is connected to the output of the device interruption. In addition, the generation of the countercurrent interrupt signal contains a trigger, an AND element, an AND-NO element, an OR element, an inverter, a clock generator and a counter, with the first and second inputs of the AND element connected to the first and second inputs of the block, the inverter input and the first input of the NAND unit is combined and connected to the third input of the unit, the outputs of the inverter and the AND element are connected respectively to the first and second inputs of the OR element, the output of which is connected to the input of the unit in the trigger unit, the output of the trigger is connected to orym input of AND-NO element whose output is connected to the setting input of the counter to zero, the generator output is connected to the counting input of the counter, the first and second outputs of which are connected respectively to the output and to the input of setting to zero the trigger. The drawing shows the functional diagram of the device for prergo programs. The device contains a group of inputs 1 interrupt devices, circuit 2 comparison, register 3 addresses, trigger 4, groups of elements AND 5-11, group of elements OR 12, elements And 13 and 14, trigger 15, register 16, masks, register 17 prerta-, SRI, interrupt enable register 18, element OR 19, valuable signal generation interrupt signal unit 20, including AND 21, inverter 22, OR 23 element, trigger 24, 25 clock generator, AND-26 element, counter 27 , a device interrupt output 28, a group of device information inputs 29, a device clock input 30, and Information outputs 31 devices. The device operates in two modes, programmatically installed by a digital computer (DVM): in the main mode and the control mode. In the main standby mode, the external interrupt request of the digital computer using the circuit 2, trigger 4, group of elements 5 and register 3 connects the device to the communication channel and sets the mode N. to control. To do this, the commands of the supervisor program (controller program) of the digital computer from the input group 29 connected to the output information highway of the digital computer, the device receives the mathematical address of the device, which is compared in the comparison circuit 2 with the physical address of the device hard-coded The perwcrp 3 addresses and the fact are compared with the output of the comparison circuit 2 is fed to the information input of the trigger. 4, where the control signal of the digital computer is detected at the clock input of three 3 as the tracking signal of the mathematical address. The output of the trigger 4 is connected to the inputs of a group of elements AND 5, in the case of a comparison of addresses, a high level of the logical unit from the output of the trigger 4 permits the passage in the device through the group of elements of the AND 5 controls of the digital computers signals coming from code 30. After that, the program The supervisor DVR sets the trigger 15 to the zero state, and to register 16 the mask code is transmitted to alternate concurrent filtering of npePH requests according to their priorities. Software zeroing of the trigger 14 is performed through the element AND 13, the signal from the output of which enters the jcTaHOBKU input to the zero of the player 15. The code to the register 16 from the digital computer also enters through the groups at the inputs 2 9 and is fixed by the accompanying control of the digital computer, the post. pushes from the outputs of the group of elements AND 5 to the clock input of the register of the mask 16. The trigger 15, set to zero, a high level from the inverse output permits the passage through the group of elements AND 8, the group of elements OR 12 to the inputs of a bit set to unit 17 of the asynchronous signals - interrupt requests from external devices of other digital computers, etc., coming from a group of inputs 1. At the same time, the logic zero level from the direct output of the trigger 15 blocks the passage of signals through a group of elements 9, zero-zero signals 17 and fed through a group of AND gates 7. Each external subscriber is assigned a priority level and a retracted channel (discharge in the register 17, the interrupt). Interrogation request signals are fixed in interrupt register 17 and bitwise logically multiplied by register code 16 on AND 6 elements, where you are allowed by an interrupt mask, which from the outputs of the AND 6 elements arrive at the information inputs of the register 18, as well as at the inputs of the element OR 19. At the output of the element OR 19, a signal of a logical unit appears, when at least in one bit the unit in the register of interferences 17 coincided with the unit of the corresponding bit of register 16 of the mask. This signal is fed to the third input of the unit 20 for generating a generalized interruption signal. In the absence of interruptions (initial state), the signal of the logic level zero from the output of the element OR 19 through the third input of the block 2O, the inverter 22, the element OR 23 rigidly sets the trigger 24 to the unit state on the INPUT of the unit. At the same time, this signal from the output of the element OR 1O through the third input of the node 2O produces, together with the signal of the logical unit from the output of the trigger 24, on the output of the N-26 element, the signal of the level of the logical unit, which is hard on the output of the zero setting of the counter 27 and it blocks the pulse of the gene & 25 rator arriving at the clock input of the counter 27. When the output at the output of the first element OR 19 of the signal is a level of a logical unit, indicating the presence of an interrupt (interrupts) enabled by the mask, this signal through the third input Lok 2 O, an inverter 22, an OR gate 23 takes the high level skgnal output setting to zero the trigger 24. This trigger 24 remains in edish1chnom state before the arrival of a control signal of positive polarity at its set input to zero. At the same time, the logic unit level signal from the output of the OR 19 element through the third input of block 20, together with the logic unit level signal from the trigger output 24, produces at the output of the NAND 26 element a logic zero level, which is processed by the counter 27. First impulse from the generator 25 arriving at the counting input of the counter 27, will not pulse the first output of the counter 27, which is output to the digital computer as a generalized pre-ganoi signal. The next pulse from generator 25 produces a pulse signal at the second output of counter 27, which is fed to the input of the setup to zero of the triger 24 and zeroed it. The logic zero level from the trigger output 24 through the IS-NOT element 26 re-embeds the counter 27. After receiving the generalized signal interrupts, the digital computer connects the device to the communication channel via block 1, then the control signal from the output of the group of elements And 5, arriving at thus, the input input of register 18 rewrites the interrupt code into the register 18 from the inputs of the AND 6 pears of the elements. Then the digital computer reads the information from the outputs of the 18 enabled interrupts and mask register 16 through the groups of device outputs 31 and the device outputs 31. After this, the supervisor DVM analyzes the priority of the contents of the register 18 allowed interrupts and determines which subscriber has the highest priority subscriber in case there are more than one allowed request in register 18. Then the supervisor program nulls the interrupt register register 17 corresponding to the requesting subscriber, and also zeros everything, register bits 16 of a mask of lower priorities, but opens bits of the register of a mask of higher priority with respect to the requester. In this case, the logic level zero signal from the output of the OR element 19, which arrives at the third input of the 2 O block, sets the block 20 to the initial state, i.e. the counter 27 through the AND-NE element 26 is zeroed and blocked, and the trigger 24 through the inverter 22. and the second element OR 23 is set to one. Then a supervisor program command to increase reliability through the first and second inputs of block 2; CAB) 1E Corresponding with the group of inputs 29, through the element AND 21, the element OR 23 confirms the setting of the trigger 24 in the unit state. The device is ready to receive a new request signal of a higher priority level relative to the requester. After that, the digital computer goes to the processing program of the subscriber who requested it. Register 18 is used for intermediate memorization of the query request mask, so its state does not change during the reading of the CVM. The introduction of the register excludes the loss of repeated orders, since at the beginning of the processing program allowed by the mask request, the code from the output of the group of elements And 6 is rewritten in register 18, and the mask-enabled register register 17 is programmatically quenched and register 17 can take on this bit new applications In the Control mode, the digital computer sets the trigger 15 in a single state through the element And 14. At the same time, the logical zero level from the inverse output of the trigger 15 prohibits the passage into the device through the element group AND 8 external interrupt signals coming in from the input 1 group. units from the direct output of trigger 15 are fed to the inputs of a group of elements AND 9 and allow gating information from a digital computer coming from a group of inputs 29. Signals from the outputs of elements AND 9 through a group of elements OR 12 arrive at respectively favoring inputs of bits in the register unit 17, for simulating signals Outer wok on .preryvanie. In the Control mode, the digital computer programmatically enters signals that simulate external interruptions into the error register 17, processes them using the mask register 16 according to the algorithm described, and thus monitors the health of the interruption request paths, and also monitors the operation of the circuit for generating a generalized signal. al interrupts The application of the present invention allows to increase the reliability of the operation of the device. Claim 1. Device for interrupting programs, containing interrupt register, mask register, comparison circuit, two groups of AND elements and OR element, with outputs of mask and interrupt registers connected to the first and second inputs of AND elements of the first group, whose outputs are connected to inputs element OR, the information inputs of the mask register are connected to the corresponding inputs of the group of information inputs of the device, characterized in that, in order to ensure the reliability of operation, it contains two gera, first and second elements AND, third, fourth, fifth, sixth and seventh groups of elements AND, group of elements OR, register of allowed interrupts, address register and generating unit of generalized interrupt signal, with first inputs of the first and second elements AND, first inputs Elements of the second and third groups, the first group of inputs of the comparison circuit and the first input of the output of the signal of the interrupt signal are connected to the corresponding inputs of the group of information inputs of the device, the clock input of the first trigger and the first inputs of And the fourth group is connected to the clock input of the device, the outputs of the l and fourth group elements are connected respectively to the second input of the generation of the interrupt signal, the clock INPUT of the mask register, the clock input of the register of allowed interrupts, to the second inputs of the first and second elements, to. the second inputs of the elements of the second and third groups and to the first inputs of the elements of both the fifth and the second groups, the output of the first and second elements AND are connected respectively to the installation input to zero and to the installation input and into the unit of the second trigger, the direct and inverse outputs of which are connected in accordance with the third inputs of the AND elements of the third group and with the first inputs of the AND elements of the seventh group, the second inputs of which are connected to the inputs of the device interrupt signals, the outputs of the AND elements of the third and seventh groups are connected respectively, with the first and second inputs of the corresponding OR elements of the group, the outputs of which are connected to the installation inputs of the corresponding bits of the interrupt register, the outputs of the AND elements of the second group are connected us to zero setting inputs sootvetsgvuyushih bits of the interrupt register, and outputs elements of the first group are connected to the data inputs of the interrupt enable register, outputs interrupt enable register and mask register are connected to second inputs of AND gates respectively the fifth and sixth groups, the outputs | The elements of the fifth and sixth groups are connected to the information outputs of the device, the output of the element OR is connected to the third input of the generation of the generalized interrupt signal, the output of which is connected to the interrupt output of the device. 2. Device pb p. 1, that is, so that the block for generating a generalized interrupt signal contains a trigger, an AND element, an AND-NOT element, an OR element, an inverter, a clock generator, and a counter, and the first and second inputs of the AND element are connected respectively to the first and second inputs of the block, the input of the inverter and the first input of the element AND –NAY are combined and connected to the third INPUT of the block, the outputs of the inverter and the AND element are connected respectively to the first and second inputs of the OR element whose output is connected to unit setup input trigger, a trigger output connected to a second input of AND-NO element whose output is connected to the input for setting the counter to zero, the generator output is connected to the counting input of the counter, the first and second outputs of which are connected respectively to the output unit and to an input of setting to zero the trigger. Sources of information taken into account during the examination 1. USSR author's certificate No. 7361О1, cl G 06 F 9/46, 198О. 2. USSR author's certificate number 744575, cl. G 06 F 9/46, 198O (prototype).