SU783782A2 - Device for exchange of information of control computer with control objects - Google Patents

Description

(54) DEVICE EXCHANGE INFORMATION

Claims (2)

CONTROL VERSE A NUMBER OF ASHIN WITH CONTROL OBJECTS The invention relates to the field of computing technology, and can be used in computer control systems of objects and is an improvement of the known device according to the authors. St. No. 547761. In the main invention auth.St. 5,47761 describes a device for exchanging information of a control computer (PC) with control objects comprising input and output information switches, an addressing unit, a command coder, a control panel, word counters and addresses, pause and interrupt priority blocks, input and output buffer blocks, command switch and serial to parallel converters and parallel to serial converters. In this case, the group of outputs and the first group of inputs of the input information switch is connected respectively to the first group of outputs and the first group of device inputs, the group of inputs and the first group of outputs of the output information switch are respectively to the second group of inputs and the second group of device outputs. The second and third groups of inputs of the input information switchboard, the second and third groups of outputs of the output information switchboard are associated respectively with the outputs of the serial to parallel converter, the input block of the buffer memory, with the inputs of the parallel converter to the serial and output buffer blocks. Control panel output groups are connected to the group of control inputs of the input and output information switches, group of outputs, first, second and third groups of command switch inputs, respectively with the third group of device outputs, with the third group of device inputs, with outputs of the address counter and command encoder. The output group of the pause priority block is connected to the first group of inputs of the word counter, address counter, and instruction coder, the second group of inputs of which is connected to the first output of the interrupt priority block. The control input of the pause priority block is connected to the output of the word counter, the second group of inputs of which, the second group of inputs of the address counter and the group of inputs of the addressing block are connected to the first group of outputs of the output information switchboard. The group of inputs of the input block of the buffer circuit, the group of inputs of the pause priority block and the first group of inputs of the preemption priority block are associated with the fourth, fifth and sixth groups of device inputs, respectively. The input of the serial to parallel converter and the parallel converter to serial converter output are connected respectively to the input and output of the device, the output group of the addressing unit and the output buffer block are connected respectively to the fourth and fifth groups of the device outputs. The disadvantage of such a device is its low reliability when exchanging an array of information. This is due to the fact that the distortion of the code of an unprogrammed command (NR) can lead to access to the memory cells of the UVM at an erroneous address. As a result, either the subscriber or the UVM receives a corrupted array of information, and this can cause a malfunction of the entire system. The purpose of the invention is to demonstrate the authenticity of the exchange of an array of information. The goal is achieved by the fact that the device according to the author. St. No. 54776, a control bit formation block of non-programmable commands was inserted, containing a trigger, an AND element, and an OR element, and the trigger output is connected to the additional switch input, and the count input is connected to the first and second inputs, respectively. element to the output of the element. OR and the control output of the address counter, the outputs of which are connected to the second group of inputs of the priority priority block, the odd outputs of which are connected to the corresponding inputs of the OR element, and the control input to the control output of the block of priority pauses. Nafig 1 is a block diagram of the device; in fig. 2 shows the structure of a non-programmable command; in FIG. 3, the structure of a control word. When exchanging an array of information, the appearance of a signal on an odd (in order) output of a block of priority of a break means that the parity of the address code of the next word of the array is opposite to the parity of the address code of the previous word. This signal through the OR element and the input element to the trigger input and changes its state to the opposite. This allows the output signal of this trigger to be used as the control bit of the code of the next unprogrammed command (NC). The NC code is entered into the FBM and monitored modulo two. In the case of a subscriber addressing at an erroneous address, the ACU issues an error signal and the information of the bar is repeated or completely eliminated. The device (Fig. 1) contains the input switch 1, the output switch 2 information, block 3 addressing, ifator 4 commands, control panel 5, word counter 6, address counter 7, pause priority block 8, interrupt priority block 9, input block 10 buffer memory, output block 11 of buffer memory, switch 12 commands, serial-to-parallel converter 13, parallel-to-serial converter 14, OR 15 element, AND 16 element, trigger 17, inputs 18-24 and outputs 25-30 devices. The device works as follows. The exchange of information between UVM and control objects is carried out in a programmed and non-programmed manner. The programmed exchange of information is carried out in accordance with work programs that provide input or output of information from the ACU. The selection of the subscriber participating in the exchange is provided by block 3 by decoding the code of the subscriber's address arriving at its input from the PSU via the output switch. 2.; The numerical information outputted by the UBM is either received through the converter 14, or through the block 11, or directly through the output 29 of the device to the selected subscriber. With programmed input, information in the ACU is received from the selected sensor subscriber either through the converter 13, or through the block 10, or directly through the input 20 of the device. And the input switch 1. The signals of correct operation of all the units of the exchange device, which enter the control panel 5, allow operator to visually monitor the performance of the device exchange. If the exchange initiator is one of the subscribers, then the information in this case is transmitted in an unprogrammed way. At the request of the subscriber, an unprogrammed command (input or output) is formed in the exchange device, which, entering the PCB, pauses the current work program for the duration of the exchange. An unprogrammed command (Fig. 2) consists of two half words - {half word 1 and half word 2), each of which is accompanied by its own test bit. The organization of the exchange of single words is as follows. Subscriber requests for information exchange arrive at the inputs of block 8 of the priority of suspensions, which generates at the output a signal corresponding to the request with the highest priority level from among 21 requests received at the input. The rest of the requests are stored in block 8 and are sent to the FMS for execution 6 times in order of their priority. The encoder 4 generates an NK code consisting of the operation code (the half word 1 with its own control bit) and the cell address code with which the exchange will be made (the half word 2 with its own control bit). The NC code through the switch 12 enters the CCM, where the control of the received code is exercised, by means of a parity check, the check bits with the corresponding half words codes. If the NC code is received in the UVM without errors, the current program is suspended for the duration of the exchange. At the same time, unit 8 generates a polling address signal (not shown in the drawing) connecting the exchange initiator to the device. An unprogrammed exchange with the address part of the NK code received from the subscriber via input 24 is also possible. When exchanging an array of information between the UVM and system subscribers, an control word is output from the UVM, defining the starting address and word numbers of the array. Through switch 2, the control word is received in counters 6 and 7. Moreover, a part of the control word defining the starting address of the array (half word 1) is recorded in counter 7, and a part of the word defining the number of words in the array (half word 2) is recorded in counter 6. The control bit of the half word 1 is written to trigger 17 ( the writing circuit is not shown in the drawing). After the request to exchange the next word of the array at the input 21 of the device, the encoder 4 generates an operation code NK (half word 1) with its control digit. The address part of the NC (half-word 2) is determined by the counter code 7 of the address, the check bit that corresponds to the state of the trigger 17. The NC code generated in this way enters the ACU through the switch 12 and is controlled modulo two. If the code NK is received in the ACU with an error, a signal is sent to the console 5 and the exchange is repeated or stopped altogether. If the check bits correspond to their codes, then the BCC exchanges the next word of the array with the subscriber. The increase in the code of the counter 7 address and the decrease in the code of the counter 6 is carried out by signals on the scrap from the output of block 8. The principle of forming the check bit of the address part of the NK code is as follows. Requests to suspend the current program, arriving at the inputs of block 8, have a higher priority than requests to interrupt it, arriving at the inputs of block 9. This means that interrupt requests are remembered by block 9, but the generation of the NC code for the interrupt is blocked in the encoder 4 time of exchange of an array (or a single word) of information. Consequently, during the exchange of an array of information, it is not necessary to prioritize interrupt requests and the equipment of block 9 can be used for purposes other than its intended purpose — to generate a check bit of the address part of the suspend code of the suspension code. For this purpose, interrupt requests are stored. The block in block 9 is masked for the time of exchanging the array with the signal from the control output of the preemption priority block. In this case, the address inputs of block 9 receive the address part of the NK code, and zero in this code is interpreted by block 9 as an interrupt request (but the interrupt is not processed, since in the encoder 4, the generation of the NK interrupt code is blocked). For the sake of definiteness, we assume that in block 9, the discipline of servicing requests from right to left, i.e. the first from right to left, zero from among the incoming ones is considered to be the highest one and the request to which it responds is to be processed. When exchanging an array of information, the appearance of a signal at an odd (in order) output of block 9 means that the evenness of the address code of the next word in the array is opposite to the evenness of the address code of the previous word; the appearance of a signal at the even output of block 9 means the parity of the address codes of the subsequent and previous words of the array. Indeed, since the addresses of the adjacent words of the array differ by, then the zero of the odd-numbered code of the address of the previous word of the array means that in the code of the address of the next word, i will be in this place (it will replace an even number of ones preceding the digit in the previous code) i.e. the parity of the address code of the next word is opposite to the parity of the address code of the previous word. On the contrary, if the zero is in even digit, then the parity of the address codes of the subsequent and previous words of the array correspond to each other. Determining whether the order of the word address code is in order from first to right zero, in order — even or uneven — generates a priority priority block 9. The signals from all the odd outputs of lock 9 to the inputs of the element LI 15, the appearance at the output of which signal means a change in the parity of the code / address of the next word of the array. If the signal appears at one of the even outputs of block 9, then the output of the element OR 15 there is no signal, which means no parity change after the new code is established in the counter 7, the permit signal is output from the control output of the element AND 16 and the output of the element OR 15 is connected to the counting input of the trigger 17. The state of this trigger (it is stored the control bit of the address part of the previous word) changes if there is a signal at the output of the OR 15 element (i.e., the parity of the address codes of neighboring words is different and does not change if the output of the 1 "input OR 15 signal is absent (i.e. codes of addresses of neighboring words are the same.) Therefore, by the time the request for exchanging the next word of the array arrives, trigger 17 contains the control bit of the address part of the input or output of this word. After this check digit is formed by the address code of the previous word (this address is not distorted), then all parity errors that occur during the Formation of the address part of the new NC, as well as errors that occur during the transmission of this NC to UVM, will be detected during the control of this NC modulo two at the entrance to the SWM. This makes it impossible to access the cells of the UVM memory at a false address, as a result of which either the subscriber or the UVM may receive a false array of information. For example, let the next word of the array be selected from the UVM memory cell with the number 1011011. The control bit of the address part of the NC is equal to 1 and stored in trigger 17, the first right-to-left zero bit of this code has an odd (third) number. When a block of 9 kbda 1011011 arrives at the input, an odd bus is excited at its output, the signal from which is a post. It goes to the counting input of the trigger 17 and changes its state to the opposite (after the next NC is received in the ACU). For the address part of the next NC 1011100, the check bit will be formed and recorded in the trigger 17. Therefore, if the parity of the address part equals The NC, command switch or communication channel between the digital computer and the interchange device, the test bit of the day corresponds to the code and an error is fixed when entering the NC to the computer, which makes it possible to prevent the exchange of information to false addresses. Upon completion of the exchange of the information array from the control output of the word counter 6, a signal is output to block 8, at which the bit corresponding to the request is reset. From block 8, a signal is sent to block 9, by which interrupt requests stored in it are de-mixed. If in block 8 there are no requests for input or output of information, then, upon an interrupt request, the interrupt NC code is generated with the highest priority, which interrupts the current program and transfers the ACU to the processing of the corresponding program. In this case, the address counter 7 is reset and does not affect the processing by block 9 of incoming interrupt requests. For NK, interrupts, check bits of both half words are formed by the encoder. The NC code of the interrupt is monitored when the CCM is entered in the same way as the NC. Thus, the device allows detecting odd errors in non-programmable commands and thereby increasing the reliability of data exchange between the PSU and subscribers. Formula of the Invention A device for exchanging information of a control computer with control objects according to the author. No. 547761, characterized in that, in order to increase the reliability of the exchange, a block of forming a control bit of non-programmable commands is inserted into it, containing a trigger, an AND element and an OR element, the trigger output being connected to the auxiliary input of the command switch, and the counting input to the output AND element, by the gap and second inputs of the OR element connected to the output and to the control output of the address counter, the outputs of which are connected to the second group of inputs of the interrupt priority block, the odd outputs of which are connected to the corresponding inputs of the OR element, and the control input - to the control output of the pause priority block. Sources of information taken into account in the examination 1, USSR Author's Certificate No. 547761, cl. G 06 F 3/04, 1975 (prototype),