SU448435A1 - Multi-coordinate numerical control system - Google Patents

Description

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The invention relates to the field of automatic control and is intended for use in numerical control systems of multi-axis metalworking machine tools.

Multi-coordinate numerical control systems are known, containing: a serially connected reading node, an input register and an input information switch, one output of which is connected to the arithmetic logic node via the address encoder of the zero-memory device (RAM) and the second output through the address memory address tuner - also with an arithmetic logic node, the third output via function decryptor - with the block number and tool number indicators, and h the fourth one is with the decoder of the algorithm codes, the operator console connected to the input register, the corresponding output of which through the input information control node is connected to the readout node, the output switchboard whose input is connected to the arithmetic logic node that is connected to the input information switchboard, and site control execution technological commands.

However, these systems have a narrow scope and low reliability.

The proposed system differs in that it contains a priority node, a control output node, and a control, correction, and reservation node, the priority node being connected to the reading node, the input information switch, the firmware control node, the semi-permanent memory node, commands, an arithmetic logic unit, a decoder of the algorithm codes and a control output node, the corresponding inputs of which are connected to the console The module and the firmware control node, and the output to the output switch, the control, correction and reservation node is connected to the arithmetic logic unit.

In this way, the application area is extended and the reliability of the system is improved.

In addition, the priority node contains a queuing switch, the inputs of which are associated with the algorithm code decoder and the firmware control node, and the outputs with two registers for the wok and the step algorithm register, the outputs of the registers for the wok are connected to the step register the polling switch and clock circuit, and the outputs are connected to the control inputs

the address encoder, the outputs of the clocking circuit are connected to the address coder and the register counter associated with the inputs of the first comparison circuit, the output of which is connected to the clocking circuit connected to the registers behind the switch, the polling switch, the group operator address register, the time register, the reading node, a switch of input information, a firmware control node, a control node for execution of technological commands, and a second comparison circuit, to the inputs of which are connected the outputs of the control output module and a time register associated with the outputs of the semi-storage device node, which are also connected to the address register of the group operator connected to the microprogram control node, and the counter register connected to the arithmetic unit.

The control output node contains step counters on coordinate axes, the outputs of which are connected to the control buses of the first decoder, a matrix of speed coefficients, the inputs of which are connected to the outputs of the decoder, a speed register, the outputs of which are connected to the counter of the period of control actions connected connected to the output with a collecting circuit, the first speed number counter is connected via a matching circuit with a second speed number counter, with the outputs of both counters connected to the comparison circuit, the second decrypt p inputs of which are coupled to the outputs of second counter rate number, and the outputs - the matrix velocity and path binary counter varying numbers speed which outputs through collective circuit coupled to the input of the coincidence circuit, the output of which is connected to the first counter rate room entrances.

The control, correction and reservation node contains a base expansion circuit made in the form of cascade connected groups of modified addition matrices whose inputs are connected to an arithmetic logic node, and outputs to the first inputs of the subtraction matrices, the second inputs of the subtraction matrices are connected to the arithmetic logic node, and their outputs are with a comparison circuit, the output of which is connected to a modular circuit switch and arithmetic logic through a series-connected address register of corrections, a passive table and a parallel register. by knot.

FIG. 1-4 shows the block diagrams of the described system and its functional units.

The block diagram contains the reading node 1, the input register 2, the input information switch 3, the input information control node 4, the operator console 5, the semi-permanent memory address encoder 6, the operational memory address encoder 7, the control actions issuing node 8, arithmetic logic node 9, function decoder 10, algorithm decoder 11, firmware control node 12, frame number indicator 13, tool number indicator 14, displacement indicator 15, output switch 16, drive connection node 17, semi-permanent memory node 18 device, technological control command execution node 19, control, correction and reservation node 20, priority node 21, priority switch 22 (FIG. 2), application registers 23, step 24 algorithms, clock circuit 25, polling switch 26, encoder 27 addresses, comparison circuit 28, register counter 29, group operator address register 30, comparison circuit 31, time register 32, counters 33, 34 and 35 (Fig. 3), decoder 36, velocity factor matrix 37, speed register 38, counter 39 of the period of control actions, the collective scheme 4 0, the first speed number counter 41, a coincidence circuit 42, a second speed number counter 43, a decoder 45 comparison circuit 44, a speed and path matrix 46, a speed number change counter 47, a collecting circuit 48, a coincidence circuit 49, a base extension circuit 50 (FIG . 4), groups of matrixes 51, matrices 52, subtraction, comparison circuit 53, register 54 of the correction address, passive table 55, parallel register 56 and switch 57 of modular channels.

The system works as follows.

The input information about the movements and commands comes from the reading unit 1 to the input register 2. In the same way, from the control panel 5 information is received about the operating modes, feed rates, the values of the length and radius corrections. From the input register, the input information switch 3 distributes information to the nodes: the algorithm information is sent to the decoder of the algorithm codes; information about the frame number, tool number and spindle speed - to the function decoder, numerical information about the movements - to the converter in the residual classes system (JUICE) of the arithmetic unit 9; commands to move the x-in encoder addresses of the operational storage device; information about the operators into the encoder of the address of the semi-permanent storage device and into the node 4 of the control. From the algorithm codebook decider, information about the algorithms in the frame in the form of code signs arrives at the priority node 21. From the decoder for auxiliary and other functions, information is fed to the block number, tool number, and machine actuator indicators.

Information about the end of the input frame and the line comes from the input information switch to the priority node, allowing it to clock the reading node. The indication of the movements is carried out by the indicator 15, to which data is received after the conversion in the arithmetic logic node. 5 The set and sequence of group operators and codes defining the time of their execution are stored in node 18. It also stores the number of group operators for each algorithm, the cell number of a semi-permanent memory device, in which the composition of this algorithm and the operational cell number are recorded memory device assigned to the given algorithm oj -10 Information about the algorithms executed in each frame of the program goes to the encoder 6, stating the address of the semi-permanent memory device according to which the contents of the algorithm are stored.15 A part of this content is the address of the random access memory corresponding to the given address of the semi-permanent storage device, as well as a number defining the number of group operators 20 in the algorithm are rewritten to the specified address in the random-access node of the logical node. In the control node, the input of the word length and parity of 25 punches in the punched tape line is controlled. If there is a flash, the read node stops by a signal from the control node. Since the processing of the operand information is performed in the JUICE. Then, by inserting an arithmetic logic node into an on-line memory, the information is converted from a binary-decimal code to an SOC in an arithmetic logic node. The address of the random access memory cell is formed by the encoder 7.35. The processing of the operand information about the movements is performed by parallel operations on the modular parts from the integer operands using an arithmetic-logical node. In accordance with the priority group selected by the group operator, the priority node controls the node 12, which switches the structure of the modular arithmetic logic node and forms the calculation process. The results of processing one-45 random information are sent to output switch 16, which is polled during periods of issuing control actions. control output unit. The switch 16 controls the communication unit 17 with the machine drives. Processing and issuing information in the system depends on the execution of individual technological commands. The control over their execution55 is carried out by the control node of the execution of the technological commands associated with the entrance to the machine, and the output with the priority node. Since the system functions in real time, to ensure maximum load of all the functional units of the system, a division of computer time is provided. The time separation mode is organized by node 21 by the priority implementation of algorithms.65 6 Unlike conventional duplex or triple redundancy methods, 30% redundancy is introduced in the system by using its modular organization when operating in the nonpositional number system of residual classes. For this purpose, a node is used to monitor the correction and reservation of modular channels, which detects a defective modular channel and controls the replacement of it with a backup channel. the priority node works as follows. When entering information of the next frame, the signs of the algorithms from the decoder algorithm (Fig. 1) are sent to the order switch (Fig. 2), which sends this information to the input of the register for the algorithms that contains the signs of the main algorithms, in the next frame. A switching control signal arrives at the second input of the queuing switch. This, g switch controls rewriting, the prize, 0 algorithms from registers of algorithms to the register of Perezar algorithms, is executed after the end of each. The priority of algorithms is determined by a bit polling of register 24, the priority of bits in which indicates priority allocation of algorithms expressed by binary signs. A random survey is conducted in each beginning with the most significant bits of register 24, i.e., with the most important priority algorithms. The survey is performed by the switch 26 with the limiting frequency of the circuit elements dd of the moment of detection of the first single feature of the algorithm. At the moment of detection of a feature of the algorithm, a request is sent to the interrogation switch, terminating the interrogation, stopping the switch on the number of this register register 24 so that the subsequent interrogation in this step will be performed from the discharge where the interruption occurred. Simultaneously with the shutdown of the switch 26, the input of the encoder of the addresses of the algorithms in the random access memory receives the detected signal of a call, causing the code of the address of the operational memory at the output of the encoder. This code is fed to a comparison circuit 28, to the second inputs of which pgg is supplied the address of the previous algorithm, stored in the register-counter 29, in which, in addition to the address of the algorithm, the number of group operators executed is recorded. The results of the comparison are fed to the input of the clock circuit 25. In the event of a coincidence of the codes, the previous algorithm is executed, and in the register of the number of group operators the node 18 receives the address code of the next group operator of the same algorithm. After that, the contents of the semi-persistent storage device at this address are rewritten into registers 30 and 32.

In the event of a mismatch of codes from the clocking scheme, signals are sent to the register counter and the encoder 27, according to which the contents of the register counter are copied to the random access memory of the arithmetic node at the address contained in this register. Next, the register counter is cleared, and the data of the next, new algorithm is written to it from the random access memory at the address received from the encoder 27. This data from the register-counter is recorded in a semi-permanent memory device as an address, from which the number of the next group operator and the time of its execution are received from registers 30 and 32. In the register counter, after each group statement is executed, one is subtracted from the number of statements. This allows you to determine the sequence of execution of group operators and a call from their semi-permanent memory device of their features (number and execution time) to registers 30 and 32. A number determining the execution time of a group operator in ticks is transferred from register 32 to comparison circuit 31, the second input of which from node 8 receives the value of the time remaining until the end of the interpolation step.

If the execution time of the group operator is less than the remaining until the end of the step, a signal is sent to the circuit 25 permitting the execution of this group operator. According to this signal, the circuit 25 generates a signal arriving at the input of register 30 and allowing reading the number of the group operator to node 12. If the implementation time of the group operator is longer than the end of the step, a signal prohibits the execution of this algorithm.

Circuit 25 generates a signal acting on registers 29, 32 and 30, which sets them to the initial state. At the same time, the signal acting on the switch 26 appears to continue polling the register 24, which determines the following algorithm. The content of the selected algorithm is called up from the random access memory of the arithmetic logic unit to the register 29, and then from the semi-permanent memory to the register 30 the number of the next group operator, and to the register 32 - the time of its execution.

When executing technological commands, the priority node starts functioning after they are completed. Signals about the execution of technological commands come from the machine to the control node of the executed commands, and from there, at the request of the priority node, to the circuit 25.

After the next group operator's firmware has been executed from the firmware control node, the termination signal is sent to the clocking circuit

group operator, through which the circuit 25 receives a signal to reduce by one the number of group operators in the register-counter 29.

5 If, after decreasing by one, the number of group operators is not zero, i.e., the algorithm has not yet been executed, the circuit 25 sends the installation signal of switch 26 to its original state and requests are queried and priority is determined for the next group operator. If, after decreasing by one, the number of group operators becomes equal to zero, which determines the end of this algorithm, the signal 15 from the circuit 25 is removed to execute this algorithm.

When all the frame wobbles are executed, one of the registers 23 receives a signal to the circuit 25, according to which the start signal 0 of the reading node is generated. Information on the passage of each line of punched tape and the end of frame reading is fed from the input switch to the priority node circuit 25.

5 The node for issuing control actions operates as follows.

The speed number that is specified in this processing frame comes from the random access memory of the arithmetic logic node to the binary-decimal counter 41. Since the feed rates are set on the punched tape by their numbers, the speed change from the console is made by changing the speed number. The integer value of the change of the 5th measure of the speed is entered from the operator's console into the three-digit subtractive binary counter 47 of the change of the speed number. The clock pulses coming from the circuit 49, resetting the IQT counter 47 to zero and simultaneously arriving at the input of the counter 41, changing its contents. At the moment that the contents of the counter 47 are equal to zero, the passage of the clock pulses by the signal coming from the circuit 48 is prohibited. In the counter 41, a modified speed number is stored. This process of changing the speed number occurs in each new frame.

The speed number code from counter 41 goes through a coincidence circuit 42 (the second inputs of which are controlled by node 12) to a second speed number counter 43. The binary counters 33, 34, and 35 steps associated with the output switch 16 count the number of steps along the coordinate axes. When one or several counters of chaps are overrun, decoder 36 allows reading from matrix 37 of the value of the corresponding velocity factor, the code of which from the output enters the arithmetic logic unit 9. Simultaneously with reading the coefficients from matrix 37, it is possible to access speed matrix 46 and the signal path from node 12 firmware control. The value of the given speed, recorded in matrix 46 in the system of residual classes, is multiplied in the arithmetic logic node by a factor chosen from matrix 47 and entered (after conversion into a code with mixed bases) into speed register 38. From the counter, the 39 clock pulses begin to subtract the units until the content is equal to zero. At the moment that the contents of the counter 39 are equal to zero, permission is issued to issue a control from the output switch 16 to the communication node with the machine drive. Thereafter, the contents of the speed register are rewritten to counter 39, and the process is repeated. The contour speed control during acceleration and deceleration is dried as follows. On the basis of acceleration, the content of the second counter 43 of the speed number is increased by one. The magnitude of the new speed and the magnitude of the time spent working out the path at this speed are transferred from the matrix 46 to the arithmetic logic node, where, as a result of multiplication, they form the magnitude of the step of the path that the numerical control system must work with the new speed. In each interpolation cycle, this value of the path is compared with the value of the maximum coordinate coordinate. At the moment of equality of the magnitude of the path and mixing, the maximum coordinate is given permission to go to the next speed number, for which the contents of counter 43 are increased again by one, etc. The process is repeated until the comparison circuit 44 gives the equal signal the current speed, the number of which is stored in the counter 43, and the final acceleration speed, the number of which is stored in the counter 41. This signal prohibits a further increase in the speed number and the step number of the path. From this moment on, the system produces control actions with a period corresponding to the final acceleration rate specified on a punched tape. The deceleration in the system is carried out similarly to overclocking. By the sign of slowdown recorded on a punched tape, the reduction of the content of the second speed number counter by one is permitted. The magnitude of the new velocity from the velocity matrix is entered into register 38, and the magnitude of the step of the path from the velocity matrix and the path is transferred to the arithmetic logic node, where it is subtracted from the slowdown path of the arithmetic logic node stored in the random access memory. In each interpolation cycle, this value of the path is compared and moving along the maximum coordinate, and if they are equal, the resolution to go to the next step of the path is formed and the contents of counter 43 are again reduced, etc. The process ends when the speed number in the counter 43 becomes equal to the speed number in the counter 41. The operation of the control, correction and reservation node is as follows. When the node implements the priority of the numerical program control of the control operator, any elementary arithmetic logic operation in the system of residual classes (SOC), performed using tabular schemes of addition, subtraction, multiplication, transformation, and comparison circuit, is carried out simultaneously on the main and redundant modules THE JUICE. According to the residuals for mobility, by expanding the bases of the JUICE, two auxiliary residues for {gpc} are determined using the circuit 50, from which the residual moduli of the excess modules N + 1 - N + e generated in the redundant part of the arithmetic logic register are subtracted from the address formation circuit. node. The corresponding differences between the auxiliary and excess residuals | A | jv + t- | A | l + e (assuming THAT both differences are by definition in comparison circuit 53 are not equal to zero) are used as the address of the passive correction table 55. If only one of the control differences is zero, the auxiliary residues for (m, v) are replaced by excess ones. The current value of the resultant operand is considered reliable and cannot be corrected only in the case of | A1l. - + g | A | l + p 0. At the generated address from the passive table 55, the correction register is added to the output register 56, which must be added to the defective module with an erroneous the remainder of the operand (the binary code of the channel number is indicated in the same selected word). With the binary code of the defective channel number, the switch 57 permits the addition of the remainder of the current operand along the defective module and the resulting correction in the corresponding modular addition matrix of the arithmetic logic node. The result of the correction is taken to be the true value of the remainder in the defective module. If the defective module gives regular failures during the repeated passage of the software correction operator, the switch switches the stationary defective modular channel to the reserve or one of the redundant ones. When building a numerical control system based on a binary number system, and not a JUICE, organizing the process of identification and error correction, similar to that used, would require the use of verification codes with the number of control operations proportional to the number of bits of the information part of the operands, and not the number of information modules OK, which would dramatically reduce the effective life of the numerical control system. the subject of the invention 1. A multi-coordinate numerical control system comprising a sequentially connected reading node, an input register and an input information switch, one output of which is connected to an arithmetic logic node through the address encoder of a semi-personal storage device and a semi-permanent memory node. the encoder of the address of the operative storage device also with the arithmetic logic unit, the third output through the function decoder -with the number indicators to adra and tool numbers, and the fourth - with the decoder of the algorithm codes, the operator console connected to the input register, the corresponding output of which through the input information control node is connected to the reading node, the output switch, whose input is connected to the arithmetic logic node, and the output the communication node with the drives, the movement indicator and the microprogram control node connected to the arithmetic logic unit that is connected to the input information switchboard, and the control node for the execution of technological commands, in order to expand the scope and increase reliability, it contains a priority node, a control output node, and a control, correction and reservation node, the priority node being connected to the reading node, the input information switch, the microprogram control node, a node of a semi-permanent memory device, a node for monitoring the execution of technological commands, an arithmetic logic node, a decoder of the codes of the algorithms, and a node for issuing control actions The connecting inputs are connected to the operator panel and the microprogram control unit, and the output to the output switch, the control, correction and redundancy node is connected to the arithmetic logic unit. 2. A system according to claim I, wherein the priority node contains a sequence switch, the inputs of which are associated with the algorithm code decoder and the microprogram control node, and the outputs with two registers for the wok and the step algorithm register, the outputs of the registers for the wok are connected with the step algorithm register, to the inputs of which the polling switch buses and clock circuit are connected, and the outputs are connected to the control inputs of the address encoder, the outputs of the clock circuit are connected to the address encoder and the counter register associated with by moves of the first comparison circuit, the output of which is connected to a clocking circuit connected to registers behind the wok, a polling switch, a group operator address register, a time register, a reading node, an input information switch, a microprogram control node, a control circuit execution node , to the inputs of which are connected the outputs of the control output unit and the time register associated with the outputs of the semi-permanent storage node, which are connected akzhe to the register operator group addresses connected to the node firmware control, and the count register, connected to the arithmetic logic unit. 3. The system according to claim 1, wherein the control output unit contains step counters on coordinate axes, the outputs of which are connected to the control buses of the first decoder, a matrix of speed coefficients, the inputs of which are connected to the outputs of the decoder, a register the speeds, the outputs of which are connected to the counter of the period of control actions associated with the output of the collecting circuit, the first counter of the speed number is connected through the coincidence circuit with the second counter of the speed number, and the outputs of both counters are connected About the comparison circuit, the second decoder, the inputs of which are connected to the outputs of the second speed number counter, and the outputs on the speed matrix and the path, the binary counter of the speed number change, the outputs of which are connected to the input of the matching circuit through the collecting circuits, the output of which is connected to the inputs first speed number counter. 4. The system according to claim 1, wherein the control, correction and reservation node comprises a base expansion circuit made in the form of cascade-connected groups of modified addition matrices, whose inputs are connected to the arithmetic logic node, and the outputs - to the first inputs subtraction matrices, the second inputs of the subtraction matrices are connected to the arithmetic logic node, and their outputs are connected to a comparison circuit, the output of which is connected to the switch via serially connected register of the address of corrections, the passive table and the parallel register The modular channels and arifmetikologicheskim node.

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