SU1372329A2 - Channel-control device - Google Patents

Abstract

The invention relates to computing, intended to control I / O channels. The aim of the invention is to increase reliability by recovering from the failure of any firmware of the device. Device for pack

Description

(L

Wfff

ifgyi V / "W 52

paFt. ieiiHH Kana.naNfH contains the register i of the address of the current multi-channel, the buffer- nbrii data register 2, the node 3 elements AND, the buffer register A} 1 values, the buffer register 5 microcommand addresses, the main register 6 data, control register 7, the destination address register 8, main register 9 microcommand addresses, switches 10, 14, node 11 elements OR, register 12 errors, element 15, element OR 13, adders 17, 20 modulo two, blocks 19, 31 of the address control of local memory or registers

The invention relates to computing, is intended to control I / O channels and is an improvement of the invention in accordance with the authors. St. No. 877519.

The aim of the invention is to increase reliability by recovering from the failure of any firmware of the device.

The drawing shows a block diagram of the device.

The device for controlling channels contains the register I of the address of the current microcommand, the buffer register 2 of data, the node 3 elements AND, the buffer register 4 of the destination address, the buffer register 5 of the address of the microcommand, the main register 6 of data, the register of control 7, the main register 8 of the destination address, the main register 9 microcommand addresses, the first switch 10, the node 11 elements OR, the error register 12, the element OR 13, the second switch 14, the element AND 15, the group of control inputs 16 of the device, the adder 17 modulo two, the group of address inputs 18 of the device, ne the second local address address control unit 19 or channel registers, modulator 2 adder 20, processor 21, microprogram control unit 22 arithmetic logic unit 23, random access memory 24, local memory 23, micromanaging unit 26; 1Y, unit 27 address control mic

channels, processor 21, block 22 of microprogrammed control, arithmetic unit 23, random access memory 24, local memory 25, block of microcommand formation 26, block of microcontrol address control 27, channel address register 28, channel selection block 29 , synchronizer 30 for split-cycle faults, switch 32 buses, split-cycle control unit 33, microprogram interrupt control unit 34, block of transmitted bytes determining unit 35, comparison unit 36. 1 il.

five

„35

commands, channel address register 28, channel address selection block 29, split cycle failure synchronizer 30, local address memory block or channel registers second block 31, bus switch 32, split loop control block 33, firmware interrupt control block 34 determining the number of bytes to be transmitted, compare unit 36, device input buses 37-45, device output buses 46-52.

The device works as follows.

The input-output operation is initiated by an input-output command executed by the processor 21. The command contains the channel address and the device address in the canape. Then, the channel address word is read from the fixed area of the RAM 24, which indicates the address of the first channel command word containing the command code to be executed, the starting data address, the transmitted byte count, and special features. The data transfer operation is then carried out under the control of the command word of the channel filled with the microprogram implementing the input-output command in the working area of the local terminal 25 for each channel and in the channel registers. For addressing local memory areas for channels and channel registers, the firmware enters in register 28

channel number on which the command is executed. The channel number enters the channel address selection block 29, which forms the potential of the currently selected channel. When a microcommand that accesses the local memory area 25 is executed, the potential of the channel and the control signal 16 blocks 19 and 31 produce a commuting signal 47, which addresses the local memory area 25 of the selected channel, and also enters the 32 bus switch. switching of the selected channel with the device. When reading the channel command word, the command code being executed, the two low-order bits of the address, the four low-order bits of the byte counter, and special features are entered into the switched channel registers.

After receiving all the necessary information, the channel frees up the processor 21 to execute the following commands and continues to work using the information located in the local memory 25 and the channel registers using split loops that are used to transfer data between the channel and the RAM 24, following 1x microprograms: state processing, organization of a chain of commands and a chain of data, indirect addressing of data.

If it is necessary to call the corresponding microprogram, the channel establishes a request for a firmware interrupt, which, together with the code of the called microprogram, enters block 27 and block 34 through the group of request 39.

Block 34 records the requests from the channels by the synchronization signal from bus 16, generated by block 22, and determines the highest priority, with the highest priority for the channel with a lower number. An exception is the request for indirect data addressing microprogram, which has the lowest priority, i.e. this request is processed only after servicing requests from other channels, even lower priority ones.

Method of detecting offsets in the device Based on the introduction of additional equipment for generating a code in which a computer error is reduced to a logical error. Control circuits are designed mainly for

Q 15 20

25 so

Q

ds

50

five

Handling single and odd multiple errors. The main control method is the control of the oddness of tires. Scheme: the control unit and the adder 17, detecting an even number of units (including the control unit), gives a signal of the airstrike. In addition to monitoring oddness, other methods are used, in particular, the control by duplicating the local address memory control block or channel registers, for which besides the main block 19, the second block 31 and the block 36 are shown, giving out the error signal.

Recovery after a failure is calculated for intermittent failures, which are caused by changes in factors such as temperature, voltage changes in the secondary power source, interference, etc. and consist in repeating the failed microcommand. To repeat, it is necessary to have the address of the failed micro-command and source operands.

In the selected microcommand system, the function part of the current microcommand is executed in the loop of the next microcommand. Therefore, depending on its type, the failure of each microcommand can be fixed in its cycle or in the next and memorize the information for creating a control point for restoring the desired microcommand for the failed (type 1 error) and the previous one (type 2). the cascade of registers storing the state before the failure — the main registers reflect the state for the previous microcommand, and the buffer registers for the current microcommand.

In each micro-command, the status of the buffer register of micro-command address 5 is written to the main register 9 of the micro-command address, and then the current value of the micro-command address from the I register of the current micro-command address is written to the buffer register 5, and the gates for entering into the specified registers are received from the output of the block 16 22

When this occurs, the data is entered into the buffer data registers 2 and the destination address A and the main registers 6 and 8, respectively. When a fault occurs, a signal about the error from one of the adders 17 modulo two or from block 36 goes to the element group 5137232

and 3, to the input of which the gates arrive, from the output of block 22 via bus 16, and from the outputs of the group of node elements And 3 arrive at the input of register 7 and to r the input of group of node of elements OR 1I, where they are combined according to the types of errors depending on the time of occurrence, From the output of the node group of the elements OR 11, the types of errors go to the register 1210 and to the switch 14, to the second input of which the output of the block 29 receives the potential of the channel during which the malfunction occurred, and the first input to the gate of the synchronizer 30.

15

The split loop is used to exchange data between the memory and the channels and is executed as a microcommand. The memory can interrupt any running firmware, and the malfunctions that can occur in the split cycle are not related to the interrupted firmware that serves and to the channel at the request of which the split loop was executed. The switch 14 and the synchronizer 30 serve to separate the failures in the firmware and in the split cycles and to determine the channels associated with these procedures. The information signal to the synchronizer 30 comes from the output of the split-cycle control unit 33. The gated signal in the split cycle from the output of the switch 14 through the output of the device via bus 51 enters the channels to set the channel down.

In addition, the output of synchronizer 30 blocks the setting of register 12, the output of error register 12 is collected by the OR element 13 to generate a common error signal, which from the output of the OR element 13 is fed to the input of AND 15 element to block the census gate from the buffer registers 5, 2 and 4 in the main registers are 9, 6 and 8 respectively. The census gate, started from the output of block 22 to the input of the AND 15 element, passes or does not pass through the AND 13 element depending on the blocking from the output of the OR 13 element. The main registers 9, 6 and 8 and the control register 7 through the switch 10 can be read and analyzed by recovery software.

five

0

five

0

five

0

five

0

five

Claims (1)

Invention Formula A device for controlling channels by ant, ev, no. 877519, about t and i ch i l e f so that, in order to increase reliability by recovering from the failure of any firmware of the device, the address register of the current microcommand is entered into it , main and buffer data registers, second block of local address memory management and channel registers, main and buffer microcommand address registers, control register, two switches, error register, split cycle synchronizer, comparator unit, OR element node, AND node , element OR, element AND, the group of control inputs of the device is connected to the control inputs of the current microcommand address register, the buffer address registers of the destination address microcommand, the second local address control block and channel registers, the split loop synchronizer, the control register, node of the elements And and the first input of the element And, the group of address inputs of the device are connected to the group of information inputs of the address register of the current microcommand whose outputs are connected to the group and formation inputs of the buffer register of the microcommand whose outputs are connected to a group of information inputs of the main register of the microcommand whose outputs are connected to the first address group of inputs of the first switch; information, control and second address groups of inputs of which are connected to the outputs of the main data register respectively; and the main register of the destination address, the output of the first switch is connected to the first information address group of outputs of the device, inform The input input group of which is connected to a group of information inputs of the buffer data register, the outputs of which are connected to a group of information inputs of the main data register, information outputs of the first local address control block and channel registers are connected to the first group of inputs of the comparison unit and the information input group of the buffer address register destination, the outputs of which are connected to the group of information inputs of the main register of the destination address, the output of the separation control unit cycles is connected to the information input of the split-cycle synchronizer, the output of which is connected to the control inputs of the second switch and the error register, the outputs of the channel address selection block are connected to the address group of inputs of the second switch and the group of information inputs of the second address control block of the local memory and channel registers, information outputs of which are connected to the second group of inputs of the comparison unit, the output of which and the group of control inputs of the device are connected to the group of inputs of the electrical node And, the outputs of which are connected to the group of information inputs of the control register and, through the node of the OR elements, to the group of information inputs of the error register and the information group of the outputs of the second switch, the outputs of which are the second address information group of the device's outputs, the output of the error register through the OR element with the control input of the microinstructor address control unit and the second input of the And element, the output of which is connected to the control inputs of the main microcommand address registers, data and a rez administration.