SU1314344A1 - Device for checking digital blocks - Google Patents

Abstract

The invention of the system of automation and computing, and b. used to control digital nodes and blocks. The purpose of the invention is to expand the functionality by providing control of digital blocks with pulse-potential input effects. The device contains a test generator, two switches, a comparison block, two memory blocks, a buffer register, a control block, a group of shift registers, a block of tasks for transition conditions to the next microtest. Depending on the type of monitored digital block, the test generator enters into two memory blocks codes of impulse and potential effects. In the shift registers there is an immediate temporary formation of impulse effects. The response is compared with a reference, stored in a block where potential effects are recorded. 1 h. the item of f-ly, 4 ill. S WITH OO 4 4

Description

1314344

12

The invention relates to the electronic of the following commands: "Start the computational technique and can be checked," Download, "Test," Used in the equipment of the automated-growing state. Thus, from the monitoring and diagnostics of the digital power 1 and the control unit 4 of the first nodes, two types of information are provided: control purpose of the invention - extending the functional data (commands) and the actual dannational capabilities due to the provided (elementary tests) . Managers

The ability to control digital data (commands) coming from coarse blocks with impulse-potential input-feeder 1, initiate certain valid actions. devices, and control data

FIG. 1 shows the scheme proposed- (word of the state). The devices contain an inm device; in fig. 2 - block up-information about its readiness for determination; in fig. 3 - block task actions.

conditions for the transition to the next micro-Necessary to control some

test; in fig. 4 is a circuit for switching on a block, the program is called according to the code of a single group of shift registers. The measure of the program from drive 1 and the input device (Fig. 1) contains a generator through the input block 2 in the corresponding tests, built on drive 1 to the relevant device blocks. By process

the formation and the input block 2, the buffer re-entry of the program is controlled by the block 4, manager 3, the block 4, the control unit 5, in-line.

diction, switch 6, blocks 7 and 8 pa —At the command “Beginning a check, a 4 M unit; the switch 9, the comparison unit 10, the control 20 is set to the initial coset of the shift registers 11, the monitoring required for the control. In the digital unit 12.gistr 3, the installation codes of the commu- nication unit are entered (Fig. 2) contains detators. By the command "Load elementary encoder 13, elements AND 14-19, electronic tests are recorded in blocks 7 and 8, cops OR 20-22, triggers 23-25, memories. By the command "Testing unit 4, the address counter 26, the long-control counter 27 selects from the memory of the first test set, the formers 28 and 29 the elementary test. From the external pulse memory unit 7, the impulse generator 30 is taken part of the action, containing the unit 31 setting transition conditions to potential signals, which through the next microtest, inputs 32-35 of the switch 6 and 9 are fed to the control inputs, outputs 36 -43 control unit - Q ka 12 is a standard that goes to block 10 of a laziness comparison, the service information, which the Block specifies the transition conditions to is barely used by control unit 4 for the next micro test (Fig. 3), contains the de fi nitions of a specific algorithm element storage unit 44 to perehodanoy rows check conditions. From the memory block 8, select the next micro test, register 45, the codes of the pulse signals, shift register 46, multiplexers 47-49, act. They are supplied to the shift address inputs 50 of the block, the input 51 of the shift, the registers which, by the signal of the block 4, the synchronization input 52, the outputs 53-55 of the edge, form the pulse signals of the block. The input to the block 12 are the Group of shift registers (Fig. 4 ) contains switches 6 and 9. Separation of the shift registers 56, informational elementary tests is ensured by the fact that inputs 57, synchronization input 58, input 5940 memory block 7 is divided into reference-shift zones, serial 60 and parallel, impacts and service information, outputs 61 registers shift group. The reaction unit 12 passes through the switching device. The device operates as follows 9 in block 10 comparison and, according to the signal of the Control program, all control logic blocks 4 are fixed in it and the blocks that can be checked are compared with the reference. In the case of the use of the proposed device, the comparison unit 10 generates rods, is stored in the storage device 1 and having the error signal, transfers it to the unit 4, the following structure falls: the code of the object that changes the word neither, trol (program numbers), installation codes allows the transfer of the reaction to block 5 of switches, elementary tests. Elemental reading and suspend operation. The unit tests implement elementary pro-jO solutions.

Verifications and are sets of eta-In the case of coincidence of the standard with reactons and effects, followed by a case, the control unit 4 selects from

information. The signals in memory are the next elementary test, etc.

HII is divided into potential and momentum-When do the last test suite,

ny. The potential signals during control block 4 change the word elementary check constant condition, and they do not stop the operation of the device. Pulsed - vary. Whether testing is completed and there is no signal.

A program that implements a pro-error algorithm, then a new one is entered

The test is stored in the accumulator 1 and the state of the test information in the memory blocks, or the verification of this monitoring object is completed. If an error signal is present, testing ends. The control unit 4 operates as follows. The commands 33 from the input block 2 are decoded by the decoder 13. The command "Start the checkout resets the address counter 26 and the triggers 23-25. The trigger 24 permits the passage of the clock signals of its generator 30 through the AND 16 element to the counters 26 and 27 and the AND element 17. The passing of the clock signals through the AND 17 element is prohibited by the trigger 23. The write signal 36 to the register 3 is formed by the And 14 element from the data tracking signal 32 from blo10

will become zero, the trigger 23 is reset, which locks the element AND 17 and issues a signal about the end of testing.

Claims (2)

Invention Formula I. A device for monitoring digital blocks containing a test generator, first and second switches, a comparison unit, a first memory block, a buffer register and a control block containing an address counter, a decoder, a pulse generator, five AND elements, two OR elements, and the bit outputs of the address counter are connected to the address inputs of the first ka 2 input. The trigger 25 permits recording of the 5th memory block, the first group of outputs is first into the group of shift registers by signal 41. By the command "Loading signal 32 for tracking data through element 15, the single pulse generator 28 is triggered, which generates the output signal 37 of the device for connecting to the input group of the monitored digital unit, the first group of information inputs of the first switch is a group of v. records in memory blocks 7 and 8. The recording is made up of 20 doses of the device to be connected to the group at the address obtained at the output of the controlled digital block. By the same signal, the contents of the bill, characterized in that, for the purpose of the raschik 26, the address is increased by one the functionality. The command "Testing runs odds due to the ability to control worldlord 29 single pulse. With its 25 digital blocks with pulse-potential input effects, the device additionally contains a second memory block, a group of shift registers, a display unit, and a control unit contains three triggers. using a signal, he cocks the block 31, writes the code for the execution of the microcommand in the counter 27, and sets the trigger 23, which permits the passage of clock signals through the AND 17 element. two formers of a single pulse. on block 31, the address of the micro-command and the code of the thirty-third test duration counter. the sixth element AND, the third element OR, and the block for setting transition conditions to the next microtest, the output group of the feature of the address of the test set vector of the test generator is connected to the group the duration of the microcommand is the service information coming from the memory block 7 to the input 35. In accordance with the selected microcommand, the block 31 generates a certain a sequence of signals implementing 35 information inputs of the buffer register. the testing process, establishes a trigger 25, which permits the shift 41 in the registers on the signal 43 from the output of the master oscillator, sets the counter 27 in the subtraction mode and prohibits the group of outputs of the test word feature, test generator is connected to the groups of information inputs of the first and second memory blocks, the output group of the feature of the test generator code test code passing the clock signals through the element 40 is connected to a group of information inputs And 17. When the contents of the counter 27 of the decoder, the first and second groups stand out equal to zero, the flip-flop 25 is reset, the buffer register moves connected to the group-shift 41 in the sweep register 11 to stop the control inputs of the first and second block, and block 31 continues working out the switches, respectively, a group of exhausting the time sequence. The second switch is connected to the second The bank from the output 42 of the unit 31 is polled by the comparison unit 10. In the case of an incomparison, the error signal from the comparison unit 10 arrives at the input 34 and sets the trigger 24, which locks the element AND 16 and generates an error signal 40, which enters the display unit 5. In the case of the comparison of the standard and the reaction, the trigger 24 retains the zero state, the block 31 generates a signal that decreases the contents of the counter 26 of the address by one and the group of information inputs of the first switch, the second group of outputs of which is connected to the first group of information inputs of the comparison unit, the second group of information inputs of which IJQ is connected to the first group of outputs of the first memory block, the second group of outputs of which is connected to the first group of information inputs of the second the switch, the second group of information inputs of which is connected to a group of a sequence element OR 22 enters a code of the duration of 55 and parallel outputs of registers the following microcommand in the counter 27 and the shift group, the information inputs cocks up block 31. Next, the operation of the circuit, which is connected to the outputs of the second bloter. When the contents of the memory address counter, the output of the “Unequal block compared to 0 will become zero, the trigger 23 is reset, which locks the element AND 17 and issues a signal about the end of testing. Invention Formula I. A device for monitoring digital blocks containing a test generator, first and second switches, a comparison unit, a first memory block, a buffer register and a control block containing an address counter, a decoder, a pulse generator, five AND elements, two OR elements, and the bit outputs of the address counter are connected to the address inputs of the first 5 memory blocks, the first group of outputs memory block, the first group of outputs The first switch is the output group of the device for connecting the monitored digital block to the input group, the first group of information inputs of the first switch is the device's input group for connecting the output group of the controlled digital pulse generator to the output group. test set duration counter test set duration counter the sixth element AND, the third element OR, and the block for setting transition conditions to the next microtest, the output group of the feature of the address of the test set vector of the test generator is connected to the group the group of outputs of the test word feature, test generator is connected to the groups of information inputs of the first and second memory blocks, the output group of the feature of the test generator code test code connected to a group of information inputs switches, respectively, the group of outputs of the second switch is connected to the second the group of information inputs of the first switch, the second group of outputs of which is connected to the first group of information inputs of the comparison unit, the second group of information inputs of which is connected to the first group of outputs of the first memory block, the second group of outputs of which is connected to the first group of information inputs of the second switch , the second group of information inputs of the coordinate is connected to the group of serial and parallel outputs of registers SRI is connected to the information input of the display unit, the output of the synchronization attribute of the test generator is connected to the first inputs of the first and second elements AND, the output of the second element AND is connected to the write input of the buffer register, the output of the third element AND is connected to the input of the blocking generator test, the output of the fourth element AND is connected with the synchronous input of the address counter, with the synchronization inputs of the group shift registers, with the first input of the fifth And element, with the synchronous input of the test set duration counter, and with the synchronous inputs of the first the first and second shapers of the single pulse, the direct output of the first trigger is connected to the shift inputs of the group shift registers and the subtractive input of the test set duration counter, the bit outputs of the address counter are connected to the address inputs of the second memory block, the write / read input of which is connected to the output the first single pulse generator, with the entry / recording input of the first memory block and with the summing input of the address counter, the third group of outputs of the first memory block is connected to the information group x inputs of the test set duration counter, the transfer output of which is connected to the first input of the first OR element, the output of the second OR element, is connected to the reset input of the second trigger, the inverse output of which is connected to the first input of the third And element, the second input of which is connected to the first output of the optimizer and the first input of the generic element I, the output of which is connected to the resolution input of the display unit, the synchronization input of the comparison unit is connected to the first output of the task block of the transition to the next microtest, the output "Equal to the comparator unit is connected to a single input of the third trigger, the inverse output of which is connected to the first input of the fourth element I, the second input of which is connected to the output of the pulse generator, the second output of the descrambler is connected to the second input of the second element I, to the input of the reset of the address counter, to the input reset the third trigger, with the second input of the first element OR, with the first input of the second element OR, the second input of which is connected to the transfer output of the address counter, the output of the first element OR is connected to the reset input p of the first trigger, the inverse output of which is connected to the second input of the fifth element I, the output of which is connected to the synchronization input of the block for setting transition conditions to the next microtest, the input group of initial conditions of which is connected to the fourth group of outputs of the first memory block, the output of the third element OR is connected with the input of the task of the logical condition of the block of tasks for the conditions of transition to the next microtest and with the input of the resolution of the counter of the test set duration, the second output of the block of the conditions of the transition to The next microtest is connected to a single input of the first trigger, the third output of the block for setting transition conditions to the next micro test is connected to the first input of the third element OR, to the subtractive input of the counter {sa address, the output of the second driver of a single pulse is connected to the second input of the third element OR, and to the single input the input of the second trigger, the direct output of which is connected to the third input The fifth element And, the third output of the decoder is connected to the input of the resolution of the second shaper of a single pulse, the fourth output of the descrambler is connected to the second input of the first element And, the output of which is connected to the input of the resolution of the first a single pulse former; the direct output of the third trigger is connected to the second input of the fifth element I. 2. The device according to claim 1, characterized in that the block setting transition conditions the next microtest contains a storage unit for transition codes to the next microtest, a register, a shift register, and three multiplexers, the synchro-input of the unit connected to the synchro-input of the shift register, the outputs of which are connected to the information inputs of the first, second and third multiplexers, the outputs of which are connected to the first, the second and third outputs of the block, respectively, the first, second and third groups of outputs of the register connected to the address inputs of the first, second and third multiplexers, respectively, the information inputs of the register are connected to the outputs of the storage unit codes for the conditions of the transition to the next microtest, the group of address inputs of which are There is a dinene with a group of inputs for setting the initial conditions of the block, the input for specifying the logical condition of which is connected to the input of the register resolution and the shift input of the shift register, whose information input is connected to the positive potential bus of the block. sri. 3 From 8 57