SU1302284A1 - Device for checking and diagnostic testing of logic units - Google Patents

Abstract

The invention relates to the field of computer technology and can be used as a device for monitoring and diagnostics of logic blocks of technical means of automation and computer technology. The aim of the invention is to expand the nomenclature of controlled bikes by providing verification of blocks whose input and output levels correspond to different types of logic or only ECL logic, or only TTL logic, as well as blocks having both TTL and ECL levels. This goal is achieved by the fact that a mask register and a switch are entered into a device for monitoring and diagnosing logic blocks. 5 il.

Description

The invention relates to computing and can be used to monitor and diagnose logic blocks.

The purpose of the invention is to expand the range of monitored blocks by providing verification of blocks whose input and output levels correspond to different types of logic; either only ECL logic, or only TTL logic, as well as blocks that have both TTL and ECL levels,

Figure 1 shows the block diagram of the device; figure 2 - block diagram

block 9, contacts 35 of switch relay 14, trigger 36 of mask register 7, element 37 with an open collector output, coil 38 of relay 5 of switch 14, trigger result 39 of result register 8, LED 40 of indication block 10.

Memory block 1 is intended for storing test information, a mask to TTL - ECL, a true response at the outputs of the control object.

Unit 2 synchronizes the operation of all units of the device, i.e. controls the reading of information from memory block 1

synchronization; FIG. 3 is a block diagram by selecting the mode of block 5, writing and ka buffer registers; figure 4 - the shift of information in block 5, recording

functional diagram for installation and interrogation of one output of the diagnosed unit; on fig.Z - the algorithm of the device.

The device for monitoring and diagnostics of logic blocks contains a memory block 1, a synchronization block 2, a start block 3, a compare block 4, a block 5

information in registers 6, 7 and 8.

Block 3 is intended for information. Signals Reset and Start for 20 block 2, as well as the formation of the higher address bits of memory 1.

Comparison unit 4 is designed to compare reference codes with signals at external contacts of an object 15

J OO-li V 4 H O. JJ J L V-LiI / 1 ,, i.

buffer registers, register 6 tests, control, register 7 masks, register 8, the result- Block 5 is designed to receive

one, the first block of 9 amplifiers, block data in a sequential code from

10, the first block 11 of the memory pre-block 1, receiving data into level drivers, the second 12-block code block from the monitored amplifiers, the second block 13 of the converters f5 through the blocks 11,12 and 13 and

level switches, bidirectional com switch 1.4 and output of data in the serial code in the comparison block 4 and in the parallel code in the registers 6, 7 and 8.

mutator 14 and controlled block 15.

The synchronization unit 2 (FIG. 2) contains a pulse generator 16, an AND element 17, a first trigger 1.8, a counter 19, a permanent memory 20, an OR element 21, a second 22, a third 23 trigger.

The block 5 of the buffer registers (FIG. 3) is designed as a group of registers 5.1-5. § shift and has a width equal to the number of outputs of the object 15 of the control. Inputs 24 are designed to control the operation modes of registers 5.1-5.8. Inputs 25 are designed to receive data from registers 5.1-5.8 in a serial code, and inputs 26 to receive data in a parallel code. The outputs 28 and 27 of register 5 are designed to output data in serial and parallel codes.

The device (figure 4) contains the element 29 of the register 5, the element 30 of the block 1 1 (conversion TTL - ECL), the element 31 of the block 12, the element 32 of the block 13 (conversion ECL - TTL), the trigger 33 of the register 6 tests, the element 34 with open you collector

block 9, contacts 35 of switch relay 14, trigger 36 of mask register 7, element 37 with an open collector output, switch 38 relay coil 38, result trigger 39 of result 8, LED 40 of display 10.

Memory block 1 is designed to store test information, the TTL mask - ECL, the true response at the outputs of the control object.

Unit 2 synchronizes the operation of all units of the device, i.e. controls the reading of information from memory block 1

information in registers 6, 7 and 8.

Block 3 is intended to provide information: the Reset and Start signals for block 2, as well as the generation of high-order bits of the address of memory block 1.

Comparison unit 4 is designed to compare reference codes with signals at external contacts of an object 15

  ,, i.

the case code in block 4 comparisons and in parallel code in registers 6, 7 and 8.

The mask register 7 is for controlling the switch 14.

The device works as follows.

Before testing, it is necessary to perform initial setup of triggers 18, 22 and 23 and counter 19 of block 2. By pressing the Reset button of the start block 3, the logical 1 signal is fed to the reset inputs trig Q

22 and 23 and to the third input of the element OR 21 of block 2. The output of the element OR 21 is a logical 1 signal input to the reset input of the trigger 18 n from its upper output - to the reset input of the counter 19.

When a Start signal is received from block 3 in block 2, the trigger 18 is set to one, 5 by opening AND 17 to pass clock signals from the output of the generator 16 pulses to the counter input of .19. The counter 19 generates, in parallel code, a sequence of command addresses located in the permanent memory 20, from the outputs of which the command information follows the blocks of the device according to a program, the algorithm of which is shown in FIG.

At the beginning of the program execution, the TTL - ECL contact mask is read from memory block 1 to block 5 (Fig. 1). In block 3, the high-order bits of the addresses of memory 1 are set, and the low bits are searched by block 2, and the number of register bits 5 to 8 is equal to the number (M) of information outputs of the monitored block 15. Block 5 is subdivided into several (N ) registers. The number N is equal to the data bus width of the memory block.

Fig. 3 shows an example of the execution of block 5 with and. Each register 5 is a shift register with a length of 24 bits. Practically, block 5 can be implemented on K155IR1 microcircuits. Information from the output of memory block 1 is fed to a group of information inputs 25 of block 5. Information is received in registers 5 by the presence of control signals on a group of inputs 24 received from block 2. By control signals, block 5 receives one byte of information from the block 1 memory and shifts the information therein by one bit to the right. Thus, 24 consecutive control signals are required to completely fill the block 5.

After the block 5 is filled, its contents by the control signal of the block 2 are simultaneously rewritten into the mask register 7. Thus, the TTL - ECL contact mask is written to the mask register 7 and all relays of the switch 14 are tuned accordingly. Next, in block 5, the first test set is written from the memory block and rewritten to the test register 6 by the control signal of block 2. In register 6, a modified test set is written in which the bits corresponding to the inputs of the control object are the same in the original test set, and the bits corresponding to the outputs of the controlled block 15 contain one.

The TTL inputs of block 15 receive TTL levels of signals from the register 6 output of tests through block 9 and switch 14. The ECL inputs of block 15 receive ECL levels of signals from the output of register 6 tests through block 9, first transducer block 11 levels, block 12 and switch 14. At the outputs of block 15, output signals are generated. The input and output signals of the block 15 TTL levels through blocks 11, 12 and 13 are fed to the inputs 16 of block 5 in the parallel code. Information on control signals of block 2

5 is written to block 5 and rewritten into result register 8. Then, byte-by-by-one comparison of this information from memory block 1 to comparison block 4 is performed.

0 According to the signal of block 2, the result of the comparison is transmitted from the block 4 of the comparison to block 2. In the case of a non-comparison signal from block 4 in block 2, the trigger 23 is set to the single state, and through the element 21, the trigger 18 is set to the zero state and resets counter 19, stop the operation of the device. With the release of the trigger 23 block 2 comes

0 a signal to the display unit 10, in which the Scrap indicator is lit, and the state of the result register 8 is displayed. If there is no incomparability, the device goes to

 reading the next test suite. After checking the block 15, the trigger signal is set to one for all test sets by the signal from the overflow output of the counter 19

0 22 and through the OR element 21 flip-flop 18 of block 2. From the output of flip-flop 22, a signal arrives at the display unit 10, in which the End of Test indicator lights up.

5 An example of a functional diagram for the installation and polling of one output of the control object 15 is shown in FIG. 4. Information from memory block 1 (one bit of information) enters

0 to the input of the AO element 29 and the control signals 24 of block 2 is written to this element. When recording ma-. The contacts of the TTL - ECL one bit of this information is rewritten from element 29 into trip 36 of register 7 of the mask according to the control signal of block 2 fed to the synchronous input of trigger 36. In accordance with the state of trigger 36 of register 7 of mask

in switch 14 after passing

through element 37 the relay is triggered

38 and its contacts are flipped 35.1

When recording test information 5, one bit of this information is copied from element 29 to trigger 33 of register 6 tests on the control signal of block 2, which is fed to the sync input of trigger 33. At the TTL control input of the monitored block, one bit of test data comes from the trigger output 33 registers of 6 tests through the element

, 34 of block 9, contacts 35 of relay 38, which in this case are in the 5 lower position of switch 14, to the input of block 15. At the ECL input of block 15, one bit of test data comes from the output of trigger 33 of register 6 tests through block element 34 9, 20 elements 30 of block 11, element 31 of block 12, contacts 35 of relay 38 (upper, position) of switch 14 on

input of block 15. From the TTL output of block 15, one data bit enters through contacts 35 of relay 38 (lower position) of switch 14, element 30 of block 11, element 31 of block 12, element 32 of block 15 to input A1 of element 29 of block 5 , from ECL output of controlled block 15, one data bit enters through contacts 35 of relay 38 (upper position) of switch 14, element 32 of block 13 to input A1 of element 29 of block 5.35. J. ,

In the event that the contact of the monitored block 15 is an output, a logical unit is entered into the trigger 33 of the register of 6 tests, which is not

prevents the passage of a data bit from block F5 to element 29 of block 5. Similarly, the input information of block 15 arrives at the inputs of element 29 of block 5. Using control signals 24 of block 2, input and output information

block 15, entering input A1 of element 29 of block 5, is entered in parallel code into block 5. From the output of element 29 of block 5, the contact status data bits of block 15 are written to the trigger 39 of the register, 8 by the control signal from the block 2 to the trigger input 39. This information is displayed on the indicator 40 of the display unit 10.

Thus, four cases of information passage are considered.

50

relative to the contact of the monitored unit 15, namely: TTL input of the monitored block, ECL input, TTL output of the monitored block, ECL output.

Claims (1)

Invention Formula A device for monitoring and diagnostics of logic blocks, containing a synchronization block, a memory block, a comparison block, a start block, a buffer register block, a test register, a result register, two amplifier blocks and two level converter blocks, the output of the memory block connected to the first information input of the comparison unit and with the first information input of the buffer register block, the first output of which is connected to the first information input. test register, the output of which through the first block of amplifiers is connected to the input of the first block of level converters, the output of which through the second block of amplifiers is connected to the input of the second block of level converters, the first, second, third, fourth and fifth outputs of the syncro block nizations are connected respectively with the synchronous inputs of the result register, the buffer register block, the test register, the comparison block and the memory block, the second output of the buffer register block is connected to the second information input of the comparison block and the second information input of the test register, which is the purpose of expanding the nomenclature of monitored blocks, the device contains a mask register and a bidirectional switch, with the first input-output of the bi-directional switch being the input-output of the device for connecting and to the monitored unit, the second input - the output of the bidirectional switch is connected to the Output of the second amplifier unit and the input of the second level converter unit, the output of which is connected to the second information input of the buffer register unit, the first and second outputs of which are connected to the first and second information inputs of the register the result and the mask register, the synchronous input and the output of the mask register are connected respectively to the sixth output of the synchronization unit and control71302284 Lead input bidirectional comm. the information input of which is connected to the first output of the first amplifier unit, the output of the comparison unit is connected to the reset input of the unit eight After the synchronization, the first and second outputs of the start block are connected respectively to the start input of the synchronization block and the address input of the memory block. Phage. J  Start I ScshpyYaaniv Hoc / fu So bhaynoy petucmp JRecord S register H & XU Find mecmaftix data in bkhozna piiucmp Census S petucmp mtanaS J ja / shsb aviekta reaction / control fa if one register Census peiuemp result i Read more 9ag VNIIPI Order .1217 / 48. Circulation 673 Random polygons pr-tie, Uzhgorod, st. Project, 4 Subscription