SU1319038A1 - Device for debugging programs - Google Patents

Abstract

The invention relates to computing technology and allows for an increase in the efficiency of means for debugging programs. The aim of the invention is to expand the diagnostic capabilities of the device. The device contains a mode setting unit, AND elements, a controllable delay unit, a pause trigger, a single signal generator, a comparison unit, a trigger, a comparison circuit, counters and a random access memory unit, a register, a delay element, and a display unit. The device allows organizing up to 17 stop modes of the program being debugged and recording information on the progress of the program, which can be used to eliminate errors in the program. 4 il. : UD 00 00

Description

The invention relates to computing technology and can be used for debugging programs, as well as for working out and tuning specialized external control devices for computing: x complexes.

The aim of the invention is to expand the diagnostic capabilities of the device.

FIG. 1 shows a block diagram of the proposed device; Fig 2 is an example of the execution of the comparison block; in fig. 3 and 4 are timing charts for recording and reading information.

The device contains a debugging mode setting unit 1 with an AND 2 element connected to it, a controlled delay unit 3, an AND 4 element, to the output of which a single signal generator 6 is connected to the output of the start-up trigger 5 ;. In addition, a block 7 is connected to block 1, a trigger 8, an element 9 and 9 through a comparison circuit 10 a counter 11 connected to an address counter 12 connected to an operational memory block 13, a register 14 and a delay element 15 which is connected to an element And 16, Moreover, the outputs of block 13 are connected to the inputs of block 17 of the display, and the inputs of the device are connected respectively to address inputs 8, information inputs 19, clock inputs 20, input 21 of the exchange direction and input 22 of the sign of the presence of information on the input. In this case, the comparison block 7 is associated with the block 1 of the addresses of address 23, data locking 24, information 25, locking of the exchange direction 26, exchange direction 27,

Comparison unit 7 (FIG. 2) consists of three matching circuits 28-30, the output signal of circuits 29 and 30 arrives at AND 31 through the OR 32 and 33 elements, and the enable signal, the operation of block 7 enters the input of AND 31 through the inverter 34 .

Block 1 is implemented as a set of toggle switches and consists of two parts that are different in construction. The first ensures the delivery of information to the inputs 23, 25, 27 on lines 24 and 26 of the blocking, to the corresponding inputs of the elements 2 and 4, as well as the code, determined by the amount of delay, to the third turn of the block 3 of the controlled delay and one to the inputs of the circuit 10 comparisons.

Block 1 consists of a corresponding number of toggle switches, with the help of which, the specified inputs can be connected either to a logical O or

to logical 1,

The second part of unit 1 is switching (Fig. 1). In it, the inputs and outputs of the constituent parts of the device are switched so as to provide the corresponding operation modes.

To control the reader, a one-shot is entered into block 1, similar to a single-signal generator 6, the output of which is connected to input 1

counter 12.

The device works as follows.

When exchanging via the trunk, the processor and external devices, the data are transferred, followed by the master clock and the acknowledgment signal. The operation of the device, for certainty, is considered when connecting it to the bus bus used in the UHM CM4 (LPS).

Curve 35 (Fig. 3) shows the signal at input 20, curve 36 — at input 22, 37 — at inputs 18 and 19 of data, 38 — at the inputs of the record and block 13, 39 — at the input +1 of the counter 12 addresses, 40 — at the input register entries 14, 41 - at the output of the counter 12 addresses and 42 - at the output of the register 14,

Part I of the diagram shows the operation of reading information from an external device, part II - the operation of writing information to an external device. The external devices include input / output devices, specialized devices and RAM of the CM4 control and computing complex (SMZ). to which the operation of the proposed device for debugging programs is considered.

When reading information from an external device, the UVK CM4 processor first (FIG. 3, diag., I) sets the address

to input 18 and after a time period d1 to the synchronization line (input 20), the external device UVK CM4 decodes the addresses and sets the required information to input 19. Through

time at. the external device outputs a signal to the input 22, according to which the UVK processor perceives information, removes the signal from the input 20, and from

31.

holding signals from input 18. By the absence of a signal at input 20, the external device UVK CM4 removes the signals from input 22 and input 19. The correct address exists during the operation of the signal at input 20, and the correct information at input 19 is during the operation of the signal at input 22 .

Thus, the correct address and information is located on the trunk while simultaneously operating signals on lines 20 and 22 (ut ,, ut).

When writing information to the external device UVK SM4, this ratio is not violated, therefore writing to block 13 takes place on the output signal of the AND 16 element, which is generated by the coincidence of the signals at inputs 20 and 22. Next, the recording strobe in block 13 is delayed by the delay element 15 so that to the address counter 12 (input +1) it enters through the u-ty time after the recording strobe ends in block 13, the recording strobe in register 14 should start no earlier than the strobe +1 in the address counter, and end with a delay relative to this signal that allows to fix in register 14 the last contents of counter 12 addresses.

Thus, when exchanging through a trunk, the state of all its lines and subrunks (including the exchange direction lines) is fixed in block 13. The state of lines 20 and 22 is equally for each cycle, therefore, recording information from & TIH lines in block 13 does not is produced. At each subsequent exchange via the trunk, the state of this highway is recorded in the next cell of block 13. Upon reaching the maximum possible address, the counter 12 is zeroed out and the block 13 begins to fill in from the zero address. At the same time, new information is recorded; For example, writing to the zero cell occurs only after writing to all subsequent ones. Thus, in block 13 information is stored about the latest states of the highway.

When reading, the operator acts on block 1, from the output of which, after each press of the operator, the corresponding button produces a single impulse (Fig. 4, curve 43). Cree Va 44 shows the status of the outputs of the address 12 counter, curve 45 - you

the input signal of the generator 6 of a single signal 6, curve 46 - output information of the block 13. A single pulse arrives at the input +1 of the counter 12 of the address. At the same time, after the first click, the address of the last exchange information is set. When the operator again acts at the output of block 13, information appears on the penultimate state of the trunk, etc. After the end of the reading of the information of interest, the operator acts on the generator 6 for continuation of the program being debugged.

the signal, while the trigger 5 is stopped, the counter 11 and the trigger 8 are reset, and the address 12 is addressed to; information from register 14 is rewritten by itself, and since this register is

14, the last state of the counter is recorded; information is recorded in block 13 in the cell in which it should be recorded if there were no interruption. In this way,

a complete correspondence is achieved between the information of block 13, and the processes that occur in the trunk when the program is being debugged, regardless of the number of interrupts,

the operating mode of the device and the operator’s influence on this device.

The presence of block 13 with the corresponding control circuits ensures the recording of information about the state of the trunk and the reading of this information, the operation of this part of the device is the same for any interruption modes, while storing and. indication of the corresponding volume

information necessary for success-. Noah debugging programs.

The remaining circuits included in the device interrupt the program being debugged in the location of interest to the operator. Depending on the state of the switching elements in block 1, the device records the following states: accessing a specific address when analyzing

directions of exchange and information are blocked by lines 26 and 24; writing to a specific address when the block is checked to compare information; reading from a specific address; writing specific information to a specific address when there is no lock; reading specific information from a specific address.

The state of the switching elements a, b, from block 1 sets the stop modes: a - 1, b, c — it makes no difference — to stop at the output signal of the comparison block 7 (first mode); a - 2, b - 1, s - stop after passing a specified number of cycles of exchange through the trunk after the signal is issued by block 7 (second mode); a - 2, b - 2, s - 2 - stop for a certain number of impulses of block 7 (third sharp); a-2, b-1, s-2 stop by the number of commands after start (fourth mode).

In the first stop mode, the output of block 7 is directly connected to the input of block 3 of the controlled delay and is stopped according to any of the states fixed by this block, i.e. there are five submodes.

In the second mode, the output of block 7 is connected to the B-input of the trigger 8, and the output of the comparison circuit 10 is connected to the input of block 3, and after the corresponding trunk condition appears, the output signal of the comparator 7 sets the trigger 8, allowing the synchronization signals to pass through the element 19 setpoint from line 20 to the input of the counter 11, In the counter, the number of exchanges through the trunk is counted, this number coincides with that specified from block I, the output from the comparison circuit 10 goes to block 3 and causes a stop.

In the third mode, the counter 11 through the element And 9 is connected to the output of block 7, the trigger 8 is forcibly set, i.e. signal translation to element 9 is allowed. When the corresponding state of the line appears by the output signal of block 7, the contents of counter 11 are incremented by one until the comparison circuit 10 fails, the signal with which causes a stop.

In the fourth mode 4, the comparison block 7 is turned off, the signals are transmitted from line 20 to counter 11, therefore a stop occurs according to the number of cycles of the trunk specified from block 1.

Thus, the proposed device allows you to organize 16 types of stops, in addition, you can organize a stop by the program execution time, if the timer adds one to the contents of a particular cell at an appropriate time interval, and in the comparison block it records the state in accordance with indicated. By changing the information standard, it is possible to set any time interval that is a multiple of the specified timer, without accommodating the main program.

Fully device operates as follows.

The operator starts the program being debugged, exchanges take place on the trunk, information issued by the processor is accompanied by a clock signal at input 20, and information issued by an external device is accompanied by a signal at input 22, and the true state of the highway (true address, true information and exchange direction) starts earlier and ends after the coincidence of the signals at inputs 20 and 22. By the coincidence of the signals at inputs 20 and 22, the state

the line is recorded in block 13; in the interval between exchanges, the address counter 12 and block 13 are prepared for recording the next state of the highway. The entry in block 13 occurs at cyclical changing addresses, with the new information being replaced with the oldest one, which allows storing the last states of the trunk in block 13. At the same time

Comparison unit 7 (the third stop mode) analyzes the state of the highway and, depending on the sub-mode, fixes one of its states.

The occurrence of the desired state leads to the generation of a signal at the output of the comparison unit 7. This signal passes through the element And 9 (b-2) to the input of the counter 11, since the trigger 8 is set by applying a low level

at the entrance (p-2). Counter 11 counts the number of output signals from the block of the 7 comparison. When the contents of this counter 11 reach the state set from the keyboard to the reference inputs of the comparison circuit 10, a signal is generated to the corresponding input of the controllable delayed unit 3, which triggers the pause trigger 5 and interrupt

lazemaya program. After stopping (if necessary, read the information of the previous states of the trunk), the operator through block 1 acts by single pulses on the input +1

the address counter 12, whereby an ever earlier state of the bus is indicated sequentially with each pulse. Upon completion of reading block 13, the operator, if necessary, dials a new mode of operation and initiates a further execution of the program using the single signal generator 6. Moreover, by recording the information from the register 14 to the address 12 by the start pulse, the sequence of trunk states is recorded in block 13 in accordance with the progress of the program being debugged and regardless of the operator’s actions,

Dp of elimination of false alarms to the control input of the comparison unit 7, a signal is output from the output of the element 16, the presence of which indicates the truth of the state of the highway.

Claims (1)

Invention Formula A program debugging DNP device containing a pause trigger, a single signal generator, a debugging mode setting unit, a ram storage unit, a comparison unit, three AND elements, a controllable delay unit, a register, and a display unit, and the output of setting the address of the mode setting unit debugging devices are connected to the first information input of the comparison unit, the address input of the device is connected to the second information input of the comparison unit, the clock input of the device is connected to the first input of the first And element and the clock input of the control unit delays, the output of which is connected to the first input of the second element And the output of the second element And is connected to a single input pause trigger, the output of which 45 is the address input of the device connected to is the output of suspending the device - the first information input of the block For example, the output of the single-signal generator is connected by the zero input of the suspend trigger and the first input of the third element AND whose output is connected to the first start input of the controllable delay block, the start output of the debug mode setting unit, the output of the value -55 by the input of the comparator unit, the outputs of the task of the debug mode setting unit, nor the information codes and direction is connected to the control input of the controllable delay unit, the first one and the exchange of the debugging mode setting unit connected respectively with n o The shutdown of the block for setting the debug mode setting is connected to the second inputs of the second and third AND elements, respectively; in order to expand the diagnostic capabilities of the device during debugging, a trigger, a fourth circuit, a fourth element And, a counter, delay element and address counter, with the information outputs of the RAM block connected with the inputs of the display unit, the input of the presence of information at the input of the device is connected to the second input of the first element I, the output of which is connected to the recording input of the RAM block, to the enable input of the comparison unit and through the delay element to the register recording input and the counting input of the addition the address counter, the outputs of which are connected to the address inputs of the RAM unit and the information inputs of the register, the output of the single signal generator is connected to the zero input of the trigger, the write input of the address counter Sa and the input of the initial installation of the counter, the output of which is connected to the first inputs of the comparison circuit, the output of the register is connected to the information inputs of the address counter, the output of specifying the number of exchanges of the debug mode setting unit is connected to the second input of the circuit compared1 | The output of which is connected to the first stop input of the debug mode setting unit, the output of the comparison block is connected to the second stop input of the debug mode setting unit, the first stop output of which is connected to the second input of the fourth And element, the readout output of the address counter. 0 five 0 memory device, the information input of the device is connected to the third information input of the comparison unit and the second information input of the memory block, the input of the sign of the direction of exchange of the device is connected to the third information input of the memory block and the fourth information input the input of the comparison unit, the outputs, the assignment of information codes and directions neither the exchange of the block setting the debug mode are connected respectively with p 9131903810 The first and sixth information inputs of the mode tribute are connected by the comparison block, the interlocking outputs, but with the first and second inputs of the data block and the exchange direction of the comparison block block block. directions exchange FIG. 2 55 well gh 57 m, 38 and h CV em tt: W H1e Ijrh iH 9 in 2x V v x / vs. U 2 Editor O. Bugir Compiled by A. Sigalor Tehred I.Popovich Order 2514 / 44Tyran 672Subscription VNIIPI USSR State Committee Inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 Phie. Proofreader A, Obruchar