SU1462325A1 - Device for monitoring the succession of performance of program modules - Google Patents

Abstract

The invention relates to automation and computing and is used to monitor the correctness of the execution of programs in an automated object management system and technological processes. The purpose of the invention is to increase the reliability of control. The goal is achieved by the fact that the device contains a memory block 13, three delay elements 2.7 and 8, element 10, two registers 9 and 11, and comparison circuits 3 and 4, an address counter 12, trigger 5, an indication block 6, a converter 1 with appropriate communications. This provides a breakdown of the program into interconnected modules, provides automatic assignment of the current module addresses to the corresponding module numbers and a comparison of the sequence of module numbers stored in the memory block. 2 Il. e cl

Description

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The invention relates to automation and computer technology and is used to control the correctness of program execution in automated systems for managing objects and technological processes, in numerical control machines and other devices and systems with program control.

The aim of the invention is to increase the reliability of the control. I Figure 1 shows the block diagram of the device; FIG. 2 is a diagram j of the address transformer to the code number i of the program module.

A: The device contains a transform; address 1 in the code of the module number: the program, the first delay element 2, the first 3 and second 4 comparison circuits, i trigger 5, indication block 6, second i 7 and third 8 delay elements, first register 9, And 10, second i register II, address counter 12, block: 13 RAM, output of RAM block 14, write input 15, address input 16, clock input 17, information input 18, record sign input 19, sign input change attribute 20 , reset input 21, reference sequence entry input 22.

The converter contains a register 23, n blocks of address analysis of programs, a shaper 25 of the initial setup signals, an encoder 26, information input 27, clock input 28, write input 29, comparison circuits 30, 31, registers 32, 33, and element 34.

The device for monitoring the execution of the program operates in the following modes: writing in the block 1 addresses of the values of the lower and upper boundaries of the sections of the program modules; write to block

14 memories of the sequence of program module program numbers.

The entry in the block I of the addresses of the values of the lower and upper boundaries of the sections of the program modules is as follows.

The input 16 of the device receives the addresses of the values of 1 and the upper boundaries of the sections of the program modules, which are written into the corresponding registers 32 and 33 of the nodes 24 of the pffrator analysis. These actions record the top and

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the lower addresses of the module of the programs to the corresponding node 24 of the range analysis of the addresses of the module, and the sequence number of the node of the analysis of the range will now correspond to the number of the module. The addresses received at the input 27 of the encoder 1 and belonging to one of the address ranges of the program module will be encrypted with the sequence number of the analysis node 24,

The mode of writing to the memory block of the RAM of the sequence of numbers of the modules of the programs of the monitored process.

The input 21 Reset the device is given a signal, which is used to set the address in O of the counter 12 and the installation of the trigger 5 to the initial zero state, on the display unit 6 the normal operation of the device is indicated. The value of the contents of the counter 12 of the address, equal to zero, arrives at the address input of the memory block 14. The information number 5 of the device 18 is fed to the code number of the first module of the program of the technological process being carried out, the device output 18 is the information input of the memory block 14. The Recording signal from the input 19 of the device, and the memory block 14, remember the number of the first module of the program from which the execution of the monitored process begins. To record the subsequent module numbers, the cycle repeats from feeding the signal to the input 20 of the device, which is connected to the counting input of the address counter 12, and increases the counter contents by two, and this value goes to the address input of the memory block 14. The number of sequences of program module numbers recorded in memory block 14 is determined by the cycle of the monitored process. Upon completion of the recording of the sequence of program numbers, the Reset signal is sent to memory block 14 at the device input 21, which sets the address counter 12 to O. The values of registers 9 and 11 are zero, the reset lines are not shown in figure 1. From the input 8 of the device, a first signal is received that permits the passage of information from the output of the register 11 through the element 10 to the input of the register 9, where it is memorized; the signal passing through the delay element 8 is sent by the read signal to block 14

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memory, and since the value of the counter is equal to zero outside the values of the lower and upper 12 addresses, the contents of the boundaries of the module addresses are formed

the zero cell of memory block 14 is read, is fed to the input of register I 1, and is stored in it. In the zero cell of the memory block 14, the first number of the program module was recorded, from which the technological process begins; The first signal from the device input 22, the passage through the delay element 8 enters the counting input of the address counter 12 and increases its contents by two, i.e. the value of the contents of the counter 12 addresses became equal to two. From the installation input 22 of the device, a second signal is received, which permits the passage of information from the output of register I1 through element 10 to the input of register 9, where it is stored, i.e. register 9 contains the first number of the program module, from which the process begins; then the contents of register 9 will be called the number of the current program module; the signal, passing through element 7, is received by the read signal to memory block 14, and if the value of the counter of address 12 is two, the contents of the second cell of memory block 14 are read, input to register II and stored in it. In the second cell of the memory block 14, the second module number of the program of the technological process being executed was written; further, the contents of register 1I will be called the number of the next module of the program; the signal from the output of the delay element 7, the passage through the delay element 8, enters the counting input of the counter 12 of the address and increases its value by two, i.e. The content of the counter 12 addresses is four.

. After performing preparatory operations, the device is ready for operation. The operation of the device is as follows.

In the process of executing the process control program, the program addresses are formed, which at address input 16 are fed to input 27 of block 1 and are accompanied by a clock signal at input 17 of the device, which is fed to input 28 of encoder 1. By a signal at input 17, encoder 1 compares the current program address (at input 16 of the device) with

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the position code of the program module number, which is fed to the first input of the comparison circuit 3. This signal, which is fed to the control input of the comparison circuit 3, compares the value of register I (the number of the current module recorded in memory block 14) with the real number, which comes from encoder I.

In the case of equality of the values of the code of the number of the module being executed, coming from the digitizing unit 1, and the code of the number of the current module stored in register 9, the second output of the comparison circuit 3 will receive a signal arriving at the trigger 5, which Q is brought to the zero state, and the display unit 6 indicates normal operation of the process.

In case of inequality, a signal appears at the first 5 output of the comparison circuit 3, which is fed to the control input of the second comparison circuit A, and the first input of the second comparison circuit 4 receives the code of the number of the executable module coming from block 1, and the number of the next module of the program stored in register II is fed to the second input of the second scheme1 4 of the comparison. In case of inequality, a signal appears at the second output of the second comparison circuit 4, which sets the trigger 5 to a single value, and the display unit 6 will indicate a failure in the process.

In the case of equality at the first output of the second comparison circuit 4, a signal appears that permits the passage of information through register I and 10 from register I to register 9 and simultaneously enters input to register entry 9, i.e. the code of the number of the next module was recorded in the register I I and became the code of the number of the current module; passage through delay element 7 enters delay element 8, read input to memory block 14, and information from memory block 14 enters input of register I1, input to register entry II, which leads to memorization of next code number on register I 1 module; passage through delay element 8 arrives at the counting input of the counter5

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12. addresses, i.e. increases the value of the counter by two - prepares the contents of the counter 13 addresses for the next change in the sequence of numbers of program modules.

The technological process is an infinite sequence of cycles, such a sequence cannot be placed in memory block 14, and it is also inexpedient. Therefore, two clocks before the end of one cycle and the beginning of the other, the proposed device, at input 21, sends a Reset signal, which sets the address counters 12 to O, which is the beginning of a new cycle.

Claims (2)

Formula of the invention I. A device for controlling the sequence of execution of program modules containing a block of RAM, three delay elements, an AND element, a first comparison circuit, first and second registers, characterized in that, in order to increase the reliability of the control, a second comparison circuit is entered into the device, an address counter, a trigger, a display unit and an address converter to the code number of the program module, where the address and the device address inputs are connected respectively to the information input and the recording input of the address converter to one module of the program module, the output of which is connected to the first inputs of the first and second comparison circuits, the device clock input is connected directly to the clock input of the address converter in the code of the program module number and through the first delay element to the read input of the address encoder and And, and through the second delay element - with the input of the second register, with the input of the read attribute of the RAM block, and the third delay element - with the counting input of the address counter, the input of the device’s initial installation is connected with the installation input of the start address n of the address counter and the second input of the zero-setting trigger, the output of which is connected to the input of the display unit, the input of the sign of the device address change is connected to the counting input 15 of the address counter, the output of which is connected to the address input of the main memory block, output d is Ser nen vtorog to data input register, data input Device for 20 roystva, Device recording feature-OPERATION input connected. respectively, with the formational input and the input of the memory block record, the read input of the device reference sequence 25 is connected to the second input of the delay element. 2. The device according to claim 1, of which is that the address converter in the code of the module number of the program contains the address register, the initial set signal generator, the encoder and the program address analysis blocks, each of which contains two comparison circuits , two registers, the element And, and the information input of the address register is connected to the information input of the converter, the output of the address register is connected with the first information inputs of the first and second comparison circuits of the i-ro address analysis block of the program, the second information in the first day and second comparing circuits 35 the clock input of the first circuit is compared respectively with the outputs No, the equality and inequality outputs of which are connected respectively to the first input of the zero setting of the trigger and to the clock input of the second comparison circuit, the output of the first element I is connected to the information input of the first register, the output of which is connected to the second input of the first comparison circuit, the output of the second register is connected to the first the input element And the second input of the second comparison circuit, the equality output of which is connected directly to the sign of the first register and the second input 50 55 first and second registers i-ro of program address analysis, information inputs of registers i-ro program address analysis block connected to the corresponding output of the initial setup signals, the resolution input of which is the input of the converter, output of the first and second comparison circuit address analysis programs are connected respectively to the first second inputs of the AND element, the output of which is connected to the corresponding input of the encoder, the enable inputs 325 And, and through the second delay element - with the write input of the second register, with the read input of the RAM block, via the third delay element - with the counting input of the address counter, the input of the device initial installation is connected to the installation input of the initial address address address and the second input set the trigger zero, the output of which is connected to the input of the display unit, the input of the sign of the change of the device address is connected to the counting input 5 of the address counter, the output of which is connected to the address input of the operational block The am, whose output is connected to the information input of the second register, the information input of the device, the device recording input, is connected. respectively, with the information input and the write input of the main memory unit, the read input of the reference sequence 5 of the device is connected to the input of the second delay element. 2. The device according to claim 1, of which is that the address converter to the code of the module number of the program contains the address register, the initial setup signal generator, the encoder and the program address analysis blocks, each of which contains two comparison circuits , two registers, element AND, the information input of the address register is connected to the information input of the converter, the output of the address register is connected to the first information inputs of the first and second comparison circuits of the i-ro program address analysis block (. P.), the second information the inputs of the first and second comparison circuits35  are united respectively with the outputs 50 55 The first and second registers of the i-ro program address analysis block, the information inputs of the i-ro registers of the program address analysis block are connected to the corresponding output of the initial setup signal generator whose resolution input is the converter record input, the outputs of the first and second i comparison block address analysis programs are connected respectively to the first and second inputs of the AND element, the output of which is connected to the corresponding input of the encoder, the enable inputs 71462325 the first n of the second comparison circuit i-ro key to the clock input of the converter of the address generator program of the feeder. 29 9H 5 / / S I g " fie. 2