SU1116432A1 - Firmware processor with fast interruption tools - Google Patents

Abstract

MICRO-PROGRAMMER PROCESSOR WITH FAST INTERRUPTION MEANS, containing state register, interrupt unit, synchronization unit, data receiver unit, data transmitter and address blocks, address register, register unit, operation unit, switch, command register, pulse generator, micro-command register, microprogram unit the memory and the microcommand address generation unit, the control input, the first and second information inputs and the output of which are connected respectively to the output of the pulse former, the first address ones The output of the microinstructions register, the first output of the command register and the Address input of the microprogram memory block, the control input and output of which are connected respectively to the output of the pulse former and the input of the TRAILED "ATIETYO- and tehLISH microstar command control input, information input, first, second the third address inputs of the register block are connected respectively to the output of the pulse generator, the first output of the operating unit, the second output of the command register, the second address output of the microc register mand and the first output of the address register, the sync input, the information input and the second output of which are connected respectively to the output of the pulse generator, the first output of the operation unit and the information input of the address transmitters block, the first and second information (the operational inputs of the operation unit are connected to the outputs of the switch and the unit, respectively registers, and the second output of the operating unit is connected to the information inputs of the status register and the data transmitter unit and the third information input unit addressing the microcommand, control input, first, second, third and fourth: the information inputs of the switch are connected to the output of the pulse generator, the information output of the data receiver unit, the information output of the status register, the second output of the operating command register and the output of the microinstruction register constant ; information1; the ion input and the first output of the interrupt unit are connected to the control input-output of the processor, and the sync input, the control input and the second output of the interrupt unit are connected to responsibly to the output of the pulses is indicative of the output state register

Description

The SRI and the fourth information input of the microcommand address generation unit, the sync input of the status register and the control input of the operation unit are connected to the output of the pulse former, the input of the pulse former and connected to the operational output of the microinstruction register; the output of the block of data receivers, whose input is connected to the information input-output of the processor, the outputs of the block of transmitters d These and block transmitters of the address are connected respectively to the information and control inputs-outputs of the processor, and the control inputs of these blocks are connected to the output of the synchronization unit, the read / write control input of which is connected to the output of the pulse shaper, and the control input and synchronization unit output are connected to control input 16432

processor output, distinguished by the fact that, in order to improve speed, it contains an interrupt processing indication block, which includes two AND elements, two OR elements and a trigger, an information input, a synchronous input and an output of which are connected respectively to the outputs of the first and second elements OR and the fifth information input of the microcommand address generation unit, the sixth information input of which is connected to the output of an additional indicator of the status register, the first and second inputs of the first OR element are connected to the outputs of the co respectively, the first and second elements AND, the first inputs of which are connected to the output of the pulse driver and the inputs of the second element OR, and the second inputs of the first and second elements AND are connected respectively with the indicative output of the block of data receivers and the output of the register of microcommands.

one

The invention relates to computing and is intended for use in digital computers with firmware and an interrupt system.

A processor is known in which, along with the usual interrupt, which preserves the automatic saving of the instruction counter, the status register, and all the working registers of the processor in the stack, only the instruction counter and the status register are automatically stored on the stack for fast interrupts. interrupts C 1 1.

The disadvantage of this device is the low speed of executing an interrupt operation, due to the slow implementation of interrupt processing.

A processor is known that includes a common bus, common bus control blocks, interrupts, data receivers.

data transmitters, address transmitters, processing, registers, address register, status register, command register and control node j 2

The disadvantage of this device is hard hardware implementation of the control, limiting its functionality: it provides only slow software interrupt processing and slow response to interruption.

The closest technical solution to the invention is a processor with a firmware implementation of a control node and a vector interrupt system comprising a status register, an interrupt block, a synchronization block, a data receiver block, a data transmitter and address block, an address register, a register block, an operating block, a switch , command register, pulse shaper, micro-command register, microprogram memory block and block

the micro-command address vanes, the first and second information inputs and the output of which are connected respectively to the first address output of the micro-commands register, the first output of the command register and the address input of the microprogram memory block whose output is connected to the input of the micro-commands register, information input, first, second and third address the register block is connected respectively to the first output of the operational block, the second output of the command register, the second address output of the micro-command register and the first output of the address register, The information input and the second output of which are connected respectively to the first output of the operation unit and the information input of the address transmitters block, the first and second information inputs of the operation block are connected to the outputs of the switch and the register respectively, and the second output of the operation block is connected to the information inputs of the status register and the transmitter block data and the third information input of the microcommand address generation unit, the first to fourth information inputs of the switch are connected to Respectively with the information output of the data receiver unit, the information output of the status register, the second output of the operation unit and the output of the micro-command register constant, the information input and the first output of the interrupt unit are connected to the control input-output of the processor, and the control input and the second output of the breakout unit respectively, with the characteristic output of the register of status and the fourth information input of the block of formation of the address of the microcommand, the synchronous inputs of the register of the state, the block of interruptions, addresses and commands and the control inputs of the microprogram memory blocks, registers, micro-commands generation, the operational block, the switch are connected to the output of the pulse generator, whose input is connected to the operational input of the micro-commands register, the information input of the command register is connected to the information output of the data receiver block, the input which is connected

324

the information input-output of the processor, the outputs of the data transmitters block and the address transmitters block are connected respectively to the information and control inputs-outputs of the processor, and the control inputs of these blocks are connected to the output of the synchronization block whose read / write control input

with the output of the pulse generator, and the mode control input and the output of the synchronization unit are connected to the control input-output of the processor Z.

A disadvantage of the known device is the low speed of performing an interrupt operation due to the slow software implementation of the interrupt processing algorithm, as well as the need to save and restore at least two registers (command counter and state register), and

lengthens the time of saving and restoring the program state

The purpose of the invention is to increase processor speed by reducing the time to save and restore program state during interruptions by memorizing one register (state register) instead of several (from 2 to 8) and reducing interrupt processing time due to the possibility of firmware interrupt processing.

The goal is achieved

so that in the firmware processor. containing a status register, interrupt block, synchronization block, data receiver block, data transmitter and address block, register

addresses, block of registers, operational block, switch, command register, pulse shaper, micro-command register, microprogram memory block and address shaping block

microcommands, control input, the first and second information inputs and the output of which are connected respectively with the output of the pulse former, the first address output

the microinstructions register, the first output of the command register and the address input of the microprogram memory block, the control input and output of which are connected respectively to the output of the pulse former and the microcommand register input, the control input, the information input, the first, second and third address inputs of the register block are connected respectively with output of pulse generator by first output of operating unit, second output of command register, second address output of micro-command register and first output of address register, sync one, the information input and the second output of which are connected respectively to the output of the pulse driver, the first output of the operation unit and the information input of the address transmitters block, the first and second information inputs of the operation block are connected to the outputs of the switch and the register block, respectively, and the second output of the operation block is connected to information inputs the state register and the transmitter block of the data and the third information input of the microcommand address generation block that controls the input, first, The second, third, and fourth information inputs of the switch are connected respectively to the output of the pulse driver, the information output of the data receiver unit, the information output of the state register, the second output of the operation unit, and the output of the microinstruction register constant, the information input and the first output of the interrupt unit are connected to the control input-output of the processor, and the synchronous input, the control input and the second output of the interrupt unit are connected respectively to the output of the pulse former, indicative of output ohm of the status register and the fourth information input of the microcommand address generation unit; the sync input of the status register and the control input of the operation unit are connected to the output of the pulse generator, whose input is connected to the operational output of the microinstruction register; and information output unit of the data receivers, the input of which is connected to the information input-output of the processor, the outputs of the transmitter unit data and address transmitters block are connected respectively to the information and control inputs-outputs of the processor, and the control inputs of these blocks are connected to the output of the synchronization block, the read / write control input of which is connected to the output of the pulse shaper, and the control input and output of the block synchronization is connected to the control input-output of the processor, an interrupt processing indication block is inserted that includes two AND elements, two OR elements and a trigger, information | Input, synchronous input and output of which respectively, with the outputs of the first and second OR elements and the fifth information input of the microcommand adres.a block, the sixth information input of which is connected to the output of the additional status register, the first and second inputs of the first OR element are connected to the outputs of the first and second AND elements, respectively , the first inputs of which are connected to the output of the pulse former and the inputs of the second element OR, and the second inputs of the first and second elements AND are connected respectively to the indicative output of the block and data receivers and the output of the micro-instruction register constant. FIG. 1 is a block diagram of the firmware processor in FIG. 2-8 functional diagrams, respectively, of the micro-instruction address generation unit, interrupt unit, synchronization unit, operation unit, status register, register unit, pulse generator; in fig. 9 - time diagram of the operation of the interrupt unit; in fig. 10 is the same as the synchronization unit; in fig. 11 - the same, pulse maker, register blocks, micro-command address generation, operational block and state register 1; on Fig-table inputs-outputs of the transcoding unit shaper pulses. A microprogram processor with fast interrupt means contains a state register 1, an interrupt unit 2, a synchronization unit 3, a data receiver unit 4, a data transmitter unit 5, an address transmitter unit 6, an address register 7, a register unit 8, an operating unit 9, a switch 10 , command register 11 pulse driver 12, micro-command register 13, microprogram memory block 14, micro-command address generation block 15, interrupt processing indication block 16 containing the first 17 and second 18 AND elements, first 19 and second 20 OR elements, and trigger 21 The first and second information inputs and the output of the microcommand address generation unit 15 are connected to the first address output of the microcommand register 13, the first use of the command register 11, and the address input of the microprogram memory unit 14, respectively. The output of block 14 is connected to the input of the register 13 micro-commands. The information input, the first and the third address inputs of register block 8 are connected respectively to the first output of the operating unit 9, the second output of the register of 11 commands, the second address output of the register of 13 micro instructions and the first output of the register 7 of address. The information input and the second register address are connected respectively to the first output of the operation unit 9 and the information input of the address transmitters block. The first and second information inputs of the operational unit 9 are connected respectively with the outputs of the switch 10 and the unit 8 registers. The second output of the operational unit 9 is connected to the information HHbiM inputs of the state register 1, unit 5 of data transmitters and the third information input unit 15 of forming the microcommand address. The first and fourth information inputs of the switch 10 are connected respectively to the information output of the data receiver unit 4, the information output of the state register 1 by the second output of the operation unit, and the output of the register 13 microcommand constant. The information input and the first output of block 2 interrupts are connected to the control input-output 22 of the processor. The control input and the second output of the block 2 are connected respectively to the indicative output of the state register 1 and the fourth informational input. The block 15 forms the address of the microcommand. Synchronous inputs of the 1 state register, 2 interrupts, 7 address registers and 11 commands and the control inputs of blocks of 8 registers, 14 microprogram memory, 15 generation of microcommand addresses, 9 operational blocks, 10 switch, and the first inputs of elements 17, 18 AND block 16 is connected to the output of the driver 12 pulses. The second inputs of the first 17 and second 18 elements And are connected respectively with the indicative output of the block 4 data receivers and the output of the register constant 13 micro-commands. The inputs of the first 19 element OR are connected to the outputs of the first 17 and second 18 elements I. The first and second inputs of the second 20 element OR are connected respectively to the first inputs of elements 17 and 18 I. The information input, the synchronous input and the output of the trigger 21 are connected cootBeTCTBeHHo to the outputs of the first 19, the second 20 elements OR and the fifth information input of the microcommand address generation unit 15. The sixth information ion input of unit 15 is connected to the output of an additional feature of state register 1. The input of the driver 12 pulses connected to the operational output of the register 13 micro-commands. The information input of the command register 11 is connected to the information output of the data receiver unit 4, the input of which is connected to the information input-output 23 of the processor. The outputs of the data transmitter unit 5 and the address transmitter unit 6 are connected respectively to the information 23 and the control input 22 of the processor, and the control inputs of these blocks are connected to the output of the synchronization unit 3. The read / write control input of the synchronization unit 3 is connected to the output of the pulse former 12 pulses, and the mode control input and the output of the synchronization unit 3 are connected to the control input 22 of the processor. The micro-command address generation unit 15 contains a micro-command address register 24, an adder 25, switches 26-30, and NAND element 31. At the same time, the outputs of the switches 27 forming the high-order bits 15-4 of the micro-command addresses and the outputs of the switches 28 and 29 forming the lower 3-0 bits of the micro-command address are connected to the information input of the register of the micro-commands 24. The first to fourth information inputs of the switches 27-29 are connected respectively to the output of the adder 25, the first 32, the second 33, the third 34 information inputs of the block 15. The register 24 is connected to the first input of the adder 25 and the output 35 of the block 15. Fifth information inputs the switches 28 and 29 are connected to the outputs of the switches 26. The fifth, sixth and seventh information inputs of the switch 30 are connected respectively to the fourth 36, fifth 37 and sixth 38 information inputs of the unit 15. The first to fourth information inputs of the switch 30 are connected by bus 39 with operation result indicia arriving at the third 34 information input of unit 15. The inverse output of switch 30 is connected to the first input of the NAND element 31, the output of which is connected to the second control inputs of the switches 27 and the third control inputs of the switches 28 and 29. The first and second control inputs 40 of the switches 26, the first control inputs 4t of the switches 27, the first 42 and second 43 control inputs of the switches 28 and 29, gating 44, the first 45, the second 46 and the third 47 control inputs of the switch 30, the second 48 input of the 31 NAND element 31, the control 49 input of the register 24 of micro-command addresses are connected to the control input 50 of the unit 15. The first-fourth information inputs of the switches 26 are set to the corresponding bits of all four tetra of data 51, arriving at the third 34 information input of the block 15 in such a way that there is a possibility of thoracic branching according to the result of the analysis of each tetrad. So, for example, the first to fourth information inputs of the switch 26, the output of which is connected to the fifth address input of the switch 29, which forms the younger digit of the address, respectively, bits 12, 8, 4, O of the data bus are input to the third 34 information input block 15. Secondly, the input of the adder 25 and the gate gateways of the switches 26-29 are connected to the internal bus B Logical zero, the third input is the sum of the torus 25 connected to the internal bus C Logical unit. In this example of technical implementation, the information and control inputs of the processor are combined into a common bus, which is a unified system of communications and signals between the processors, the main memory and external devices. The shared bus includes address, data and control lines. Address lines are used to transmit the address of a memory location or the address of an external device register. Data lines are used to transfer data between the setter and the agent. The master clock sync signal (CSP) is used to indicate to the contractor that the address and control information is set on a common bus. Signal Synchronization execute-. L (SHI) is the response of the executor to the SHS signal. Signals A Transmission Request Transmission Request (7-4) is used by peripherals to request control of a common bus. These signals are transmitted on four lines. Each line has its own priority level, and RFP 07 has the highest priority. Signals Allowing the TLR (7-4) to be transmitted is the processor's response to the ZP signals. The Sample Validation (PVB) signal is issued by the device that requested the common bus and received permission to use the bus. The Zanto (ZAN) signal determines that the bus is occupied by the current setpoint device. The Interrupt Signal (PREP) is triggered by the knob in order for the processor to switch to the program or firmware for processing the interrupt for this external device. The Signal Prep (POD) signal is transmitted to all devices from the processor when the Start button is pressed or when the Reset command is executed. The control lines L1, RN are used to transmit the operation code from the setter to the executor. The lines ZP (7-4), RP (7-4), PVB, PRYR, PODG unidirectional. The remaining lines are bidirectional. The high signal level of the TL (7-4) on the common bus is operational. The operating level of the remaining common bus signals is low. Interrupt unit 2 contains inverter receivers 52-58, triggers 59-62, element 63 W-NOT, delay elements 64, 65, comparison node 66, AND-NOT elements 67-70, IPI element 71, transmitter inverters 72-76 , element-transmitter 77 IS-NOT, triggers 78, 79, one-shot 80. At the same time, the inputs of inverter receivers 52-58 are connected respectively to information input 81 of block 2 interrupts by lines 82 ЗП4, 83 ЗП5, 84 ПП6, 85 ЗП7, 86 SUBG, 87 PVB, 88 PREP. The outputs of inverter receivers 52-55 are connected respectively to the information inputs of the flip-flops 59-62, the gate inputs KOTOpbtx are connected to the syncro Odom unit 89 line 2 90 Phase 1. The outputs of flip-flops 59-62 are connected respectively to the first to fourth comparison input node 66, the fifth to seventh inputs of which are connected to a control input 9t unit 2 interrupts. The first to fourth outputs of the comparison node are connected respectively 20 but with the first inputs of the elements 67-70 AND-NOT and the inputs of the element 71 OR whose output is connected to the information input of the trigger 78 and the second output 36 of the interrupt unit 2. The inputs of the one-shot 80 and the delay element 65, as well as the second inputs of the elements 67-70, are NOT connected to the direct output of the trigger 78, the gate input of which is connected by the line 92 Interrupt analysis to the synchronous input 89 of the interrupt unit 2. The outputs of elements 67-70 AND-NOT are connected respectively to the inputs of inverter-transmitters 72-75, the outputs of which are connected respectively by lines 93 93 РП4, 94 РП5, 95 РБб, 96 РП7 with the first code 97 of the block 2 interrupt. The outputs of the inverter receivers 56, 57 are connected to the inputs of the IPI-NE element 63, the output of which is connected to the installation input O of the trigger 78. The output of the inverter receiver 58 is connected to the input of the delay element 64, the output of which is connected to the inverter input of the transmitter 76, the output of which connected by line 98 SHI with the first output 97 of block 2 interrupt. The output of the delay element 65 is connected to the first input of the transmitter element 77 IS-NOT, the second input of which is connected to the output of the one-shot 80. The output of the element transmitter 77 IS-NOT is connected by the line 99 of the PVB to the first output 97 of the interrupt unit 2. The inverse output of the trigger 78 is connected to the gate input of the trigger 79, the installation input to 1 of which is connected to the output of the inverter receiver 57. The installation inputs to the O flip-flops 59-62 are connected to the code of the trigger 79, the information input to which is connected to the internal bus B Logical zero.

Synchronization unit 3 contains triggers of 100 readings (PST), 101 records (TMP), 102 records of bytes (TMPB), 103 Zanto then (TZAN), 104 master synchronization (TSHZ), 105 errors

(TOSH), inverter-receivers 106, 107, receiver 108, elements 109-112 OR, delay elements 113-115, inverter-transmitters 116, 117, elements 118-120 AND, one-shot 121, elements 122-126 AND-NOT, 127-128 inverters. In this case, the installation inputs in 1 trig. GERA 100-102 are connected respectively by lines 129 Read, 130 Write, 131 Write byte to input 132 of read / write control unit 3. Information inputs of the trigger 100-103 are connected to the internal bus B Logical zero, and the gate inputs of these triggers are connected to the first input the element 112 OR and the output of the inverter 106, the input of which is connected by line 133 Preparation to the block mode mode control input 134. The output of the delay element 115 is connected to the installation inputs O of the flip-flops 100-103, the installation input 1 of the last of which is connected to the output of the element 122 AND - E, the first input of which is connected to the first inputs of elements 120 AND, 126 AND-NOT and the output of element 109 OR, the first to third inputs of which are connected respectively to the direct outputs of the flip-flops 100, 101 and 102. The second input of element 122 AND-NOT is connected line 135 Phase 2 with input 132 control reading / writing unit 3, and the third input element 122 AND-NOT connected to the output of the receiver 108, whose input is connected by line 136 ILI to input 134 controlling the mode of unit 3, which is connected by line 137 SHI to inverter input -Receiver 1.07, the output of which is connected to the first inputs of the elements Commodity 118, 119 And with the information input of the trigger 105. The direct output of the trigger 103 is connected to the first inputs of the elements 123-125 AND-NOT, the inputs of the delay element 113 and the inverter 116, the output of which is connected by the line 138 ZAN with the output 139 of block 3. The inverted output of the trigger 103 is connected to the input of the inverter 127, the output of which is connected by a line 140 Address output to the output 139 of block 3, the first input of the element 111 OR is connected by a line 141 Read with a pause to the input 132 of the block 3. The second input of the element 111 IL is connected to the trigger output 102 and ne input of element 110 OR, the second input of which It is connected to the output of the trigger 101. The output of element 110 OR is connected to the second inputs of elements 123 and 125 AND-NOT, the output of the last of which is connected to the input of the inverter 128, the output of which is connected by a line 142 of the output of the element 123 AND - is NOT connected by line 143 U 1 to output 139 of block 3. Output of element 111 OR is connected to the second input of element 124 AND IS NOT whose output is connected by line 144 O to output of .139 of block 3. The output of delay element 113 is connected to the second input of element 119 And, the output of which is connected to the trigger input of the trigger 104, info The input input is connected to the internal bus C Logical unit, and the direct output to the second input of element 118 I, the installation input to 1 flip-flop 105, the first input of one-vibrator 121 and the input of inverter 117, the output of which is connected by line 145 of CX3 to output 139 of unit 3. Output the one-shot 121 is connected to the gate input of the trigger 105, the inverse output of which is connected to the second input of the element 120 AND, the output of which is connected to the second input of the element 112 OR, the third input of which is connected to the output of the element 118 I. The output of the element 112 OR is connected to by entrance The delay element 114, the output of which is connected to the second input of the element 126 AND-NOT, the output of which is connected to the input of the installation on the O flip-flop 104, the second input of the one-shot 121 and the input of the element 115 of the delay. : Operational block 9 contains a switch 146, an arithmetic logic unit 147, a shifter 148, a data register 149, an OR element 150, an EXCLUSIVE OR element 151, an overlap trigger 152, 153 zero, 154 overflow, 155 hyphenations. The first information input of the switch 146 is connected to the first information input 156 of block 9, the second input of the switch 146 is connected by bus 157 to the second information input 158 of block 9. The first information input of arithmetic-logic node 147 is connected by bus 159 to the second information input 158 of block 9. The output of the switch 146 is connected by bus 160 to the second information input of the arithmetic logic unit 147, the first output of which is connected to the information input of the shifter 148, the first output of which is connected to the input of the data register 149, the input element This 150 OR and the first output 161 of the block 9. The second output of the arithmetic logic unit 147, through which the lis transfer of the most senior of the fifteenth bit of the result enters, is connected to the information input of the transfer trigger 155 and the first input of the 151 element EXCLUSIVE OR, the second input of which is connected with the third output of the arithmetic unit 147, which receives the transfer from the previous (fourteenth) bit of the result. Information inputs of the trigger 152-154 are connected respectively to the second output of the shifter 148, the output of the element 150 OR, the output of the element 151 EXCLUSIVE OR. The output of data register 149 is connected by bus 51 to the second output 34 of block 9. The outputs of flip-flops 152 characters, 153 zero, zero overflow 154, transfer 155 are connected by bus 39 to the second output 34 of block 9. Control inputs of data register 149, shifter 148, arithmetic logic node 147, switch 146, and triggers 152-155 are connected, respectively, by lines 162-166 to control input 167 of operation unit 9. State register 1 contains priority triggers 168, 169 features and 170 additional features of state register 1, switches 171 and Element 172 OR, First Element Entry These 172 OR and control inputs of the flip-flops 168 and 170 are connected by a line 173 PCB loading with a state-of-the-art 174 state register 1. The information inputs of the flip-flops 168, 170. as well as the first information inputs of the switches 171 are connected by bus 51 to the information input 34 of the state register 1. The second input of the element 172 OR is connected by a line 175 Installation of signs with the synchronous input 174 of the register 1. The output of the element 172 OR is connected to the control inputs of the trigger 169, the information inputs of which are connected to the outputs of the switches 171, the control inputs which are connected by the line 176 to the synchronous input. 174 register 1 The second information / inputs of the switches 171 are connected by bus 39 to input 34 of register 1. The outputs of the trigger 168170 are connected to the output 177 of register 1. The outputs of the trigger 168 are also connected to the indicative output 91 of register 1, and the output of the trigger 170 is connected With the release of 38 additional feature of the register 1.

Block 8 registers contains switches 178-180, node 181 of the first registers, node 182 of the second registers, the first 183 and second 184 registers. The first address inputs of switches 178 and 179 are connected to the first 185 address input of block 8, the second address inputs of switches 178 and 179 are connected respectively by lines 186 and 187 to the second 188 address input of block 8, the third address inputs of switches 178 and 179 are connected to the third 189 by the address input of block 8. The control inputs of the switches 178 and 179 are connected, respectively, by lines 190 and 191 to the control input of 192 of block 8. The output of the switch 178 is connected to the address input of the first register node 181 and the first address input of the switch 180; the course of which is connected to the output of the switch 179. The output of the switch 180 is connected to the address input of the node 182 of the second registers. The information inputs of the nodes 181 first registers and 182 second registers are connected to the information input

161 blocks 8. VTGPP RbtfinnKH V4.TTOR 18-1

the first registers and 182 second registers are connected by a line 193 Sample to the control input 192 of block 8, the entry entry of the nodes 181 of the first registers and 182 second registers are connected by line 194 to the control input 192 of block 8, which is also connected by a line 195 to the gate inputs of the first 183 and the second 184 registers and also the line 196 with the control input of the switch 180. The outputs of the nodes 181 and 182 of the second registers are connected respectively to the information inputs of the first 183 and second 184 registers, the outputs of which are connected respectively by buses 159 and 157 to the output 158 blocks ka 8 registers.

Shaper 12 pulses contains a generator 197 clock signals, decoders 198-200, element 201 OR NOT, elements 202-205 AND-НЁ, elements 206-210 And, transcoding node 211. The first output of generator 197 clock signals is connected by a line 90 Phase 1 to the first inputs elements 201 OR-NOT, 203-205 AND-NOT, 206208 Neither the output 212 of the driver 12 via the bus 89, which is fed to the synchronous input of the block 2 interrupt. The second output of the generator 197 clock signals is connected by a line 135 Phase 2 through the bus 132 to the output 212 of the driver 12 pulses. The outputs of the elements 203-205 AND-NOT are connected respectively by lines 129-131, connected to the bus 132 with the output 212 of the driver 12. The second input of the element 201 OR-NOT is connected by a line Phase 3 with the third output of the generator 197 clock signals, the fourth output of which is connected by the line 195 Phase 4 is connected via bus 192 with output 212 of generator 12. Fifth generator output 197 of clock signals is connected by line Phase 5 with the first inputs of elements 202, 209 and 210. Secondary. The swarm input element 202 AND-NOT connected by line 213 to the input 214 of the generator 12. The output of the element 202 AND-NOT connected by line 194 through the bus 192 to the output 212 of the driver 12. The sixth output of the generator 197 clock signals connected by line 49 Phase 6 through the bus 50 to the output 212 driver 12. The input of the decoder 198 is connected by a line 215 to the input 214 of the driver 12. The first to fourth and fifth outputs of the decoder 198 are connected respectively to the second inputs of elements 206, 207 AND 203-205 AND The sixth output of the decoder 198 is connected by line 141 Reading from pause through the bus 132 with the output of 212 formate 12. The seventh output of the generator 197 sync signals and the output of the element 201 IHR-NOT are connected respectively by lines 196 Phase 7 and 193 Sampling through the bus 192 with the output 212 of the former 12. The output of the element 206 And connected by the line 216 with the output 212 of the former 12. This line enters signal entry on the synchronous register of the address 7. The output of element 207 AND is connected by a line 16Z.Hepe3 bus 167 with an output 212 of the former 12. The first to fourth inputs of the transcoding unit 211 are connected respectively by lines 21 and 220 to the input of the former 12. First and eighth outputs of the transcoding node 211 are connected respectively by lines 41, 48 , 44, 43, 42, 45, 46, 47 ,. assembled into bus 50, with output 212 of driver 12. The control signals in this example implementation on output bus lines 40, 50, 163, 164, 165 of output bus 167 and 190, 191 of output bus 192 come from the corresponding fields of the operational part of the register 13 micro-commands received at the input of the 214 driver 12 pulses. The input of the decoder 199 is connected by line 221 to the input 214 of the driver 12. The first to third outputs of the decoder 199 are connected respectively to the second inputs of elements 208, 209, 210 And, the output of the first of which is connected by line 166 through the bus 167 to the output 212 of the driver 12. The second output of the decoder 199. And the outputs of the elements 209, 210 and And are connected respectively by lines 176, 173, 175, collected in the bus 174 with the output 212 of the former 12. The fourth output of the decoder 199 is connected by a line 92 through the bus 89 with the outlet 212 of the former 12. The fifth output of the decoder 199 is connected by line 222 to the output 212 E) Warner 12, arriving at the synchronous input of the register of 8 commands. The input of the decoder 200 is connected by bus 22 to the input 214 and output 212 of the former 12. The first and second outputs of the decoder 200 are connected by lines 224 respectively. Receiving the indicative output of the block 4 of data receivers and 225 Receiving constants assembled into the bus 226 with the output 212 generator 12. Control signals along lines 224 and 225, respectively, arrive at the first inputs of elements 17 and 18 I. Control signals via bus 223 arrive at the control input of switch 10. Chip 1515 can be used for the technical implementation of the recoding node 211 that The blitz of the inputs-outputs of which is shown in FIG. 12. The microprocessor processor works in the following way. At the current time point, the next instruction is read from the information input 23-output of the processor from the main memory, which through the data receiver block 4 enters the command register 11 and then into the micro-instruction address generation unit 15 to form the initial micro-instruction address of the command being executed. According to the address formed in block 15 from block 14 of firmware memory to register 13 of micro-instructions, a micro-command is read. Pulse generator 12 decrypts the operational part of the microcommand, and at its outputs there appear control signals affecting the operation of the operating unit 9 and other blocks and processor circuits. The first address part of the microcommand from the first address output of the register 13 microcommand enters the block 15 of the formation of the address of the microcommand to determine the address of the next microcommand. The second address part of the microcommand from the second address output of the register 13 microcommands enters the block 8 of registers to determine the number of the register involved in the operation. Block 8 of registers contains two nodes of 16 registers. At each node, eight RO-P7 universal registers are both firmware and software accessible and include a command counter (P7) and a stack pointer (P6). The remaining eight working registers (P10-P17) are available only by firmware. The contents of the same-name registers of both nodes are the same. Register P12 is used to store the address of the interrupt vector. In block 8 of the registers, the operands are processed by the operation block 9. The register address is set by firmware from one of three directions:, the register of 11 commands, the second address part of the register 13 of microinstructions and the four best bits of the register 7 address. The address of the next command is calculated in operation block 9 and sent to the command counter, register P7 of register block 8. When requesting the next command, the command address is read out from the register P7 of the register block 8 and through the operation block 9, the address register 7, the block of address transmitters 6 and the control input / output processor 22 enters the main memory. Synchronizer 3 up19

Equalizes the exchange of information with the main memory and external devices controlled by control signals from the driver 12 pulses

Interrupt block 2 selects the highest priority interrupt request from external devices through control processor 22 I / O, compares it with the priority of the executing program coming from the indicative output of state register 1, and, if the priority of the received gapros is higher, issues signal for interruption in block 15 of the formation of the address of micro-commands. After each command is executed, the micro-command address generation unit 15 according to the control signal from the pulse former .12 analyzes the presence of this interrupt signal. If there is no interrupt signal, a transition is made to the next command. Otherwise, an interrupt is performed, which is as follows.

1. External device transmits

to the processor, the address of the interrupt vector, which through information 23 input-output of the processor, block 4 of data receivers, switch 10, operational block 9 enters the register P12 of block 8 of registers. In this case, the indicative bit of the address of the interrupt vector is stored on the trigger 21 of the block 16 of the interrupt processing flag. The interrupt vector consists of two consecutive words — the address of the beginning of the program or interrupt service firmware and the value of the program status register.

2. The microprogram performs the operation of storing the state word from state register 1 via switch 10, operation unit 9, data transmitter unit 5, information processor input-output 23 to a special area of the main memory — stack. For addressing the stack is the register P6 (stack pointer) block 8 registers. When you push one word into the stack, the value of the pointer decreases by 2, and when you select a word from a bet, the value of the pointer increases by 2.

3. In block 15 of the formation of the address of micro-commands, the output value of the trigger 21 of the block 16 is analyzed at 1643220

interrupt service mark. this output means that the termination must be processed by the firmware, and O - by software or 5 firmware, depending on

the output values of the additional feature of the state register 1. In accordance with this, with a single value of the trigger output 21 block 16

fO the contents of the register P12 of the register block 8 through the operational block 9. enters the block 15 of the address of the microinstructions, thus initiating the microsubprogram processing

15 interrupt, the address of the first microcommand of which is given by the address of the interrupt vector.

With a zero value of the trigger output 21 of the block 16 processing feature

20, the interrupt content of the register P12 of the register block 8 in the operational block 9 is increased by 2 and this modified address through the address register 7, the block of 6 address transmitters,

The 25 control modules 22 processor output is sent to the main memory. The new processor state word via the information 23 read from this address from the main memory.

30 processor input / output, data receiving unit 4, switch 10, operation unit 9, recording into state register 1 under control of signals from driver 12 pulses.

4. In block 15 of the formation of the address of micro-instructions, the output of an additional feature of the state register 1 is analyzed. 1 on this output means that the interrupt must be processed. microprogramme.mno, and O programmatically. In accordance with this, with a single value of the output of an additional feature of the state register 1, the contents of register P12 of the block 8 registers through the operational block 9, the address register 7, the block of transmitters 6 of the address, controlling 22. processor input / output is sent to the smooth memory. At this address from

0, the main memory is read the first word of the interrupt vector and through; information 23 input-output processes, copy, block 4 data receivers,

the switch 10 and the operational unit 9 5 enters the formation unit 15

addresses of microinstructions, thus initiating an interrupt-processing microsubprogram. At zero value 21, the output of the additional indicator of the status register 1 is performed; the address of the next command is saved from the register 7 of the register 8 block through the operational block 9, the data sensor 5 block, 23 information processor input-output to the stack. Thereafter, the address of the interrupt vector from the register P12 of the register block 8 via the operation block 9, the address register 7, the address transmitter block 6, the control 22 input-output processor is sent to the main memory. At this address, the first word of the interrupt vector, which in this case is the address of the interrupt processing subroutine, is read from the main memory and is written to the command counter (register P7 of the register block 8) via the information input processor 23, the data receiver block 4, the switch 10 and the operational block 9. 5. At the address read from the register P7 of the register 8 block from the main memory, the first command of the interrupt processing subprogram is retrieved, thus initiating this subprogram. The subroutine processing routine may in turn be interrupted by a request from a device with a higher priority. If such an interruption occurs, the command counter and state register 1 of the current interrupt processing routine are automatically (as for the case of interrupt processing) entered into the stack, and initiated by the interrupt processing program of the new device. Such accumulation of priority interrupts can continue to the level determined by the amount of memory allocated for the processor stack by the programmer. With the firmware interrupt, such an accumulation of interrupts does not occur and the interrupt is completed as quickly as possible. 6.After the end of the interrupt processing program, the state of the interrupted wpb program is restored using the Return From Interrupt command, which retrieves the two upper words from the stack, and loads them back into the command counter and into the state register 1. In the case of firmware interrupt, the firmware 3232 is implemented to extract from the stack and load only one word — state register 1. In the process of executing the commands of internal interrupts TRAP, EMT, VRT, JOT, the address of the interrupt vector fixed for each of these commands is sent to the register P12 of the register 8 block from the output of the register 13 microcommands constant through the switch 10 and the operational block 9. At the same time the output of the microconstruction register 13 constant is also sent to the interrupt processing indication (O or 1) to the flip-flop 21 of the interrupt processing indication unit 16 via the elements 18 AND, 20 OR under the control of the signal arriving at the first input of the element 18 AND from the driver 12 pulses. After that, the operation of the microprocessor processor when processing internal interrupt commands is performed according to clauses 2-6. It should be noted that during interrupt microprocessing there is no need to memorize and then restarting software-accessible universal registers RO-P7, since you can use only internal firmware P10-P17 as operating registers, which also significantly reduces interrupt processing time. Thus, the proposed firmware processor allows interrupt processing in three ways. A microprogram with a single value of the trigger output 21 of block 16 of the interrupt processing flag. In this case, the address of the interrupt vector is the address of the interrupt processing firmware. This interrupt handling method is the fastest. The microprogram at zero output value of trigger block 21 of 16 and a single value of the output of an additional feature of state register 1. The address of the interrupt processing firmware is the first word of the interrupt vector read from the main memory at the address of the interrupt vector. Software at zero output of the trigger 21 of block 16 of the interrupt processing flag and zero output of the additional sign of the state register 1. In this case, the address of the interrupt handler program is the first word of the interrupt vector read from the main memory at the interrupt vector address. This method is the slowest and coincides with the interrupt processing method in the prototype device. The sign of the interrupt processing is set by the hardware in each external device (at its address of the interrupt vector) or written by the programmer in the interrupt vector word of each device. B in accordance with the specified principle of operation - the proposed device and shown in FIG. 2-8 block diagrams of microcommand address generation blocks 15, 2 interrupts, 3 synchronizations, 9 operational blocks, state register 1, block 8 registers, 12 pulses, these blocks work as follows. In block 15, the formation of the address of micro-commands under control of the signal at the control input 50 will receive the address to the register 24 of the address of the micro-commands through the switch 27-29 from the adder 25 (when performing the micro-command with natural addressing, which corresponds to the code 00 on the control inputs of the switches 27 and code 000 on the control inputs of the switches 28 and 29), from the first 32 information inputs (when the microcommand of unconditional passage through the contents of the first address output of the register 13 microcommands is executed, which corresponds to the code 01 on the control switches 27 and code 001 on the control inputs of switches 28 and -29), from the second 33 information inputs (when .commanding the microcommand group branching from the contents of the register 11 is a coma, which corresponds to code 10 on the control inputs of the switches 27 and code 010 on the control switches 28 and 29), from the third information input 34 (when executing the microcommands of the grouping branch on the contents of the operation block 9, which corresponds to code 11 on the control inputs of the switches 27, and code 011 on the control inputs of the switches 28 and 29). When a group command microcommand is executed by the contents of one of the tetrads of the operating unit, 9 which corresponds to code 100 on the control inputs of the switches 28 and 29, one of the tetrads of the operating unit 9 enters the four lower-order bits of the microcommands via the switches 26, 27, 28 The tetrade number is indicated by the code on the control inputs of the switches 26. The corresponding bits of the first address output of the register 13 microcommands from the input 32 of the block 15 arrive at the high bits of the register 24 microcommand addresses via the switches 27. mmutators 26, 27 are described by the following logical formula (2 Vz 2%), respectively, the first, fourth information inputs of these switches h ("2, respectively, the first and second control inputs of these switches {Q is the output of these switchesJ f is the gate input of these switches. The operation of switches 28-30 is described by the following logical formula s.). where C is the gate input of these switches}, respectively, the first, eighth information inputs of these switches; - - respectively, the first control inputs of these switches. When performing a microcommand of a transition, the sign of which is the appearance of a low level signal at the gate input of the commutator 30, a low level signal corresponding to O, the first and second control signals come from the control input 50 of the block 15 from the control inputs 50 of the switch 15 the inputs of switches 28 and 2.9 ignals corresponding to code 00 to the second input of element 31 NANDA high-level ignals corresponding to code 1. If the condition is met (i.e., signal 1 on the indicated information input of switch 30) on the first input The ga of the NAND element from the inverted output of the switch 30 receives the signal O. The second control inputs of the switches 27 and the third control inputs of the switches 28 and 29 from the output of the element 31 NID signal 1, i.e. when the condition is fulfilled, the control inputs of the switches 27 receive the code 01, and the control inputs of the switches 28 and 29 receive the code 001, which corresponds to the transfer to. the input of the register 24 of the address code from the first 32 information input of the block 15. If the condition is not met (the signal O is present at the indicated information input of the switch 30) through the switch 30 and the N-element 31 to the second control inputs of the switches 27 and to the third directing switches 28 and 29, the signal O is received. Thus, if the condition is not fulfilled in the microcommand of the conditional transition, the control inputs of the switches 27 receive the code 00, and the control inputs of the switches 28 and 29 receive the code 000, which corresponds to the transmission of the address 24 of the address mic okomand via the switches 27, 28 and 29 {soda) extensible adder 25, ie when nevtolnenii conditions are satisfied is the following by microinstruction queue. The adder 25 performs the addition of the current address of the microcommand that is supplied to its first input with the unit code from the internal buses of the adder to its second and third inputs. When other types of microinstructions are executed, due to the presence of a high level signal at the gate input of switch 30, the first input of element 31 NAND from signal 1 of the inverse output of switch 30 allows the control signal passing to the second input of element 31 AND NAND. In block 16, the interrupt processing, controlled by signals on lines 224, 225, receives and stores the interrupt processing attribute received from the acknowledged output of the data receiver unit 4 through AND 17, OR 19 element to trigger information input 21 during reception addresses of the interrupt vector from the external device or from the output of the register register 13 microinstructions through element 18 AND, element 19 OR to the information input of the trigger 21 during the execution of the internal interrupt commands. In the latter case, the low bit of the constant is a sign. In both cases, the memorization of the pre-run processing attribute on the trigger 21 is performed under the influence of control signals on lines 224 or 225 arriving at the control input of the trigger 21 through the OR element 20. Interrupt block 2 organizes the capture of a shared bus in order to interrupt the processor. Interrupt requests from external devices ZP4-ZP7, arriving respectively on lines 82-85 from the second control input 81 of block 2 interrupts via inverter receivers 52-55, are memorized on triggers 59-62 by a strobe signal received on line 90 Phase 1. Comparison node 66 selects the highest priority interrupt request from all requests received at its first to fourth inputs, compares it with the priority of the executing program arriving at its fifth to seventh inputs from control input 91 of block 2 interrupts and if priority by tupivshego vppe request, generates at its output corresponding to a high level signal which via OR element 71 is fed to the data input of flip-flop 78 and the output 36 to the second unit 2 interrupts the processor as an interrupt signal. When a control signal arrives via interrupt analysis line 92 (which is generated after each command is executed) from the synchronous input 89 of interrupt unit 2 to the gate input of the trigger 78, the latter is set to one, allowing the interrupt request issued by the comparison unit 66 to be output through one of the corresponding elements 67 -69 or 70 NAND and one of the corresponding inverter-transmitters 72-74 or 75 to the first output 97 of block 2 interrupts as one of the FP4 signals via line 93 or FP5 via line 94, or FPG via line 95 or FP7 via line96. So, for example, if at the same time on the 59-62 flip-flops all requests on the LAP are closed, then ZPA-ZP7 is terminated, then the output 97 of the interrupt 2 unit will receive only the FP7 signal on the line 96 through the fourth output of the comparison node 66, element 70 AND-NOT inverter transmitter 75. Due to the absence of a PVB signal (high, the signal level on line 87), a low level signal is sent through the inverter receiver 57 to the input of the installation in 1 flip-flop 79, as a result of which from its output to the inputs of the NONKI terminal in O flip-flops 59, 60-62, a high level signal is received that does not cause these rigger in G. In accordance with the algorithm of the interface bus overall external device that sent signal CP, recognizes the rising edge of its line RP RP signal vschaet signal PVB removes CP signal and waits for removal of the RP signal. In block 2, the interruption of a low-level PVB signal on line 87 results in a high-level signal at the input of a setup in 1 flip-flop 79 and a low-level signal at the input of a setup in O flip-flop 78, causing the latter to be set to O, prohibiting Vspaschu signals FP4-FP7. Setting the trigger 78 to O also causes the rising edge of the signal from the inverted output of the trigger 78 to the gate input of the trigger 79, which causes the latter to be set to O and to the low level signal from the output of three heights 79 to the inputs of the installation to the O trigger 59-62, as a result, these triggers are set to O. After removing the TL signal, the external device sets the address of the interrupt vector on the data lines, the Interrupt signal, removes the PVB signal. The removal of the PVB signal on line 87 causes the trigger 79 to switch to 1 and the input to the installation of high level triggers 59, 60-62, which allows the reception of successive requests for these triggers. After the occurrence of the signal Interrupt on line 88 after time 1, detected by delay element 64, through inverter-sensor 76 to output 97 on line 98, you receive 228 a CXI signal. Then the external device that caused the interrupt, identifying the SHI signal, removes the Interrupt signal. The considered cycle of operation of interrupt block 2 is repeated when the next interrupt request is received. The trigger 78 is set to the state O also when a signal appears, an initial reset, while the signal level is low. Preparation on line 86 through the inverter receiver 56, element 63 OR NOT is fed to the input of the installation in О trigger 78. The one-vibrator 80, element 65 delays and the 77-AND-NE transmitter element cause a PVB signal in case the external device does not transmit a PVB signal within 10 µs after the output of one of the FP4-FP6 or FP7 signals. After the output of one of these signals from the direct output of the trigger 78 to the inputs of the delay element 65 and the one-shot 80, a high-level signal arrives, triggering the one-shot 80, the output of which produces a negative pulse of 10 microseconds. The delay element 65 eliminates the loss of the PVB signal from the element 77 AND IS in the time interval between the appearance of a high level signal at the input of the one-shot 80 and a low level signal at its output. Thus, after one of the TL signals, through the delay element 65, a high level signal appears at the first input of the transmitter element 77. At the second input of the transmitter element 77, a high level signal is detected after 10 μs from the output of the one-shot 80. As a result, after 10 μs after the detection of one of the signals FP4-FP6 or FP7, a signal is generated on line 99 from the output of the transmitter element 77 IS-NOT Low PVB, If the external device enters the PVB signal on line 87 during a time less than 10 µs after one of the FP4-FP6 or FP7 signals, the trigger 78 when a PFB signal appears is set to 0. A low signal level from its direct output resets the one-shot 80 and through element 65 post delay It goes to the first input of the transmitter element 77, so that the PVB signal from its output is not visible. 29 The operation of the comparison node 66 is described by the following logical formulas:,; gtsz% bd, yb,); i where b - bf. accordingly, the first to eighth information inputs of the node 66, respectively, the first and fourth outputs of the node 6; The comparison node 66 can be performed on the chip K556 PT4. The synchronization unit 3 controls the I / O operations on the common bus not in accordance with the requirements imposed on the common bus interface. Triggers 100-102 respectively remember the types of I / O operations: Read, Write and Write bytes, the low-level signals of which are received according to lines 129-131 from input 132 of unit 3 to the inputs of the installation into 1 trigger 100-102. When one of the triggers 100, 101 or 102 is installed in G, the first input of element 122 NAND is from the output of element 109 OR a high level signal is received, which causes the appearance of a signal of no level at the output of element 122 NID without signal ZAN (high signal on line 136 and the appearance of a high-level strobe signal on phase 135 on line 135, which triggers 103 TZAN to trigger 1. In the initial state, triggers 100-103 are set to O with a leading edge of the Prepare signal coming in on line 133 through inverter receiver 106 These triggers are used by the processor, a symptom of which is to set the TZAN trigger 103 to 1, to allow for the common address bus (due to high signal level output of the line 140) given during the Record and Byte Record operations. (due to the high signal strength of data output 5

on line 1A2), operation code on control line 143 У1 and 144 У О, encoded on elements 110, 111

second through the elements 12Q AND 112 OR, 114 delays arrive at the second input of element 126 NAND, the first 2 OR. The codes on the lines 143, 144 In tl-03 designate the following operations: 00 - Read, 01 - Read with pause, 10 - Write, 11 - Write byte. Installing 1 TZAN trigger 103 causes the ZAN signal on line 138 and setting TSHZ trigger 1 to 1 after a time 2 determined by delay element 113 when there is no SHI signal on line 137, i.e. with a high signal level on this line. Setting TSXZ trigger 104 to 1 causes a CXS signal (low level) to appear on line 145 through inverter 117 and triggers a one-shot 121, the output of which produces a negative impulse to the gate input of trigger 105. If the signal is a SHI (low level on line 137 ) wils less than 20 mks, high level of signal from inverter 107 through elements 118 and 112, OR, 114 delays go to the second input of element 126 AND-NOT, on the first input of which at this time there is also a high level signal. The low level of the signal from the output of element 126 AND-NOT resets the TSHZ trigger 104 and the one-shot 121. The low signal level from the direct output of the TSHZ trigger 104 arrives at the installation input to 1 TOSH trigger 105, confirming its single state, which is a sign of no error . After time i ,, determined by the element 115 C-delays, after resetting the TSHZ trigger 104, a low signal level from the output of the delay element 115 arrives at the inputs of the installation in O of the flip-flops 100-103, set the latter to O. If the signal level of the SHI is low 137 does not appear within 20 µs, the leading edge of the signal appears at the gate input of the TOSH trigger 105 from the output of the one-shot 121 after 20 µs after setting 1 of the TSHZ trigger 104. Since at the same time the low level of the signal arrives at the information input of the trigger 105 from the output of the inverter 107, the trigger 105 is set to O, a high level error signal is output from its inverse output, at which time there is a high level signal from the output of the OR element 109. The low level of the signal from the output of element 126 AND-NOT is fed to the input of the installation in O of the TSHZ trigger 104, it is set to O. The low level of the signal from the direct output of the trigger 104 is fed to the input of the installation in 1 of the TOSH trigger 105, set to 1 in this at the inverse of the output of the trigger 105 appears a low level signal, which is a sign of no error. When a low level signal appears, the preparation on line 133, which through the inverter 106, elements 112. OR, 114 delays, 126 AND-NOT, goes to the input of the installation in O of the trigger 104, the latter is set to O.

Operational unit 9, depending on the microcommand being executed, under the influence of control signals at control input 167 can perform arithmetic logic one in arithmetic logic module 147 on one or two operands arriving at its first and second information inputs on the bus 159 from the second information input 158 of block 9 and on the bus 160 from the output of the switch 146, carry out the shift of the result of the arithmetic logic operation on the shifter 148, memorize the result of the operation in the data register 149, generate and store signs of operation on triggers 152 characters, 153 zero, 154 overflow, 155 transfers. On trigger 152, the senior (sign) bit of the shifter 148 is remembered. Element 150 W, to which the outputs of all bits of the shifter arrive, forms at its output a sign of zero result Element. 151 EXCLUSIVE OR forms at the output a sign of overlap. Signs trigger triggers

operations 152 characters, 153 zero, 154 overflows, transfer 153 via bus 39 through the second output 34 bpock 9 enter the indicative part of the state register 1 and respectively to the first to fourth information inputs of the switch, 30 of the microcommand address generation unit 15. The output 51 of the data register 149 through the second output 34 of the block 9 is fed to the inputs of the block 5 of data transmitters, the switch 10, the state register 1, the block 15 for generating the microcommand addresses. The switch 146, under the control of a signal arriving via line 165 from control input 167 of block 9, switches to its output the contents of the second register 184 of block 8 of registers arriving via bus 157 from the second information input 158 of block 9, or the contents of the first information block 9, arriving bus 156 from the switch output 10.

In the state 1 register, on the leading edge of the control signal, loading the state register arriving on line 173 from the synchronous input 174, on the flip-flops 168, 169 and 170, the corresponding bits of the data register 149 are stored on bus 51 from the input 34 of register 1 neither In this case, the switches 171 pass the corresponding bits of the data register 149, coming through bus 51, to the input of flip-flops 169, with a high signal level on the line 176. Signs of the result of the operation, coming through bus 39 from input 34 through the switches 171, with a low signal level on the line 176 memorized on the flip-flops 169 on the leading edge of the signal. Setting the signs coming along the line 175.

In block 8 of the registers in the first half of the machine clock cycle, which is determined by the high level of the signal on line 196 Phase 7, reading is performed from the nodes 181 of the first and 182 second registers in one register, the address of each of which comes from the output of the switches 178 and 179, respectively. Switch 178 switches the address of the selectable register to the address input of node 181 of the first registers from the first 185 or second 188, or third 189 address inputs of block 8, depending on the code on the line 190. Switch 179 switches the address of the selectable register to the address input of the node 182 second registers via switch 180 from the first 185 or second 188, or third 189 address inputs of block 8, depending on the code on the line 191. The operation of the switches 178, 179 is described by the following logical formula

,

23 33 where 1. 3, respectively, the first address inputs of these switches 2.,,, - respectively the first and second control inputs of these switches, coming through lines 190 or 191 F3 in the switch of these switches In the second half of the machine, so that low level the signal on line 196. recording of the information received at the information input 161 of block 8 into that of the registers of the nodes 181 of the first and 182 second registers, whose address comes from the switch 178. At the same time, the switch 180 switches to the address input of the node 182 of the second register There are switch output 178 in the first half of the machine cycle. Due to the high signal level on line 196 (Fig. 11), switch 180 switches the address of node 182 of the second registers to switch output 179. When recording information, signals on lines 193 and 194 have. low levels. The reading is performed when the signal level on line 193 is low and the signal level on line 194 is read. Information from the first register register node 181 records from the gate on line 195 Phase 4 to the first 183 register, from which it sends over the bus 159. The second register of information is recorded on the same strobe. Phase 4 is in the second 184 register, from where it is issued via bus 157. The pulse former 12 generates control signals for other processor units. The clock generator 197 generates the clock signals (FIG. 11) necessary for the operation of various units. Thus, for example, information on the micro-command register 13 is entered by the sync signal of Phase 2, received via line 135. The signal in register block 8 is generated when there is a high signal level on line 213, coming from the corresponding bit of the micro-command register 13. Decoders 198200 decrypt the corresponding fields of the operating part of the register 13 microinstructions, arriving at their inputs, respectively, on lines 215, 32 221 and 223. Transcoding node 211, depending on the code on lines 217220, generates control signals on lines 41-48 for the unit to work 15 forming the address of microinstructions in accordance with the table shown in FIG. 12 and the description of the operation: bots of the microcommand address generation unit 15. The device provides an efficient mechanism for accessing the firmware level of control through interrupts, which makes it possible to increase the performance of various user algorithms, operating systems, and input / output drivers by a factor of 2–10 with little hardware costs. The performance degradation is achieved due to the possibility of the firmware implementation of the algorithm for processing interrupts from external devices and internal interruptions when executing commands of extracodes. An increase in the speed of interrupt microprogram processing is achieved by reducing the number of accesses to the relatively slow-acting main memory due to the absence of command selection steps, the use of higher-speed internal processor elements for storing intermediate results; high microcommand operational saturation, which allows to perform several operations in parallel (in the proposed technical solution, one microcosm can perform up to six operations; reading operands, arithmetic and logic operation, shifting, recording the result, setting signs and checking conditions for reducing the number of steps when organizing branching in several directions due to the possibility of setting group branching in one microcommand; less time of microcommand sampling from the microprogram memory by comparison with the time of fetching commands from the main memory; reducing the time to save-restore the state of the interrupted program by saving the recovery of one register during microprogram interrupt processing instead of several (from 2 to 8) during program interrupt processing tz

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fig 12

Claims (1)

A FIRMWARE MICROPROGRAM PROCESSOR, containing a status register, an interrupt block, a synchronization block, a data receiver block, data transmitter and address blocks, an address register, a register block, an operation block, a switch, an instruction register, a pulse shaper, a micro-instruction register, a microprogram memory block and a micro command address generation unit, a control input, the first and second information inputs and the output of which are connected respectively to the output of the pulse shaper, the first address output m of the micro-command register, the first output of the command register and the Address input of the microprogram memory block, the control input and output of which are connected respectively to the output of the pulse shaper and the input of the micro-register register ^ control input, information input, the first, second and third address inputs of the register block are connected respectively with the output of the pulse shaper, the first output of the operating unit, the second output of the command register, the second address output of the micro-command register and the first output of the address register, sync ode, the information input and the second output of which are connected respectively to the output of the pulse shaper, the first output of the operation unit and the information input of the address transmitter unit, the first and second information inputs of the operation unit are connected to the outputs of the switch and the register unit, and the second output of the operation unit is connected to the information the inputs of the state register and the block of data transmitters and the third information input of the block forming the address of the micro-command, control input, first, w The second, third and fourth information inputs of the switch are connected respectively to the output of the pulse shaper, the information output of the data receiver block, the information output of the status register, the second output of the operation block and the output of the micro-register register constant, the information input and the first output of the interrupt block are connected to the control input-output of the processor and the sync input, control input and the second output of the interrupt unit are connected respectively to the output of the pulse shaper, the characteristic output a state register and the fourth information input of the micro-command address generation unit, the status register clock input and the operating unit control input are connected to the pulse former, the pulse former is connected to the operational output of the micro-register, the clock input and the command register information are connected respectively to the pulse former and the information the output of the block of data receivers, the input of which is connected to the information input-output of the processor, the outputs of the block before of data sensors and the block of address transmitters are connected respectively to the information and control inputs and outputs of the processor, and the control inputs of these blocks are connected to the output of the synchronization block, the read / write control input of which is connected to the output of the pulse shaper, and the mode control input and the output of the synchronization block are connected to the control input of the processor, distinguishing with the fact that, in order to improve performance, it contains an interrupt processing indicator block, including two AND elements, two elements OR and a trigger, the information input, the clock input and output of which are connected respectively to the outputs of the first and second elements OR and the fifth information input of the micro-command address generating unit, the sixth information input of which is connected to the output of the additional status register attribute, the first and second inputs of the first OR element are connected to the outputs, respectively, of the first and second AND elements, the first inputs of which are connected to the output of the pulse shaper and the inputs of the second OR element, and the second inputs of the first and second of elements and connected respectively to output data indicative of the receiver unit and output of the microinstruction register constant.