SU972494A1 - Data input-output control device - Google Patents

Description

(5) DEVICE FOR CONTROLLING INFORMATION INPUT

one

The invention relates to automation and computing technology and can be used for organizing the exchange of information in collective systems for the use of computing resources, information retrieval systems, and so on.

A device for input / output information is known, comprising a processor, a memory unit, an interface unit and a clock signal generating unit with their communications Cl.

The disadvantage of this device is limited functionality when entering large amounts of data from the most priority users.

The closest in technical essence to the present invention is a device for input-output information, containing a processor processing instruction block, the communication register c. processor, mask register, priority analysis block, request register.

address output block, data output glint, subchannels by the number of input / output devices, each of which contains a control word register, a control signal generator, a write register, a read register, a machine clock counter with their connections 2.

A disadvantage of the known device is its limited functionality.

The purpose of the invention is the expansion of functional capabilities: device by organizing a priority mode of information exchange with external devices. roystva

This goal is achieved by the fact that the first, second, and third counters, pulse generator, first and second registers are entered into the first, second, and third elements of the I / O device, the first, second, third, and fourth elements, 3.97 / pulse distributor, one-shot, comparison unit, first, second and third decoders, OR element, switch and trigger, the first input of which is the first input of the device, the second input connected to the output of the first counter, the direct output to the first input of the first And, the inverse output - with the first input of the device, the second input of the first element And is connected to the output of the pulse former, with the first input of the second element And with the first inputs of And elements of the group, and the output with the inputs of the first and second counters and with the first input of the first register ; pa whose second input is connected to the input of the second register and is the second input of the device, and the output to the first input of the distributor, the second input of which is connected to the output of the second counter, and the outputs are the outputs of the first group of the device, the outputs And ementov groups are output devices of the second group, the output of the second AND gate connected to the first

the input of the third element is And with the first input of the third register, the second input of which is connected to the output of the element OR, the third input is connected to the first input of the device, the fourth input is connected to the first input of the third counter and BbixojqoM one-shot, the first output is to the second output of the device the second output is with the input of the first decoder, the direct output of which is the third output of the device, and the inverse output is connected to the second input of the second element AND, the inputs of the group of the OR element are inputs of the first group, the output of the second D the hyste is connected to the first input of the comparator unit, the second input of which is connected to the switch output, the first output is the fourth output of the device and is connected to the input of the one-vibrator and the first input of the fourth And element, the second output is connected to the second input of the third And element, the output of which is connected to the second input of the third counter, the output of which is connected to the second input of the fourth element I, the output of the switch and the input of the second decoder, the outputs of which are connected to the second inputs of the elements of the group, the output of the fourth The AND terminal is the fifth output of the device, the switch inputs are the inputs of the second group device.

25 scrap 20. Then, on the installation bus, the processor sends a signal that translates trigger 4 into a state allowing clock pulses from the imaging unit 13 through element 8 to the inputs of counter 10, counter 20 and the shift input of register 2. As a result, the distributor 21 controlled the counter 12, the contents of the register register 2 enters the corresponding ter The drawing shows a block diagram of the device. The device contains a processor 1, the first and second registers 2 and 3, the trigger 4, the third register 5, block 6 comparison, one-shot 7, the first element And 8, the first decoder) 9, the first counter 10, the second element And 11, the second estimator 12, pulse shaper 13, elements AND groups And, the third element And 15, the fourth element And 16, the third counter 17, the switch 18, the second dispenser 19, terminals 20, the distributor 21, the element OR 22. The device works as follows. Processor 1 according to the program sets either the read mode or the write mode of the information. I In the mode of recording information to the terminals 10, the processor 1 transfers the first information packet to the register 2 via the information bus, in which the i-cell is assigned to the i-th terminal 20. At the time of issuing the last character from register 2 from counter 10, a signal is set that triggers in the state prohibiting receipt of clock pulses through the element 8, and from the inverse output of the trigger, a recording interrupt signal is generated, according to which the processor 1 sets a new dose of information in register 2. The operations continue until the recording mode is removed. In the mode of reading information from terminals 20, the output information bus of processor 1 is loaded into register 3, the code corresponding to the minimum priority of terminal 20, or the indication of the slow terminal 20, then the code leading register 5 to original (zero) is removed from the installation bus from processor 1 a state, with the marker being written to the first digit of this register. If the code of the de register register 5 is zero, then the inverse output of the decoder 9 is removed

the signal that permits the passage of clock pulses from the imaging unit 13 through the element L. The clock pulse arrives at the shift input of register 5 preparing it for receiving the code from the next terminal 20. This same signal provided that the code in register 3 is more or equal to the request code arriving from terminal 20 via U switch 18 to block 6, transfers counter 17 to a new state, decoded by decoder 19, as permission to connect a clock signal from driver 13 through i and element T to i and terminal 20. In a result: those from the terminal 20 with The symbol code written into register 5 is processed through element 22. If the request code from this terminal 20 does not exceed code 20 in register 3, then the read operations on the character from each terminal 20 continue until the last bit of register 5 of the code Marker appears in the last bit. . At this moment with inverse output 25

the decoder 9 removes the signal that prohibits the passage of clock pulses through the element 11, and from the direct one; The output of the decoder 9 generates a processor interrupt 1, by which the contents of register 5 go to the processor 1 via the information bus. The read operation continues after the installation code in register 5.35 enters the processor 1 set bus 1

If, during the read mode, a request code of terminal 20 is detected, which is greater than the code stored in register 3, then a signal is removed from block 6 that prohibits a change of address in counter 17, another output of block 6, the signal is received by processor 1 to interrupt it and allowing the receipt of the address code through element 16 to processor 1, which ensures identification of the received information. In this case, the reading is carried out in the same way as it was shown, but the characters in register 5 are written only from one selected terminal 20. Interrogation 50 of the other terminals 20 continues after the request from the terminal has the highest priority. At this moment, the one-shot 7 on the falling edge of the pulse forms, in marker times, a row of de register 5 to clear it from

information and resets counter 17 to zero. After the signal arrives at

The bus for installing processor 1 to register 5, the device continues operations in the read memory.

When working with terminals of the same type, the invention allows the use of priority information retrieval mode, which is especially important in the conditions of automated control systems, where the occurrence of extreme situations requires first of all information processing and a control node that is the source of this situation, provided that applicants are serviced evenly.

Claims (1)

Invention Formula A device for controlling information input and output, containing the first second and third counters, pulse generator, first and second registers, characterized in that, in order to expand functionality by organizing a priority mode of information exchange with external devices, first, second, third, and fourth are entered into it elements AND, group of elements AND third register, pulse distributor, one-shot, block compared to them, first, second and third decoders, OR element, switch and trigger, first input the first input of the device, the second input is connected to the output of the first counter, the direct output to the first input of the first element I, the inverse output to the first input of the device, the second input of the first element I connected to the output of the pulse former, to the first input of the second And with the first inputs of the AND elements of the group, and the output with the inputs of the first and second counters. And with the first input of the first register, the second input of which is connected to the input of the second register and is the second input of the device, and the output to the first input of The terminal, the second input of which is connected to the output of the second counter, and the outputs are outputs of the first group of the device, the outputs of the elements of the AND group are the outputs of the device of the second group, the output of the second element AND is connected to the first input of the third element AND register, the second input of which is connected to the output of the OR element, the third input is connected to the first input of the device, the fourth input - to the first input