SU1524055A1 - Device for checking programs - Google Patents

Abstract

The invention relates to digital computing and can be used in the development of software control systems. The device contains registers 1-6, blocks 7 and 8 elements AND, elements OR 9-13, comparison unit 19, memory block 14, instruction decoder 16, pulse distributor 15, adder 17, subtraction unit 18, delay elements 20 and 21. The invention makes it possible to increase the reliability of program control by controlling the correctness of program execution through control and data communications. The correctness of program execution is determined on the basis of the "dimensions" control of operands of the controlled operation, which are defined by the program developer or are determined during the translation stage. "dimensions" are represented by numbers. The verification takes into account that for the operations of addition, subtraction and comparison of the "dimension" of the operands must be the same, i.e. the sequence of control and information links between program objects is performed correctly. 1 il.

Description

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The invention relates to digital computing and can be used in the development of software control systems.

The purpose of the invention is to increase the reliability of the control device.

The drawing shows the proposed device.

Monitoring the correctness of program execution, based on checking the correctness of its informational and control links between program objects in the process of execution, is exemplified.

Let the assignment operator be executed.

(E + T) / B.

For correctly written programs in the context of this operator, the following relations between the physical dimensions of the quantities (P, A, C, E, T, B) should be fulfilled:

Cp A c3 Ali: c3; ,

Р (Е-ЬТ) / Б El Bj t В; ,

where US is the size of a volume

ekta X.

Verifying the correctness of the performed ratios by their dimensions is the essence of the localization of errors when executing software. Dimension values are determined by the developer or at the stage of program translation and are presented to numbers. When checking y1, it is assumed that for addition operations, now, comparisons of the dimensions of the operands must be one D, i.e. a sequence of control and informational links between program objects. performed correctly. Therefore, when performing | -d ET1GH operations, in order to verify the correctness of program execution, it is necessary to compare the values of the dimensions of the corresponding operands. If the values of the dimensions coincide, then the program is executed correctly, if they do not match, then a violation occurred on the program’s direct links (for execution a program fragment from another part of the program is involved) or a violation on the program’s communication links (for For the operation, the wrong program object was selected). In the process of implementing the program of internal dimension

Program objects (variables) can be changed when performing addition and division operations. Therefore, when multiplying and dividing, the dimensions of the operands are added and subtracted accordingly.

The device for controlling the progress of the programs contains six registers 1-6,

the first and second blocks of elements And 7 and 8, the first - the third elements of OR 9-11, two blocks of elements OR 12 and 13, block 14 of memory, distributor 15 pulses, decoder 16 commands,

adder 17, subtraction unit 18, comparison circuit Miii 19, first and second delay elements 20 and 21, clock input 22, second, second, third information inputs 23-25,

Output 26 is a device error.

Command decoder 16 has three B1) :; ode. The first output corresponds to “-decoding of the multiply command, the second - dividing, the third - adding,

subtraction and comparison.

The device works as follows.

Before the device starts operation, the information corresponding to the program being executed is stored in the memory. It is a section of the memory of the monitored program, in which the addresses of the similar, intermediate, and output objects (variables) of the program are assigned the corresponding dimension values, the remaining memory cells are set to zero. The dimensions of the dimensions are presented in the form of numbers, which, according to the corresponding rules, are indicated by the developer of the program or are determined automatically using a special translator. When the device is ready for operation, the sitals from the clock input 22 begin to arrive at the input of the distributor 15 pulses that the processor has prepared the next command for execution, while the information inputs of the device 23-25 are received. Accordingly, the operation code, addresses of the first and second operands. From the first, second and third outputs of the distributor 15 pulses are output sequentially

These signals allow the recording of information from inputs 24, 25 and .3 to the first 4, second 3 and third 2 registers, respectively. At the same time

51524055

the third control signal of the distribution - the first delay element 20, where

A pulse of 15 pulses through the first delay is delayed by the time required

to perform the addition operation in the adder 17. From the output of the first delay element 20, the control signal enables the result of adding the result OR 9 allows the information corresponding to the address of the first operand to pass from the information output of the second register 2 through the first element AND 7 and the second element OR 10 to the address input block 14. The same third control signal of the distributor 5 pulses through the third element OR 11 allows reading information from the memory block 14 to the address specified on the address input of the memory block 14, i.e. reading information corresponding to the dimension value, the address of which is in BTopoi-i register 2. The control signal from the fourth output of the distributor 15 pulses permits writing of the dimension a register 4 read from block 14 of the memory.

Similarly, the control signal from the fifth output of the pulse distributor 15 permits reading the dimension code corresponding to the address of the second operand, which comes from the third 3 regg.stra through the second element 8 and the 1sh 10 element to the address input of the memory block 14, the read signal goes through the third element OR 11. The control signal from the sixth output of the pulse distributor enables writing the read dimension code to the fifth register 5.

Thus, in the fourth and fifth registers 4 and 5 there is a corresponding BeTCTByromirii code of the dimensions of the first and second operands of the controlled operation.

The control signal from the seventh output, the distributor 15 pulses to 10

This information is fed to the input of register 6 through the fifth element OR 13. At the same time, the signal from the output of the first delay element 20 through the second delay element 21 enters the write control input of memory block 14 and simultaneously

15 permits the passage of the information of the address of the first operand from the second register 2 through the first block of elements AND 7 and the second element OR 10, respectively, to the address input of the memory block 20 14. The memory block records the dimension code arriving from KiecToro register 6 to the information input of the block 14 memory at the address specified on the address input of the unit

25 4 memories, i.e. at the address of the first operand of the operation being performed.

Changes of dimensions are carried out in a similar way, if controlla; the signal comes from the second output of the decoder 16 commands, which corresponds to the execution of the division operation.

If the decoder 16 of the commands determines the addition, subtraction, or comparison command, then the control signal appears at the third output. It enters the control input of the comparison circuit I9. In this case, in the comparison circuit 19, the codes that are 40 steps to register O2 3 and 5 are compared. If the values of the dimensions coincide, i.e. Since the codes are equal, then the monitored nporpaMt.a is executed correctly. If the dimension values are not

0

This information is fed to the input of register 6 through the fifth element OR 13. At the same time, the signal from the output of the first delay element 20 through the second delay element 21 enters the write control input of memory block 14 and simultaneously

5 permits the passage of the information of the address of the first operand from the second register 2 through the first block of elements AND 7 and the second element OR 10, respectively, to the address input of the memory block 0 and 14. The memory block records the dimension code received from the KiecToro register 6 to the information input of the block 14 memory at the address specified on the address input of the unit

5 4 memories, i.e. at the address of the first operand of the operation being performed.

Changes of dimensions are carried out in a similar way, if controlla; the signal comes from the second output of the decoder 16 commands, which corresponds to the execution of the division operation.

If the decoder 16 of the commands determines the addition, subtraction, or comparison command, then the control signal appears at the third output. It enters the control input of the comparison circuit I9. In this case, in the comparison circuit 19, the codes arriving from register O2 3 and 5 are compared. If the values of the dimensions coincide, i.e. Since the codes are equal, then the monitored nporpaMt.a is executed correctly. If the dimension values are not

step on the control input of the decipher dZ coincidence, an error is detected and

To a command 16 that decrypts the operation code and at its output (one of the three) a control signal appears corresponding to the operation code. If a multiplication operation is performed, the control signal appears on the first you: the decoder of 16 commands. This signal is fed to the control input of the adder 17 and allows the operation to add the values of the dimensions in the fourth 4 and fifth 5 registers. At the same time, this control signal goes through the fourth element OR 12 to the input

50

From sup-: one of the comparison circuits, an error signal is output to the output of the device 26.

Claims (1)

Invention Formula The device for controlling the program contains six registers, the first and second blocks of the AND elements, the first one and the second elements 1-SHI, the memory block, the comparison circuit and the distributor and pulses, first the output of the pulse distributor is connected to the input of the first register, the output cat 50 From sup-: One of the comparison circuits, an error signal is output to the output of the device 26. Invention Formula A device for controlling programs containing six registers, the first and second blocks of the AND elements, the first and second elements of 1-SHI, the memory block, the comparison circuit and the pulse distributor, first of which the first distributor of pulses is connected to the input of the first register, whose output It is connected to the first input of the first element AND, characterized in that, in order to increase the reliability of the control, a third OR element and two blocks of the OR elements, a command decoder, an adder, a subtractor, the first and second delay elements are entered into the device, and the address inputs of the first and the second operand and the operation code of the device are connected to the information inputs of the first, second and third registers, respectively, the device synchronization input is connected to the pulse input of the pulse distributor, the second output of which is connected The third output of the pulse distributor is connected to the recording input of the second register, with the first input of the first OR element, the output of which is connected to the second input of the first block of AND elements, the output of which is connected to the first the input of the first block of elements OR, the third, fourth, fifth, sixth and seventh outputs of the pulse distributor are connected respectively to the first input of the second OR element, to the recording input of the fourth register, to the second input the second OR element, with the input of the recording of the fifth register and the clock input of the command depotfraser, the first, second and third outputs of which are connected respectively to the first input of the third OR element, to the second input of the third OR element, and to the clock input of the comparison circuit, the fifth output distribution 5 n 0 five 0 five The pulse generator is connected to the control input of the second block of AND elements, the output of which is connected to the second input of the first block of OR elements, the output of which is connected to the address input of the memory block, the output of the second register is connected to the information input of the second block of AND elements, the output of the second OR element connected to the read input of the memory block, whose information output is connected to the information inputs of the fourth and fifth registers; the output of the third OR element is connected through the first delay element to the write input of the sixth register jC by the second input of the first OR element and through the second delay element with the recording input of the memory unit, the output of the fourth register is connected to the input of the first operand of the adder, with the input of the first operand of the subtractor and with the first input of the comparison circuit whose output is the output of the device error, output The 5th register is connected to the second input of the comparison circuit, to the input of the second operand of the subtraction unit, and to the input of the second operand of the court, the output of which is connected to the first input of the second block of OR elements, first and second outputs The instruction decoder odes are connected to the tamper input of the adder and to the clock input of the subtraction unit, the output of which is connected to the second input of the second block of SHS elements, the output of which is connected to the informational input of the sixth register, the output of which is connected to the information input of the memory unit.