SU1456963A1 - Device for interfacing electronic computer with common trunk line - Google Patents

Abstract

The invention relates to computing and is intended to interface several computers to a homogeneous computing system with a common highway. The first step of the invention is to improve speed. The device contains a switching unit, a setting unit, a setting verification unit, a generalized conditional transition unit, a synchronization register, a firmware control block, a status register, an address decoder, a transceiver register, a direct memory access block, an interrupt block. 3 hp ff, 13 ill.

Description

one

The invention relates to computing and is intended to interface several computers into a single-computing computer system with a common backbone.

The purpose of the invention is to increase speed.

Figure 1 shows the structural diagram of the device; -2-1 2 - examples of the implementation of a switching unit, a setting unit, a setting checker, a generalized conditional transition block, a synchronization register, a microprogram control unit, a state register, an address decoder, a transceiver register, a direct access block to the memory, the pre-icing unit, respectively; on Fig - structural diagram of a homogeneous computing system using the proposed device.

with:

The device contains (FIG. I) switching unit 1, setting unit 2, setting check unit 3, generalized conditional transition unit 4, synchronization register 5, firmware control unit 6, status register 7, address decoder 8, transceiver register 9 , block 10 of direct memory access, block 11 of interruptions, inputs-outputs 12-14 of the switching unit, groups of inputs-outputs 15 and 16 of the device, inputs and outputs of 17-84 nodes and blocks of the device.

Switching patch 1 contains (Fig. 2) transmitters 85. and information signal receivers 86, control signal transmitters 87-89, signal / control transmitter 90, control signal transmitter 91, and control signal receivers 92-96.

ate

O5

with

05 DO

Block 2 settings contains (fig.Z) switch 97 and trigger 98,

Unit 3 for checking the configuration contents (Figure 4) of the element And 99, the switch 100 and the element 101 of the comparison.

Block 4 of the generalized conditional transition contains (FIG. 3) the trigger 102 of the particular condition and the trigger 103 of the generalized condition.

Synchronization register 5 (FIG. 6) may consist of synchronization trigger 104 (K555TM2).

Block 6 mic1) of the program control computer in the system interaction. Signs of the setting are transmitted by one of the computers in the address word of the setting and are fixed by the trigger 98 in block 2 of the computer indicated in the address word. In the process of setting up, hardware failures or shutdown of the computer from the common highway are possible, therefore the device of the setting up computer makes an on-line check of the response address word (the presence of setting signs in the receiving computers) and the address word of the setting. This way

neither contains (Fig.7) the memory 105 micro-15 with the working configuration of the calculator program, the register of microcommand addresses 106, the address coder 107, the multiplexer 108 and the register of command 109.

The state register 7 contains (FIG. 8) the AND elements, the first 111 and the second 112 triggers.

The address decoder 8 contains (FIG. 9) a write decal 113 conditions, a read condition decoder 114, address registers 115, AND elements 116-188, OR 9 and 11 and delay elements 120.

Register 9 transceiver contains (figure 10) register 12) data and the elements K 122.

Direct memory access unit 10 contains (FIG. 11) counter 123, register 124, triggers 125-129, group of elements K 130, elements K 131 and 132, element CLA 133 and elements 134 and 135 of the delay.

Block 11 prertani contains (Fig.12) triggers 136 and 137, the elements To 138 and 139, a group of elements And 140.

A homogeneous computing system built on the basis of the proposed device is a system with a common backbone consisting of a computer 14 connected with interface devices 142 (Fig. 13),

The system allows to solve complex tasks that cannot be solved on a single computer due to insufficient speed, RAM size, reliability.

The following system operations are performed in the computing system: setup, exchange, generalized conditional transition, generalized unconditional transition ,. .

The setting is to assign to one or more computers a sign indicating whether the data is involved.

0

0

five

Noah system.

The device has four software-accessible registers: register of 7 states, register of 109 commands, register 124 and counter 123, Assignment of state register 7 — displaying the command code (1p-3p), readiness (7p), generalized conditional transition (8p) and setting error (15p) of the status register.

5 The assignment of the instruction register 109 is the fixation of the instruction code (1p -3p) and the resolution of the interrupt (-6th bit of the instruction register). The register 124 stores the address of the beginning of the data block in the computer RAM, from which (into which) the data will be read (written). The register 124 increases its value by 2 by the hardware. In the counter 123, the size of the data block is entered, and the counter of the contents of the data counter is subtracted by the hardware.

Before each system performs a computer operation, it prepares the device by entering or exchanging information through a group of inputs and outputs 16 to the addresses of command registers 109 and state 7 of register 124 of counter 123.

At the beginning of the computer, it sets the address of the corresponding register from the register area allocated for external device registers. The address comes through a group of inputs and outputs 16, from the computer to the inputs of the register 115 of the address and

The Q inputs of the And 116. Element. The signal for recording the address, coming through the group of I / O 15 to the input of register 115, gates by storing the address. When entering information (reading register 7

g state) the computer sends an input signal to the input of the element 118 in the input-output group 15 — the signal from the output of the address register 115 arrives at the other input of the element 118. The signal from the output of the AND 118 element arrives at the enabling input of the decoder 114 reading condition, permitting the output 60 of the decoder 114 of the signal to read the read state register (PTS). In addition, the signal from the output element AND 1I7 through the element OR 119 and the element 120 delay as the response signal received data; the synchronization signal from the output of the delay element 120 (Sin), which establishes the particular condition of the group of inputs and outputs 15 in the computer, computer, the synchronization flag; the control signal, having received the response signal, counts the data of the role (K), which requires to set a prize from the information output 55 of the settings register to the trunk; The signal of the 7 states, which arrive at the is a private condition (NC), sets the group of inputs-outputs 16 in the computer, and removes all signals.

When entering information into the device, the addressing cycle is repeated. The computer sends 15 signals (20), input (BB), output (SB), input signal, which receives data (CTD), reads the address of the input element K 117, to another input element And 117 receives a signal from the output of the address register 115. The signal from the output of the element 117 goes to the permitting input of the decoder 113 of the recording conditions, allowing the appearance at the outputs of the decoder 113 of the conditions recording the particular condition with a generalized conditional transition; direct access signal (PD initiating the operation of direct access unit 10; address signals

(ChAdr), increasing the contents of the current address register (+2), subtracting the word counter (-1), which participate in the direct memory access mode; the interruption signal (Pr) activating the operation of the interruption unit 11; the signal Setting itself.

C, and therefore, at outputs 61, the Second field is the field in which the co 62, 66 and 67 of the decoder 8 addresses the signal 30 is held - the address code to form the recording conditions of the particular condition (Cn NC), the address of the next microcommand (AFMK) , records of a command code (Zp RK), record

which arrives at the corresponding inputs of the next-address address coder 107,

in the register of the current address (ZPRTA), entry in the counter of the number of words (ZsSchSl),

Firmware control unit 6 operates as follows.

The command code from the register 109. commands enter the input of the address encoder 107. The latter provides for the command to decode the microprogram cycle by repeating the command code received from the command.

Having received the appropriate command,

the command hub 109 encrypts the address of the next microcommand as a linear sequence of microcommands as well as conditional and unconditional jumps, depending on the sign of the transition coming from the output of the multiplexer 108. Thus, the encoder 107 forms the address of the microcommand and the device is exchanged with the computer in the forward mode access to the memory, the product 45, while entering or outputting information into the RAM (from RAM),

Direct memory access procedure. This mode initiates block 6 of firmware control. To the commands that installs it at the memory outputs 105, A first micro-command appears at its outputs, to be implemented in the current microswitches it to the address register 106 of the nick-50 Direct input memory access block 72 appears. my access (PD), which is fed simultaneously to the input element K 131 and the installation inputs of the trigger 125 command cycle. The microcommand contains 55 and 127 pre-installed three main fields, forcibly low sig potential. The first field is the micro-operation code (KMO) field that defines micro-operations performed as on blocks

Nala Direct access to the zero state. To the other input element K 131 receives a single signal from zero

Depending on the command being executed, in the KMO field (at output 46 of block 6), the following appears: a tuning signal (H) that synchronizes the transmitted address tuning word; signal exchange (Obm), strobe the transmitted data; the synchronization signal (Syn), which establishes a particular condition of the synchronization flag; the control signal (K), which requires setting the parameters of the configuration to the trunk; a private signal (NC) setting

(Adr), input (BB), output (Higher), data reading (ChtD), reading address

a particular condition under a generalized conditional transition; direct access signal (PD initiating the operation of direct access unit 10; address signals

(Adr), input (BB), output (Higher), data reading (ChtD), reading address

(ChAdr), increasing the contents of the current address register (+2), subtracting the word counter (-1), which take part in the direct memory access mode; the interruption signal (Pr) activating the operation of the interruption unit 11; the signal Setting itself.

 The second field — the field in which it is kept — is the address code to form the address of the next microcommand (AFMC),

which arrives at the corresponding inputs of the next-address address coder 107,

35 The third field is the control field of multiplexer 107 (KUM), to which signs of execution of one or another micro-operation are applied.

After the readout, the microdevice exchanges with the computer in the direct memory access mode, the product being in this case inputting or outputting information into the RAM (from the RAM),

Direct memory access procedure. This mode initiates block 6 of firmware control. At the control input 72 of the direct memory access unit, a Direct Access (PD) signal appears, which simultaneously enters the input of the K 131 element and the setup inputs of the trigger 125 and 127, which are preset forcibly low by the potential of the Direct Access signal to zero. condition. To the other input element K 131 receives a single signal from zero

trigger output 125. At the output of the element 131, a signal appears. Requirement of direct access, which via the control channel output 78 arrives at, a group of inputs-outputs 15 S computers. At the end of the processor cycle (. my access, set the direct access grant signal by a group of input-output 1 5 from the computer. This signal is sent to the channel control input 79 of the unit 10 at the same time to the sync input of the trigger 127 and the input of the element 134

ten

Neither sampling means that the device has captured the mainline of the computer and can perform I / O to the RAM (from the RAM), the computer removes the direct access grant signal.

The sign of the sample confirmation signal goes through the output 75 of the signs to the input 49 of the microprogram control unit 6, which removes the direct access signal. Microprogram control unit 6 performs a micro-operation Input (transfer of information from RAM to the system backbone)

delays. Confirmation signal to direct js or microtool (transmission

go access consistently passes

through all external computer devices,

have direct access equipment

memory Therefore, if the device is 142

mates are not involved in capturing the signal control reading address,

data from the register 9 transceivers in the RAM. Computer)

During micro-operations, microprogram control unit 6 is activated.

Address

 Input

Conclusion

, Reading

data in the code field of micro-operations of memory 105 microinstructions.

Consider, for example, the implementation of

computer gages, t, e, triggers 125. and 127 are in the zero state, from the zero output of the trigger 127 a positive potential is fed to the input of the element I 132, and to the other input of the element 25 of the microoperation. input signal Firmware access control unit 6 (direct access delayed by delay delay element) 34, a little longer than the switching time of the trigger 127, The single value of the output signal of the direct access representation comes from the output

thirty

It analyzes the status of the confirmation of the direct access coming from the single output of the trigger 125 through the output 75 to the input 49 of the signs (in the code field of the memory instruction 105 of the micro-commands the channel code corresponding to this input of the multiplexer 108 is set) , then at the control output 46 a signal appears Reading the address, which through the control input 72 comes to the first inputs of the elements And 130, to the second

element K 132 through the channel control output 78 to a group of inputs / outputs 15 in the computer and then to the device that requested the capture of the computer bus,

It analyzes the status of the confirmation of the direct access coming from the single output of the trigger 125 through the output 75 to the input 49 of the signs (in the code field of the memory instruction 105 of the micro-commands the channel code corresponding to this input of the multiplexer 108 is set) , then at the control output 46 a signal appears Reading the address, which through the control input 72 comes to the first inputs of the elements And 130, to the second

On the leading edge of the input representation access signal, the trigger 1 27 is set to one and at its 40 inputs which receive signals from the output; Zero output, a zero value appears on the register 124, At the outputs, the element prohibiting the passage of inputs 130 the address of the RAM appears, which enters through the information output 77 to the group of inputs-outputs 16

JHoro signal of the provision of direct access to the control channel output and 130 is the address of the RAM, which is fed through the information output 77 to the group of inputs-outputs 16

course 78, A positive signal from one output 46 of the pioneering output of the trigger 127 through the OR element 133 is fed to the sync input of the trigger 125 and sets it to one. The low level of the signal from the zero output of the trigger 125 is received at the input of the And 131 element, stopping the signal of the direct access requirement from the output of the K 131 element. The positive signal from the single output of the trigger 125 is fed through the caggral control output 78 of the unit 10 on a group of inputs and outputs 15 in the computer as a signal to confirm the sample. Activating the confirmation signal. The address that is fed to the trigger input 126 via the input 72 and sets it to one. From the single output of the trigger 126, the signal to the channel control output 78 is sent as the address tracking signal, which is used for the address decoder of the RAM circuit. Then, a signal Read data, appearing at the input 71 of the transceiver register 9, appears at the control output 46, From the output 71 the signal Read data goes to the second inputs of the elements And 122, to the first inputs

Neither sampling means that the device has captured the mainline of the computer and can perform I / O to the RAM (from the RAM), the computer removes the direct access grant signal.

The sign of the sample confirmation signal goes through the output 75 of the signs to the input 49 of the microprogram control unit 6, which removes the direct access signal. Microprogram control unit 6 performs a micro-operation Input (transfer of information from RAM to the system backbone)

data from the register 9 transceivers in the RAM. Computer)

During micro-operations, microprogram control unit 6 is activated.

control signals Reading address

Address

 Input

Conclusion

, Reading

Microoperations Output, Firmware Control Unit 6

data in the code field of micro-operations of memory 105 microinstructions.

Consider, for example, the implementation of

microoperations Output, Microprogram control unit 6

microoperations Output, Microprogram control unit 6

It analyzes the status of the confirmation of the direct access coming from the single output of the trigger 125 through the output 75 to the input 49 of the signs (in the code field of the memory instruction 105 of the micro-commands the channel code corresponding to this input of the multiplexer 108 is set) , then at the control output 46 a signal appears Reading the address, which through the control input 72 comes to the first inputs of the elements And 130, to the second

the inputs of which receive signals from the output of register 124, the outputs of the element

the inputs of which receive signals from the output of register 124, the outputs of the element

Commerce And 130 appears the address of the RAM, which enters through information output 77 to a group of inputs / outputs 16

    exit 46 occurs

Address signal, which via input 72 enters synchronization trigger 126 and sets it to one. From single output trigger 126, a signal goes to channel control output 78 as an address strobe signal, at which the address decoder of the RAM circuit is activated, then the control output 46 appears a signal Read data received at the input 71 of the register 9 transceiver, From the output 71 the signal Read data goes to the second inputs of the elements And 122, to the first inputs 91

The outputs of the register 122 are connected to the outputs of the elements And 122 through the information output 70 to the data on the group of inputs and outputs 16 in the computer.

At control output 46, a signal B output arrives through input 72 to the trigger input 129. At the unit output of the latter, a single signal appears that goes through output 78 to a group of inputs / outputs 15 in a computer as a signal, indicating about

that the data is exposed. Circuit pack-15 move 46 appears signal setting

The RAM of the computer records the data at the address indicated by the device and sets the Response signal at the input-output group 15 of the computer. The Response Signal, through the control input 79, arrives at the set trigger input 129 delayed by the delay element 135. Signal Output from trigger output 129 is removed.

When the transmission of the word is completed, the firmware control unit 6 removes the direct access signal, which sets the trigger 125 to its initial state, and the confirmation-sampling signal from the trigger of the trigger 125 is removed.

Performing a micro-operation Input in a loop capture cycle is similar, except that instead of a signal Output at the control output 46

se, which is fed to the installation input 28 of block 2 settings. The signal from input 28 sets the trigger 98 to one state and on the infor20 form 27 output it appears

a unit potential, which is fed to the input 51 of the sign of tuning, Next, the firmware control unit 6 initiates the execution of the microprocessor Direct Access-Input. A set address address word appears on the I / O Group 16 of the computer, which is fed to the channel information input 25 of the switching unit 1 and

30 then goes to the system information input / output 12, entering the highway. Firmware control unit 6 activates the Setting (N) signal, which from the control

microprogram control unit 6 of the output 46 is supplied to the control

. The signal is Input, which from control input 72 enters the synchronization input of trigger 128 and sets it to one. From the output of trigger 128, control input 78 sends input signal to input-output group 16, in response to it the RAM control circuit The computer sets the data at the address of the RAM defined by the direct access cycle address to a group of I / O 16 of the computer. The data is accompanied by a Response signal, which also sets the trigger 128 to the initial state.

The setup procedure is as follows.

The computer, making the setting, prepares the service tuning block (SNE) in its RAM, the First word SNB — the address address settings, the bits of which are assigned to certain computers of the computing complex, the second word SNB is the operation code (data exchange, generalized conditional code 24 blocks 1 switching and through the main transmitter 91 arrives at the system input-output 13 on all devices,

40 Setting address word and signal H are sent to all devices 142 connected to the system trunk, then in each device the setting address word goes through the system

45 dark information input / output 12 switching unit 1 and information output 17 of the switching unit to the information input 29 of the tuner, on the gate of input 26 of which from the sy

50 of the main highway, a signal K is received, which has passed through the inputs-outputs 13 and 19 of the switching unit. The address layer in the settings is input to the switch 97 of the number, which connects

gg is one of the bits corresponding to the measure of the computer, to the input of the trigger 98 setup. The signal H, which arrives from the input 26 to the synchronization input of the trigger 98, sets it to the state corresponding to 10

move, code generalized unconditional transition), the third word - the size of the transmitted array. Next, the computer prepares the device for the tuning operation, writing the tuning command code to the register of the 109 commands, the address of the service tuning block placed in the computer RAM in the register 124, the size of the tuning block to the counter 123,

Firmware control unit 6 configures its interface device. At the same time, a control is issued on the control that is supplied to the setup input 28 of the settings block 2. The signal from input 28 sets the trigger 98 to one state and on the infor20 form 27 output it appears

a unit potential, which is fed to the input 51 of the sign of tuning, Next, the firmware control unit 6 initiates the execution of the microprocessor Direct Access-Input. A set address address word appears on the I / O Group 16 of the computer, which is fed to the channel information input 25 of the switching unit 1 and

30 then goes to the system information input / output 12, entering the highway. Firmware control unit 6 activates the Setting (N) signal, which from the control

5E-

the input 24 of the switching unit 1 and through the trunk transmitter 91 is fed to the system input-output 13 to all devices,

40 Setting address word and signal H are sent to all devices 142 connected to the system bus, and then in each device the setting address word is received via the system 45 dark information input-output 12, switching unit 1 and information output.17 switching unit to information input 29 of the tuner, to the gateway input 26 of which the signal K is fed from the sym of the system trunk, which has passed through the input-outputs 13 and 19 of the switching unit. The address of the settings is fed to the input of the switch 97 numbers, which connect

gg is one of the bits corresponding to the computer number to the trigger input 98 of the setting. The signal H, which arrives from the input 26 to the synchronization input of the trigger 98, sets it to the state corresponding to the information on the D input of the trigger 98,

After a time that is sufficient to switch the setting triggers - (300-400 nil), the tuning computer performs a tuning check.

A control signal appears at the control output 46, which enters the system input-output 14 of the switching unit via its input 24 and the main transmitter 90. The control-signal goes to all devices through the trunk to the first control input 35 of the setting checker through the inputs- the outputs 14 and 18 of the switching unit; the Ka second control input 30 of the checking unit receives a sign of the setting from the output 27 of the setting unit. Inputs 25 and 30 are connected to the first and second inputs of the element E 99, the output of which is connected to the computer room switchboard 100, from the corresponding output of which the sign of tuning to information output 31 of the setting check block is detected and then through the second information input 21 and system information input-output 12 of the switching unit to the trunk.

Thus, on the system information input-output 12 of the switching unit of the tuning computer, a response address word is assembled, each bit of which corresponds to a really established feature of the setting. The response address word through the inputs-outputs P2 and 1 7 of the switching unit is fed to the information input 34 of the setting verification unit and to the first input of the comparison element 10. The microprogram control unit again reads the address word from the computer RAM, similarly to that described, and installs it from the information bus 16 of the computer to the second information input 32 and then to the second input of the comparison checker unit 1.01. At the output of the comparison element 101 and at the output 33 of the Tuning block of the setting, the sign of checking the tuning appears, which is fed to the input 52 of the signs of the firmware control block.

If the check sign is passive, then block 6 sequentially sets on its output 46 signals Error, Done, Interrupt. The error signal is fed to the input 54

of the status register and sets the trigger 111 to the unit. The Ready signal also enters the input 54 of the status register and sets the trigger 112 to the unit. The Interrupt signal enters input 80 of the interrupt unit and sets the trigger trigger to the unit 137. The single signal from the output of the trigger 137 arrives on one of the inputs of the element I 139, on the other input of which the prereggoi resolution signal is received from the sixth bit of the register of 1 09 commands.

5 If the test flag is active, the firmware control unit changes the contents of the current address register to two, subtracts one from the command counter and cycles to Denmark's synchronization flag.

In receiving computers, the adjustment is as follows. In the informational input 29 € of the settings area, the address word is set,

5 coming through the inputs-outputs 1 2 and 17 of the switching unit. From the input 29, the information enters the inputs of the switch 97 and further to the D input of the trigger 98 of the setting. Switch 97 is installed

0 to the position corresponding to the computer number. System signal Setting via the inputs-outputs 13 and 19 of the switching unit and the input 26 of the setting unit enters the synchronous input of the trigger 98 and

g sets it to the position corresponding to the information input of trigger 98. At output 27 of the tuner, an active state is set. The receiving computer microprogramme control unit 6 is cycling while waiting for a setting feature and, in the event of an activity of a given feature coming from the output 27 of the tuner, to the input 51 of the signs, sets the interrupt signal at the output 46 of the block 6. The interrupt signal is fed to the 80 input of the unit 1 1 interrupts and sets trigger 137 to one. At control output 83,

0 is an interrupt request signal (TPR), arriving at a group of inputs-outputs 15 in a computer. The computer responds to the Input and Provision Interrupt (PRL) signals. by group of inputs and outputs 15

5 of the computer. The input signal is thrown from the group of inputs and outputs 15 and input .. 84 to the synchronous input of the trigger 136 and sets it to one, the signal from the output of the trigger 136 goes to the first

input element K 138, and the second input element AND 138 receives a signal PPr, which also enters the permitting inputs of elements 140, passes the address-interrupt vector, set by jumpers, through information output 82 to a group of inputs-outputs 16 in the computer.

The computer, having received a fault, loads the command for receiving into the command register into its device, the RAM address in the register of the current address — the address of the RAM where the nyu write the data of the service tuning block (NSS); the word counter — the size of the NSS.

The first step in executing this command is the installation and the synchronization signal to the system backbone.

The receiving computers, when resetting the synchronization feature, activate the operation of the direct access unit 10 and transmit data from the transceiver register 9 to the computer RAM at the address of the current address register in the same way as described. Next, receiving computers change the contents of the current address and word count registers. Signals -t-2 and -1 appear at control output 46, which arrive at input 72, increase the contents of register 124 by two, and decrease the contents of counter 123 by one.

The transmitting computer, when resetting the synchronization feature, performs similar actions. In the same way, an active computer transmits the following words of service

ten

At the control output 46 of the micro block, 20 tuning words. Transmission

continues until counter 123 in the direct access block is reset. A negative signal appears at the output of the 1-meter signal. The end of the cyctrigger 104, and a single value of 25 la (KP), which through the output 75 of the register output, through the output 42 of the direct access step, enters

Firmware control input 49, after analyzing the state of which, the firmware block When all the configured computers, the control department completes the Setup command by setting the Ready and Breaking signals to output 6 of the block 6. Signal Done enters

the program control, a synchronization signal (syn) appears, which, through the input 43 of the synchronization register 5, is fed to the setup input

goes to the system trunk through the inputs-outputs 23 and 13 of the switching unit.

The variables in this interaction set their triggers 104 to one, the transmitting computer produces the output of the second word of the SNB. At that, the microprogram control unit 6 initiates g

micro operation Direct access-input, terminus Received at input 80 as a result of which data from the information bus 16 and the signal Exchange from the JW-JQ of the firmware block 46 are transmitted to the channel information input 25 and control input 24. Signal Exchange through the inputs / outputs 24 and 13 of the switching unit enters through the trunk to all devices and then in each device through 45 inputs-outputs 13 and 18 of the switching unit to the synchronous inputs 68 and 44 of the transceiver register 9 and synchronization register 5, the latter is set to zero. Data

from the inputs-outputs 12 and 1 7 come on. The gQ to this receiving computer is placed into the regional information input 69 of the register 9 of the current address address of the RAM address, on the radio, and stored in the register input 54 of the status register and sets the trigger 111 to one. Sigblock interrupt, which causes the computer to crash, together with the completion of the Settings command.

The execution of the Transfer command is similar to the execution of the Setup command, starting with the transfer of the second word of the control word.

Execution of the Receive command.

In the course of executing the Setup command, a service tuning block was transmitted to the receiving computer, which contained information about the size of the transmitted array from the transmitting computer. The data will be received, and the word count will be the size of the array corresponding to the data from the service setup J23 with the arrival of the signal Obm. All computers involved in this interaction

are in the state of analysis

the synchronization feature coming from the output 42 of the synchronization register to the input 53 of the features of the microprogram control unit 6.

The receiving computers, when resetting the synchronization feature, activate the operation of the direct access unit 10 and transmit data from the transceiver register 9 to the computer RAM at the address of the current address register in the same way as described. Next, receiving computers change the contents of the current address and word count registers. Signals -t-2 and -1 appear at control output 46, which arrive at input 72, increase the contents of register 124 by two, and decrease the contents of counter 123 by one.

The transmitting computer, when resetting the synchronization feature, performs similar actions. In the same way, an active computer transmits the following words of service

at input 54 of the state register and sets the trigger 111 to one. Signal Termination arrives at input 80

interrupt unit that crashes the computer, informing about the completion of the Settings command.

The execution of the Transfer command is similar to the execution of the Setup command, starting with the transfer of the second word of the control word.

Execution of the Receive command.

In the course of executing the Setup command, a service tuning block was transmitted to the receiving computer, which contained information about the size of the transmitted array from the transmitting computer. Therefore, receiving computers, - are in the registers of the current address of the address of the RAM,

Yes, the data will be received, and the word count is the size of the array corresponding to the data from the service settings of the block.

The implementation of a generalized unconditional transition (AEC).

The generic unconditional transition is to stop all attitudes. 15 145696316

computer and in the reception of the main line of the generalized conditional redirection of the transition in the executed EVMhoda. programs. Computer manufacturing procedure

Claims (2)

BOOL using the Transmit command, the Invention Form sends the service data block, the first word of which is the operation code1. The device for interfacing the computer OBOOL, the second - the address of the transition, For you - with the common highway containing the complement of the operation of the OBOUL is used the switching, the setting unit, the command Transmission. generalized conditional transition, re- Implementation of the generalized conditional convention, the register transceiver-. transition consists in the development of an all-dacha, block of prereshans, with the first configured by the computer hardware prize-second, one-third of the information group of the generalized conditional transition. the input-output of the switching unit is processed. In all computers, private ulo-15 z are loaded. I / O device. At the address of the generalized unit for connecting the LUMBLE transition of a computer through a group of information, control input / output buses 16, respectively, outputs the private bus and control signal busses (0 or 1) coming through the main line, which is different from input 37 of unit 4. The generalized transition 20 is aimed at fast D-input. the trigger 102 is privately activated; a check block is entered into it. The gating input of the trigger setup, the synchronization register, ra 102 via input 38 of block 4 and you microprogram control block, move 61 of the decoder 8 receives the address decoder, the block of the pre-impulse recording of the particular condition. A Cig-25 stupa to the memory, the first from the output of the trigger 102 of the private information inputs of the commutation block through the output 36 of the 4 post office block, the first information inputs falling into the system trunk through the input-block of the configuration check and the general block Inputs 22 and 13 of the switching unit. A conditional transition group The computer displays the command code Vyrabat-ZO of the information inputs of the descriptor of the conditional transition of the time entry and the block of direct access to the register of 109 commands. Block 6 starts, groups of information outputs from the micro-operation of the synchronization-state register, the reception register. All the configured computers of the transfer-unit, the pre-blocking unit, the unit direct their triggers 104 into a single memory access, the first group of states, as evidenced by the inputs of the logic condition of the unit, control input 53 of block 6. At the control output-group of device I / O for block 46, block 6, the Out-connection signal to the group of information letters of the generalized condition (CpOU) appears, the co-40 computer input-outputs, the control group enters input 39 and onwards to our inputs and the outputs of the fail-over block, the synchronous input of the trigger 103. On the D-input group of control outputs and the first triggers 103 a generalized group of control inputs of the pr block is set, which is a conjuncture of access to memory, a group of control-all private conditions, set loops and group of exits by de-tuned computers. The generic attribute of the address coder form a group that passes from the I / O, 13 and 18 I / O of the device to the sub-block of the switching unit 1 to the input of the unit 4 ,. The control signal group sets the trigger of the computer input triggers, while the first group of the generalized condition, in accordance with gQ information inputs of the unit, is communicating with the D input. From the output, it is connected to the group of information trigger 103 through the informational outputs of the tuning unit, with the input 40 the signal of the generalized information input of the transition unit enters input 58 of the setting register, with the status information group 7. Block 6 of the microprogrammed gg entries of the transceiver register completes the execution of the gate, the gate of which is input, the commands by setting the signal. The first input of the logical condition blb and interrupt is ready. The computer, reading the contents of the firmware control, stan-state register, can determine the synchronization register input, the second information input of the generalized conditional transition block, the first control input of the tuning check block are connected to the second group of information blocks of the switching block, respectively, the output of the tuning signal of which is connected with the tuning unit input, the output of the setting attribute of which is connected, Q is dinine with the input of the setting attribute of the switching unit, with the second control input tuning control unit and with the second inputs of the logic condition of the firmware control unit, the first group of outputs of which is connected to the control inputs group of the switching unit, with the setup input of the tuning unit, with the first strobing input of the general conditional transition unit, with a group of sync-inputs of the state register, with gating inputs of the intermittent transition unit, with the reading input of the state register, with the first and second gating inputs of the block direct to stupa to memory. 2. The device according to claim 1, wherein the setting unit comprises a switch and a trigger, wherein the group of information inputs of the switch forms the group of information inputs of the block, the single output, the synchronous input and the single output of the trigger, respectively the installation inputs, the synchronous input and 15 by the output of the block setting feature, while in the tuning block the informational OUTPUT of the switch is connected to the information input of the trigger. 3, the apparatus according to claim, characterized in that the setting verification unit comprises a switch, an element K, a comparison element, the first and second inputs of the AND element being the first and second respectively. nor, with the register reading input, the receiving inputs, the control unit, the first and the second inputs of the comparison element are respectively the first and second information inputs of the block, the group of information outputs of the commutation transfer, with the second group of control inputs of the direct memory access block, the group of outputs of the characteristics of which are connected to the second group of inputs of the logical condition block of the microprogram 30 calls a group of information program control, the third moves of the block, the output of the comparison element is the output of the sign of the setting check, while in the check block of the setting of the output of the element K the logical condition move - which is connected with the information inputs of the synchronization register and with the first information inputs of the switching unit, the second group of information inputs of which are connected to the information output group of the setting checker, the output of the check sign 2g dinen with information input of the switch, 4, The device according to claim 1, characterized by the fact that the montage unit of which is connected to the fourth to 40th memory access contains a register. The second input of the logic condition of the firmware control block, the second group of outputs of which is connected respectively to the resolution input of the breakout unit and the group of information inputs of the status register, whose information input is connected to the output of the generalized condition block of the generalized conditional transition, the output of which is connected to the second information input of the switching unit, the synchronous input of the microprogram control unit is connected to the setup input of the status register and to the first one the output of the address decoder, the second, third, fourth, fifth outputs of which are connected respectively to the second building block input of the generalized counter, the group of elements AND, five triggers, two elements K, the element OR, two elements of delay, and the group of information inputs of the register 45 Pa and the counter form a group of information inputs of the block, the outputs of elements And groups form a group of information outputs of the block, the gate inputs of the counter and the register are 50, respectively, the first and second.; gating inputs of the block, the first input of the OR element, the input of the first delay element, the synchronous input of the first trigger connected to the input of the second delay element, representing the first group of control inputs of the block, the first inputs of AND elements of the group, the input of two registers, the input counter, zero input Q a junction with the read input of the state register, with the first and second gating inputs of the direct memory access unit. 2. The device according to claim 1, wherein the setting unit comprises a switch and a trigger, wherein the group of information inputs of the switch forms the group of information inputs of the block, the single output, the synchronous input and the single output of the trigger, respectively the installation inputs, the synchronous input and 5 by the output of the block setting feature, while in the tuning block the informational OUTPUT of the switch is connected to the information input of the trigger. 3, the apparatus according to claim 1, wherein the setting verification unit comprises a switch, an element K, a comparison element, the first and second inputs of the AND element being the first and second respectively. the second inputs of the comparison element are respectively the first and second information inputs of the block, the group of information outputs of the switch forms a group of information outputs of the block, the output of the comparison element is the output of the sign of the configuration check, while in the configuration check block the output of the element K is connected with information switch input, 4, The device according to claim 1, characterized by in that the direct memory access block contains a register. a counter, a group of elements AND, five triggers, two elements K, an element OR, two delay elements, the groups of information inputs of the register 45 and the counter form a group of information inputs of the block, the outputs of elements AND of the group form a group of information outputs of the block gating the inputs of the counter and register are 50, respectively, the first and second.; gating inputs of the block, the first input of the OR element, the input of the first delay element, the synchronous input of the first trigger connected to the input of the second delay element, representing the first group of control inputs of the block, the first inputs of AND elements of the group, the input of two registers, the input counter, zero input nineteen 1456963 the first trigger connected to the zero input of the second trigger and the first input of the first element I, the sync inputs of the third, fourth and sixth trigger form the second group of control inputs of the block, the output of the first and second elements I, the single outputs of the third, fourth, fifth, right iggers, a single output of the second trigger, connected to the zero input of the third trigger, form a group of control blocks of the block, the output of the counter and a single output of the second trigger form a group of outputs of the block signs, while in the block directly a memory access of the second input of the first AND element is connected to zero 20 the output of the second trigger, the sync input of which is connected to the output of the OR element, the second input of which is connected to the single output of the first trigger, the zero output of which is connected to the BbiM input of the second element And, the second input of which is connected to the output of the second delay element with zero inputs of the fourth and fifth trigger, the group of information outputs of the register is connected to the second inputs of the elements of the AND group, the information inputs of the first, second, third, fourth, and fifth trigger in connected to the bus unit capacity of the device. 1 f / e.S 3 V LO I: E Fi.6 t ttsm so with uH. syst. SI Hacmt). 5Z Trial, tuning Reg, ein. S3 FIG. 7 i 7 8 71 Phi ".8 Thebes. S 70 Thebes. Jl -; / 2J / Sia Adp W 5G Lt3 - SB r-of l with QnSfn 135 72 7 JO /ABOUT 7 75 125 /five/ Y / 7 / If L / 27 / Jf Pprv ( t l Conclusion / g 7  77